CN118588704B - Semiconductor device and method for manufacturing the same - Google Patents
Semiconductor device and method for manufacturing the same Download PDFInfo
- Publication number
- CN118588704B CN118588704B CN202411074990.3A CN202411074990A CN118588704B CN 118588704 B CN118588704 B CN 118588704B CN 202411074990 A CN202411074990 A CN 202411074990A CN 118588704 B CN118588704 B CN 118588704B
- Authority
- CN
- China
- Prior art keywords
- dielectric layer
- layer
- conductive
- bonding
- conductive layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 271
- 238000000034 method Methods 0.000 title claims abstract description 35
- 238000004519 manufacturing process Methods 0.000 title claims description 18
- 150000002500 ions Chemical class 0.000 claims abstract description 26
- 230000003068 static effect Effects 0.000 claims abstract description 18
- 230000005611 electricity Effects 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims description 262
- 238000002955 isolation Methods 0.000 claims description 87
- 229910052751 metal Inorganic materials 0.000 claims description 39
- 239000002184 metal Substances 0.000 claims description 39
- 230000008569 process Effects 0.000 claims description 16
- 239000000463 material Substances 0.000 claims description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 12
- 229910052710 silicon Inorganic materials 0.000 claims description 12
- 239000010703 silicon Substances 0.000 claims description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- 238000000137 annealing Methods 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 8
- 239000004020 conductor Substances 0.000 claims description 6
- 238000011049 filling Methods 0.000 claims description 5
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- 230000007547 defect Effects 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 4
- 238000005468 ion implantation Methods 0.000 claims description 3
- 229910021645 metal ion Inorganic materials 0.000 claims description 3
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 3
- 230000008439 repair process Effects 0.000 claims description 3
- 239000003990 capacitor Substances 0.000 abstract description 19
- 230000000694 effects Effects 0.000 abstract description 11
- 230000008054 signal transmission Effects 0.000 abstract description 6
- 230000005684 electric field Effects 0.000 abstract description 4
- 230000005641 tunneling Effects 0.000 abstract description 4
- 239000010410 layer Substances 0.000 description 422
- 238000010586 diagram Methods 0.000 description 20
- 235000012431 wafers Nutrition 0.000 description 10
- 238000002360 preparation method Methods 0.000 description 7
- 230000005540 biological transmission Effects 0.000 description 5
- 238000009826 distribution Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- JPVYNHNXODAKFH-UHFFFAOYSA-N Cu2+ Chemical compound [Cu+2] JPVYNHNXODAKFH-UHFFFAOYSA-N 0.000 description 4
- -1 aluminum ions Chemical class 0.000 description 4
- 229910001431 copper ion Inorganic materials 0.000 description 4
- 239000003989 dielectric material Substances 0.000 description 3
- 230000001939 inductive effect Effects 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- 239000005360 phosphosilicate glass Substances 0.000 description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 239000005388 borosilicate glass Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910005540 GaP Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 230000005496 eutectics Effects 0.000 description 1
- 230000004927 fusion Effects 0.000 description 1
- HZXMRANICFIONG-UHFFFAOYSA-N gallium phosphide Chemical compound [Ga]#P HZXMRANICFIONG-UHFFFAOYSA-N 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 description 1
- 230000005693 optoelectronics Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Landscapes
- Semiconductor Integrated Circuits (AREA)
Abstract
本发明提供了一种半导体器件及其制备方法，第一导电层、第二导电层及两者之间的介电层构成的三明治结构可以等效为电容，电容的一个极板接地，另一个极板连接第一互联结构，正常情况下，电容可以将第一互联结构与地隔开，不影响第一互联结构上的信号传输，当第一互联结构接收到异常高压（静电）时，在强电场下，介电层中的导电离子被激活，在电容的两个极板之间形成通道，利用电子隧穿效应将静电快速导入地，实现静电防护作用。第一导电层、介电层及第二导电层在介质层中是堆叠着的，能够减少静电防护结构的版图面积，不会过多占用布线资源，为器件提供性能、功耗和面积方面的优势。
The present invention provides a semiconductor device and a method for preparing the same. A sandwich structure composed of a first conductive layer, a second conductive layer and a dielectric layer therebetween can be equivalent to a capacitor. One plate of the capacitor is grounded, and the other plate is connected to a first interconnect structure. Under normal circumstances, the capacitor can separate the first interconnect structure from the ground without affecting signal transmission on the first interconnect structure. When the first interconnect structure receives abnormally high voltage (static electricity), the conductive ions in the dielectric layer are activated under a strong electric field, forming a channel between the two plates of the capacitor, and using the electron tunneling effect to quickly introduce static electricity into the ground, thereby achieving electrostatic protection. The first conductive layer, the dielectric layer and the second conductive layer are stacked in the dielectric layer, which can reduce the layout area of the electrostatic protection structure, will not occupy too much wiring resources, and provide the device with advantages in performance, power consumption and area.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor device and a preparation method thereof.
Background
Electrostatic discharge (Electrostatic Discharge, ESD) is a major contributor to excessive electrical stress damage to Integrated Circuits (ICs), and with the rise of three-dimensional integrated circuit (3D IC) technology, the design of electrostatic protection structures for three-dimensional stacked semiconductor devices has also become particularly important.
Dense power transmission and signal transmission are needed between wafers or between chips in the three-dimensional stacked semiconductor device, wiring resources are tense, and the existing electrostatic protection structure needs to occupy a large amount of layout area, so that the problem of IC layout is caused. Therefore, with the improvement of the chip process node and the development of 3D IC technology, the electrostatic protection structure in the three-dimensional stacked semiconductor device needs to be improved.
Disclosure of Invention
The invention aims to provide a semiconductor device and a preparation method thereof, which are used for solving the problem that the conventional electrostatic protection structure occupies a large layout area, so that the problem of IC layout is solved.
In order to achieve the above object, the present invention provides a semiconductor device, which comprises at least two stacked semiconductor substrates, wherein each semiconductor substrate is provided with a metal layer therein, and the metal layers in two adjacent semiconductor substrates are electrically connected through a first interconnection structure; and
A dielectric layer is arranged between two adjacent semiconductor substrates, an electrostatic protection structure is formed in at least part of the dielectric layers, the electrostatic protection structure comprises a first conductive layer and a second conductive layer which are stacked, each of the first conductive layer and the second conductive layer is at least one, each first conductive layer is grounded, a dielectric layer is arranged between each second conductive layer and at least one first conductive layer, conductive ions are doped in each dielectric layer, and each second conductive layer in the dielectric layer is electrically connected with the corresponding first interconnection structure.
Optionally, the first conductive layers and the second conductive layers are in one-to-one correspondence, and the dielectric layers are arranged between the second conductive layers and the corresponding first conductive layers.
Optionally, the dielectric layer is disposed between each of the second conductive layers and each of the first conductive layers.
Optionally, the material of the dielectric layer is silicon oxynitride, aluminum oxide, silicon nitride or silicon oxide.
Optionally, the conductive ion is a metal ion or a semiconductor ion.
Optionally, the dielectric layer includes stacked isolation dielectric layers and bonding dielectric layers, the first conductive layer and the dielectric layer are located in the isolation dielectric layers, the second conductive layer is located between the isolation dielectric layers and the bonding dielectric layers, the dielectric layers are in direct contact with the corresponding first conductive layer and the corresponding second conductive layer, and the dielectric layers and the corresponding first conductive layer and the corresponding second conductive layer have overlapping areas in a thickness direction along the semiconductor substrate.
Optionally, the first interconnection structure includes a first plug and a bonding pad pair, where the first plug is located in the isolation dielectric layer and the corresponding semiconductor substrate, the first plug is electrically connected with the second conductive layer in the dielectric layer and the corresponding metal layer in the semiconductor substrate, and the bonding pad pair is located in the bonding dielectric layer and is electrically connected with the corresponding second conductive layer and the metal layer.
Optionally, the first conductive layer in the dielectric layer is grounded through a second interconnection structure, the second interconnection structure includes a third conductive layer and a second plug, the third conductive layer is located between the isolation dielectric layer and the bonding dielectric layer, and the third conductive layer is grounded, and the second plug is located in the isolation dielectric layer and is electrically connected with the third conductive layer and the corresponding first conductive layer.
Optionally, one of the semiconductor substrates in the semiconductor device is a logic substrate, the other semiconductor substrates are device substrates, the logic substrate is located at the outermost side of all the semiconductor substrates, and the dielectric layer between at least the logic substrate and the device substrates has the electrostatic protection structure.
The invention also provides a preparation method of the semiconductor device, which comprises the following steps:
providing at least two semiconductor substrates, wherein each semiconductor substrate is internally provided with a metal layer;
All the semiconductor substrates are stacked together, the metal layers in two adjacent semiconductor substrates are electrically connected through a first interconnection structure, a dielectric layer is arranged between the two adjacent semiconductor substrates, an electrostatic protection structure is formed in at least part of the dielectric layers, the electrostatic protection structure comprises stacked first conductive layers and second conductive layers, at least one first conductive layer is grounded, a dielectric layer is arranged between each second conductive layer and at least one first conductive layer, conductive ions are doped in each dielectric layer, and the second conductive layers in the dielectric layers are electrically connected with the corresponding first interconnection structures.
Optionally, when stacking all the semiconductor substrates, stacking a next semiconductor substrate on a previous semiconductor substrate in turn, when stacking two adjacent semiconductor substrates, forming an isolation medium layer, a first plug, the electrostatic protection structure and a first hybrid bonding structure on the previous semiconductor substrate, forming a second hybrid bonding structure on the next semiconductor substrate, and bonding the next semiconductor substrate to the previous semiconductor substrate by using the first hybrid bonding structure and the second hybrid bonding structure;
The first plug is positioned in the isolation dielectric layer and the corresponding semiconductor substrate and is electrically connected with the metal layer in the corresponding semiconductor substrate and the second conductive layer in the dielectric layer; the electrostatic protection structure is integrally positioned in the isolation medium layer; the first hybrid bonding structure is positioned on the isolation dielectric layer and the static electricity protection structure, and comprises a first bonding dielectric layer and a first bonding pad positioned in the first bonding dielectric layer, the first bonding pad is electrically connected with the corresponding second conductive layer, the second hybrid bonding structure comprises a second bonding dielectric layer and a second bonding pad positioned in the second bonding dielectric layer, and the second bonding pad is electrically connected with the corresponding metal layer; the isolation dielectric layer, the first bonding dielectric layer and the second bonding dielectric layer form the dielectric layer, and the first plug, the first bonding pad and the second bonding pad form the first interconnection structure.
Optionally, when stacking all the semiconductor substrates, stacking a second semiconductor substrate on a first semiconductor substrate, stacking a next semiconductor substrate on a previous semiconductor substrate in turn, and when stacking two adjacent semiconductor substrates, forming an isolation medium layer, a first plug, the electrostatic protection structure and a first hybrid bonding structure on the next semiconductor substrate, and forming a second hybrid bonding structure on the previous semiconductor substrate, and bonding the previous semiconductor substrate on the next semiconductor substrate by using the first hybrid bonding structure and the second hybrid bonding structure;
The first plug is positioned in the isolation dielectric layer and the corresponding semiconductor substrate and is electrically connected with the metal layer in the corresponding semiconductor substrate and the second conductive layer in the dielectric layer; the electrostatic protection structure is integrally positioned in the isolation medium layer; the first hybrid bonding structure is positioned on the isolation dielectric layer and the static electricity protection structure, and comprises a first bonding dielectric layer and a first bonding pad positioned in the first bonding dielectric layer, the first bonding pad is electrically connected with the corresponding second conductive layer, the second hybrid bonding structure comprises a second bonding dielectric layer and a second bonding pad positioned in the second bonding dielectric layer, and the second bonding pad is electrically connected with the corresponding metal layer; the isolation dielectric layer, the first bonding dielectric layer and the second bonding dielectric layer form the dielectric layer, and the first plug, the first bonding pad and the second bonding pad form the first interconnection structure.
Optionally, the step of forming the isolation dielectric layer, the first plug and the electrostatic protection structure on the semiconductor substrate includes:
forming the isolation dielectric layer on the semiconductor substrate, and forming the first conductive layer in the isolation dielectric layer;
etching the isolation dielectric layer and the semiconductor substrate to form a first contact hole exposing the metal layer;
filling conductive material in the first contact hole to form the first plug;
etching the isolation medium layer to form an opening exposing the corresponding first conductive layer;
forming the dielectric layer within the opening; and
And forming the second conductive layer on the isolation dielectric layer, wherein the second conductive layer covers the dielectric layer and the first plug correspondingly.
Optionally, after forming the dielectric layer, implanting the conductive ions into the dielectric layer by an ion implantation process.
Optionally, after forming the second conductive layer, the preparation method further includes:
performing a first annealing process to infiltrate conductive ions at an interface of the dielectric layer and the second conductive layer into the dielectric layer; and
And performing a second annealing process to repair the defects of the second conductive layer.
Optionally, after the first plug is formed, before the isolation medium layer is etched to form the opening, the preparation method further includes:
Etching the isolation medium layer to form a second contact hole, wherein the second contact hole exposes the corresponding first conductive layer;
Filling conductive material in the second contact hole to form a second plug; and
And when the second conductive layer is formed, a third conductive layer is further formed on the isolation dielectric layer, the third conductive layer is used for grounding, and the third conductive layer is electrically connected with all the second plugs.
The semiconductor device and the preparation method thereof provided by the invention have the following beneficial effects: the sandwich structure formed by the first conductive layer, the second conductive layer and the dielectric layer between the first conductive layer and the second conductive layer can be equivalent to a capacitor, one polar plate of the capacitor is grounded, the other polar plate is connected with the first interconnection structure, under normal conditions, the capacitor can separate the first interconnection structure from the ground without influencing signal transmission on the first interconnection structure, when the first interconnection structure receives abnormal high voltage (static), conductive ions in the dielectric layer are activated under a strong electric field, a channel is formed between the two polar plates of the capacitor, and the static is quickly guided into the ground by utilizing an electron tunneling effect, so that a static protection effect is realized; and the first conductive layer, the dielectric layer and the second conductive layer are stacked in the dielectric layer, so that the layout area of the electrostatic protection structure can be reduced, wiring resources are not excessively occupied, metal congestion is reduced, noise and inductive parasitic in a transmission path formed by the first interconnection structure are reduced, the reliability of a device is improved, and advantages in performance, power consumption and area are provided for the device.
Drawings
Fig. 1 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention;
Fig. 2 to fig. 13 are flowcharts corresponding to respective steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention, where:
fig. 2 is a schematic structural diagram of a semiconductor substrate according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of forming a second hybrid bonding structure on a front surface of a first semiconductor substrate according to a first embodiment of the present invention;
fig. 4 is a schematic structural diagram of a support substrate bonded to the front surface of a second semiconductor substrate according to an embodiment of the present invention;
Fig. 5 is a schematic structural diagram of forming an isolation dielectric layer and a first conductive layer on a back surface of a second semiconductor substrate according to a first embodiment of the present invention;
FIG. 6 is a schematic diagram illustrating a structure of forming a first plug and a second plug in an isolation dielectric according to an embodiment of the present invention;
fig. 7 is a schematic structural diagram of forming a dielectric layer in an isolation dielectric layer according to a first embodiment of the present invention;
Fig. 8 is a schematic structural diagram of forming a second conductive layer and a third conductive layer on an isolation dielectric layer according to a first embodiment of the present invention;
Fig. 9 is a schematic structural diagram of forming a first hybrid bonding structure on an isolation dielectric layer according to a first embodiment of the present invention;
fig. 10 is a schematic structural diagram of bonding a front surface of a first semiconductor substrate to a back surface of a second semiconductor substrate according to a first embodiment of the present invention;
FIG. 11 is a schematic diagram of a structure for removing a supporting substrate and a temporary bonding layer according to an embodiment of the invention;
fig. 12 is a schematic structural diagram of forming a second hybrid bonding structure on a front surface of a second semiconductor substrate according to a first embodiment of the present invention;
Fig. 13 is a schematic structural diagram of a semiconductor device according to a first embodiment of the present invention;
Fig. 14 is a schematic diagram showing the distribution of the first conductive layer, the second conductive layer and the dielectric layer according to the first embodiment of the present invention;
fig. 15 to 17 are flowcharts corresponding to respective steps of a method for manufacturing a semiconductor device according to the second embodiment of the present invention, where:
Fig. 15 is a schematic structural diagram of bonding a second semiconductor substrate to a first semiconductor substrate according to a second embodiment of the present invention;
Fig. 16 is a schematic diagram of a structure of bonding a third semiconductor substrate to a second semiconductor substrate according to a second embodiment of the present invention;
fig. 17 is a schematic structural diagram of a semiconductor device according to a second embodiment of the present invention;
fig. 18 is a schematic diagram showing the distribution of the first conductive layer, the second conductive layer and the dielectric layer according to the third embodiment of the present invention;
wherein, the reference numerals are as follows:
10-a semiconductor substrate; 11-a substrate; 12-an insulating layer; 13-a metal layer; 20-supporting a substrate; 21-a temporary bonding layer; 31-isolating the dielectric layer; 32-a first bonding medium layer; 33-first bond pads; 34-a second bonding medium layer; 35-a second bond pad; 41-a first conductive layer; 42-a second plug; 43-dielectric layer; 44-a second conductive layer; 45-a third conductive layer; 50-first plug.
Detailed Description
Specific embodiments of the present invention will be described in more detail below with reference to the drawings. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.
Example 1
Fig. 13 is a schematic structural diagram of the semiconductor device provided in this embodiment. As shown in fig. 13, the semiconductor device includes at least two stacked semiconductor substrates 10, 3 of which semiconductor substrates 10 are schematically shown in fig. 13, and the other semiconductor substrates 10 are replaced in the form of ellipses in fig. 13.
Each of the semiconductor substrates 10 includes a substrate 11 and an insulating layer 12 disposed on a first surface of the substrate 11, wherein a device structure is disposed on the first surface of the substrate 11, and a metal layer 13 electrically connected to the device structure is formed in the insulating layer 12, and the device structure may be an active device (e.g., a transistor, a diode, a triode, etc.), a passive device (e.g., a capacitor, a resistor, an inductor, etc.), etc., or a combination thereof.
The material of the substrate 11 may be a semiconductor material, glass, ceramic, or other material, and when the material of the substrate 11 is a semiconductor material, may include, but is not limited to, doped or undoped silicon, doped or undoped germanium, semiconductor-on-insulator (SOI), silicon carbide, gallium arsenide, gallium phosphide, indium arsenide and/or indium antimonide, siGe, gaAsP, alInAs, alGaAs, gaInAs, gaInP and/or GaInAsP, or the like, or combinations thereof. The semiconductor substrate 10 may have a wafer-level size or a chip-level size, for example, the semiconductor substrate 10 may be a wafer or a chip such as an optoelectronic wafer/chip, a biological wafer/chip, a memory wafer/chip, a logic wafer/chip, a computing wafer/chip, or the like. The semiconductor device in the present embodiment is illustratively a combination of one logic chip and a plurality of memory chips.
The insulating layer 12 may comprise a single layer or a multi-layer film, and the material may include, but is not limited to, a low-k dielectric material, phosphosilicate glass (PSG), borosilicate glass (BSG), boron doped phosphosilicate glass (BPSG), undoped Silicate Glass (USG), silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, carbon doped silicon dioxide, or the like.
In this embodiment, the side of the semiconductor substrate 10 corresponding to the insulating layer 12 is the front side (i.e., the side where the insulating layer 12 is exposed), and the side corresponding to the substrate 11 is the back side (i.e., the second surface of the substrate 11). When two adjacent semiconductor substrates 10 are stacked, the front surface of one semiconductor substrate 10 is bonded to the back surface of the other semiconductor substrate 10.
Further, the metal layers 13 in two adjacent semiconductor substrates 10 are electrically connected through a first interconnection structure for signal transmission or power transmission. A dielectric layer is disposed between two adjacent semiconductor substrates 10, and an electrostatic protection structure is formed in at least a part of the dielectric layers.
The electrostatic protection structure includes stacked first conductive layers 41 and second conductive layers 44, where each of the first conductive layers 41 and the second conductive layers 44 has at least one, each of the first conductive layers 41 is grounded, a dielectric layer 43 is disposed between each of the second conductive layers 44 and at least one of the first conductive layers 41, each of the dielectric layers 43 is doped with conductive ions, and all of the second conductive layers 44 in the dielectric layer are electrically connected with the corresponding first interconnection structure. The sandwich structure formed by the first conductive layer 41, the second conductive layer 44 and the dielectric layer 43 therebetween may be equivalently a capacitor, one plate of the capacitor is grounded, the other plate is connected to the corresponding first interconnection structure, the capacitor may normally separate the first interconnection structure from ground, and does not affect signal transmission on the first interconnection structure, when the first interconnection structure receives abnormally high voltage (static electricity), under a strong electric field, conductive ions in the dielectric layer 43 are activated, a channel is formed between the two plates of the capacitor, and the static electricity is quickly guided to ground by using an electron tunneling effect, thereby realizing a static electricity protection effect. The first conductive layer 41, the dielectric layer 43 and the second conductive layer 44 are stacked in the dielectric layer in sequence, so that the layout area of the electrostatic protection structure can be reduced, wiring resources are not excessively occupied, metal congestion is reduced, noise and inductive parasitics in a transmission path formed by the first interconnection structure are reduced, the reliability of a device is improved, and advantages in performance, power consumption and area are provided for the device.
In this embodiment, the electrostatic protection structure is formed in each dielectric layer, so as to have a relatively strong electrostatic protection effect, but the electrostatic protection effect is not limited thereto, and only a part of the dielectric layers may have the electrostatic protection structure. In general, one of the semiconductor substrates 10 in the semiconductor device is a logic substrate (logic wafer or logic chip), and the other semiconductor substrates 10 are device substrates (device wafer or device chip), and the logic substrate is located at the outermost side of all the semiconductor substrates 10, and since the difference between the logic substrate and the device substrate is large, at least the electrostatic protection structure may be disposed in the dielectric layer between the logic substrate and the device substrate, and of course, the electrostatic protection structure may also be disposed in the dielectric layer between two adjacent device substrates, thereby improving the electrostatic protection effect.
Further, the dielectric layers include stacked isolation dielectric layers 31 and bonding dielectric layers, in this embodiment, for two adjacent semiconductor substrates 10, the isolation dielectric layers 31 are attached to the back surface of one of the semiconductor substrates 10, and the bonding dielectric layers are attached to the front surface of the other semiconductor substrate 10.
Specifically, the first conductive layer 41 and the dielectric layer 43 are both located in the isolation dielectric layer 31, the dielectric layer 43 is closer to the bonding dielectric layer than the first conductive layer 41, and at least part of the surface of the dielectric layer 43 needs to be exposed out of the isolation dielectric layer 31; the second conductive layer 44 is located between the isolation dielectric layer 31 and the bonding dielectric layer, and covers the surface of the dielectric layer 43 exposed from the isolation dielectric layer 31. Also, the dielectric layer 43 is in direct contact with each of the respective first conductive layer 41 and the second conductive layer 44, and each of the dielectric layer 43 and the respective first conductive layer 41 and the second conductive layer 44 has an overlapping region in the thickness direction of the semiconductor substrate 10, and in fact, the dielectric layer 43 is located in the overlapping region of the first conductive layer 41 and the second conductive layer 44 in the thickness direction of the semiconductor substrate 10. In this way, the first conductive layer 41, the second conductive layer 44, and the dielectric layer 43 therebetween can be equivalent to a capacitance, and an effective area of the capacitance is an overlapping area of the dielectric layer 43, the first conductive layer 41, and the second conductive layer 44 in the thickness direction of the semiconductor substrate 10.
Further, the conductive ions doped in the dielectric layer 43 may be metal ions, such as copper ions, aluminum ions, etc.; the conductive ions doped in the dielectric layer 43 may also be semiconductor ions, such as boron ions, phosphorus ions, arsenic ions, and the like.
The material of the dielectric layer 43 is a dielectric material such as silicon oxynitride, aluminum oxide, silicon nitride or silicon oxide, and the material of the dielectric layer 43 is preferably silicon oxynitride, which has simple preparation and low cost, and the special material characteristics can enable the electrostatic protection structure to have a smaller turn-on voltage.
The first conductive layer 41 may be one or more, and the second conductive layer 44 may be one or more, and the dielectric layer 43 is disposed between each of the second conductive layers 44 and one or more of the first conductive layers 41. Fig. 14 is a schematic distribution diagram of the first conductive layer 41, the second conductive layer 44, and the dielectric layer 43 provided in this embodiment, and a line A-A in fig. 14 is a cross-sectional line of the semiconductor device shown in fig. 13. As shown in fig. 14, in this embodiment, the number of the first conductive layers 41 and the second conductive layers 44 is 4, the first conductive layers 41 and the second conductive layers 44 are in one-to-one correspondence, and the dielectric layer 43 is disposed between the corresponding second conductive layers 44 and the first conductive layers 41. It should be understood that the number of the first conductive layers 41, the dielectric layers 43, and the second conductive layers 44 is not limited to 4, and the number of the first conductive layers 41, the dielectric layers 43, and the second conductive layers 44 may be equal or unequal.
In this embodiment, each of the first conductive layer 41 and the second conductive layer 44 is strip-shaped and extends along the first direction and the second direction, and the shapes and the distribution manners of the first conductive layer 41 and the second conductive layer 44 should not be limited thereto, but it is preferable to dispose one first conductive layer 41 near each of the second conductive layers 44, so as to reduce the difficulty of wiring.
With continued reference to fig. 13 and 14, in this embodiment, the dielectric layer further includes a second interconnection structure, and the second interconnection structure includes a third conductive layer 45 and a second plug 42. The second plugs 42 are located in the isolation dielectric layer 31, one ends of the second plugs 42 are exposed out of the isolation dielectric layer 31, the other ends of the second plugs 42 are electrically connected with the corresponding first conductive layers 41 in the isolation dielectric layer 31, and the third conductive layers 45 are located between the isolation dielectric layer 31 and the bonding dielectric layer and are electrically connected with all the second plugs 42. In this way, the third conductive layer 45 is electrically connected to all the first conductive layers 41 in the isolation dielectric layer 31 through the second plugs 42, and all the first conductive layers 41 can be grounded by grounding the third conductive layer 45, so that each first conductive layer 41 does not need to be grounded separately, and the wiring difficulty is simplified.
It should be appreciated that in some embodiments, the second interconnect structure may also be omitted.
It should be noted that, the provision of a plurality of the first conductive layers 41 may make the design more flexible and the wiring simpler, and the substrate 11 in the semiconductor substrate 10 and each of the first conductive layers 41 may be used as a ground plate, which provides more feasibility for the device design.
Further, the first interconnection structure includes a first plug 50 and a bond pad pair. The first plug 50 is located in the isolation dielectric layer 31 and the corresponding semiconductor substrate 10, one end of the first plug 50 is electrically connected to the second conductive layer 44 in the dielectric layer, and the other end is electrically connected to the metal layer 13 in the corresponding semiconductor substrate 10. The bonding pad pair is located in the bonding dielectric layer and is electrically connected to the corresponding second conductive layer 44 and the metal layer 13. Specifically, the bonding dielectric layer includes a first bonding dielectric layer 32 and a second bonding dielectric layer 34, the first bonding dielectric layer 32 is attached to the isolation dielectric layer 31, the second bonding dielectric layer 34 is attached to the front surface of the semiconductor substrate 10, the bonding pad pair includes a first bonding pad 33 and a second bonding pad 35, and the first bonding pad 33 is located in the first bonding dielectric layer 32 and is electrically connected with the corresponding second conductive layer 44; the second bonding pads 35 are located in the second bonding dielectric layer 34 and electrically connected to the metal layer 13 of the corresponding semiconductor substrate 10, and the corresponding first bonding pads 33 are bonded to the second bonding pads 35 and form bonding pad pairs.
Based on this, the present embodiment also provides a flowchart of the method for manufacturing the semiconductor device, and fig. 1 is a flowchart of the method for manufacturing the semiconductor device provided in the present embodiment. As shown in fig. 1, the method for manufacturing the semiconductor device includes:
step S1: providing at least two semiconductor substrates, wherein each semiconductor substrate is internally provided with a metal layer;
Step S2: all the semiconductor substrates are stacked together, the metal layers in two adjacent semiconductor substrates are electrically connected through a first interconnection structure, a dielectric layer is arranged between the two adjacent semiconductor substrates, an electrostatic protection structure is formed in at least part of the dielectric layers, the electrostatic protection structure comprises stacked first conductive layers and second conductive layers, at least one first conductive layer is grounded, a dielectric layer is arranged between each second conductive layer and at least one first conductive layer, conductive ions are doped in each dielectric layer, and the second conductive layers in the dielectric layers are electrically connected with the corresponding first interconnection structures.
Fig. 2 to 13 are flowcharts corresponding to the steps of the method for manufacturing a semiconductor device according to the present embodiment, and the semiconductor device according to the present embodiment will be described in detail with reference to fig. 2 to 13.
Step S1 is performed, where at least two semiconductor substrates 10 are provided, each semiconductor substrate 10 is shown in fig. 2, each semiconductor substrate 10 includes a substrate 11, an insulating layer 12, and a metal layer 13 located in the insulating layer 12, each semiconductor substrate 10 has a front surface and a back surface, and in fig. 2, an upper surface of the semiconductor substrate 10 is the front surface thereof, and a lower surface is the back surface thereof.
In step S2, as shown in fig. 3, a second hybrid bonding structure is formed on the front surface of the first semiconductor substrate 10, where the second hybrid bonding structure includes a second bonding dielectric layer 34 and a second bonding pad 35 located in the second bonding dielectric layer 34, the top surface of the second bonding pad 35 exposes the second bonding dielectric layer 34, and the second bonding pad 35 is electrically connected with the metal layer 13 of the semiconductor substrate 10.
As shown in fig. 4, a supporting substrate 20 is bonded to the front surface of the second semiconductor substrate 10, and the supporting substrate 20 may not include a functional structure; or the support substrate 20 may contain functional structures, in some embodiments the support substrate 20 may contain functional structures that are located inside and/or on the surface of the interior and/or edge of the support substrate 20.
In this embodiment, a temporary bonding layer 21 is provided between the front surfaces of the support substrate 20 and the second semiconductor substrate 10, and the support substrate 20 and the second semiconductor substrate 10 can be bonded together by the temporary bonding layer 21. The bonding method of the support substrate 20 and the second semiconductor substrate 10 may include fusion bonding, thermocompression bonding, low temperature vacuum bonding, anodic bonding, eutectic bonding, hybrid bonding, or the like.
Thereafter, the back surface of the second semiconductor substrate 10 may be polished, thereby removing a part of the thickness of the substrate 11 of the second semiconductor substrate 10.
As shown in fig. 5, an isolation dielectric layer 31 is formed on the back surface of the second semiconductor substrate 10, and a first conductive layer 41 is formed in the isolation dielectric layer 31. The isolation medium layer 31 may include, for example, two films, and the first conductive layer 41 is formed between the two films.
As shown in fig. 6, the isolation dielectric layer 31 and the second semiconductor substrate 10 are etched to form a first contact hole (not shown in fig. 6), and the first contact hole exposes the metal layer 13 of the second semiconductor substrate 10. Then, a conductive material is filled in the first contact hole to form a first plug 50, and at this time, the first plug 50 is electrically connected to the metal layer 13 of the second semiconductor substrate 10.
With continued reference to fig. 6, the isolation dielectric 31 is etched to form a second contact hole (not shown in fig. 6), which exposes the corresponding first conductive layer 41 in the isolation dielectric 31. And then filling conductive material in the second contact hole to form a second plug 42, wherein the second plug 42 is electrically connected with the corresponding first conductive layer 41.
As shown in fig. 7, the isolation dielectric layer 31 is etched to form openings (not shown in fig. 7) exposing the corresponding first conductive layers 41 in the isolation dielectric layer 31. The dielectric layer 43 is then formed in the opening, at which time the dielectric layer 43 covers a portion of the surface of the corresponding first conductive layer 41 and is in direct contact with the first conductive layer 41.
In this embodiment, the material of the dielectric layer 43 is silicon oxynitride, and a silicon oxynitride layer can be formed by using a Plasma Enhanced Chemical Vapor Deposition (PECVD) process or sputtering of electron cyclotron resonance, and in this embodiment, a direct high-frequency PECVD apparatus is used to form the silicon oxynitride layer in the opening and on the isolation dielectric layer 301, which specifically includes: introducing N 2 O and SiH 4 gas into the reaction cavity, ionizing the reaction gas containing film constituent atoms by means of microwaves or radio frequency and the like to form plasma, growing silicon dioxide in a nitrogen-containing environment, and doping nitrogen into the silicon dioxide to form a silicon oxynitride layer; thereafter, the silicon oxynitride layer on the isolation dielectric layer 301 is removed by an etching process or a grinding process.
As shown in fig. 8, a second conductive layer 44 and a third conductive layer 45 are formed on the isolation dielectric layer 31. The second conductive layer 44 covers the corresponding dielectric layer 43, and the second conductive layer 44 further extends to cover the first plug 50, so that the second conductive layer 44 can be electrically connected to the first plug 50 and directly contact with the dielectric layer 43. The third conductive layer 45 covers all the second plugs 42, so that the third conductive layer 45 can be electrically connected to all the first conductive layers 41 through the second plugs 42. The first conductive layer 41, the dielectric layer 43 and the second conductive layer 44 form the electrostatic protection structure, and the third conductive layer 45 and the second plug 42 form the second interconnection structure.
In some embodiments, the steps of forming the third conductive layer 45 and forming the second plug 42 may be omitted.
Next, a first annealing process is performed to allow conductive ions at the interface of the dielectric layer 43 and the second conductive layer 44 to penetrate into the dielectric layer 43 (silicon oxynitride is porous and may be doped with conductive ions), so that the dielectric layer 43 is doped with conductive ions. A second annealing process is then performed to repair defects in the second conductive layer 44 itself. For example, the material of the second conductive layer 44 is copper, the conductive ions at the interface between the dielectric layer 43 and the second conductive layer 44 are copper ions, the first annealing process is performed, so that the copper ions penetrate into the dielectric layer 43, the dielectric layer 43 is doped with copper ions, and the second annealing process is performed, thereby repairing the defects of copper itself.
In some embodiments, the conductive ions may be implanted into the dielectric layer 43 through an ion implantation process after the dielectric layer 43 is formed, thereby simplifying the steps of the annealing process.
As shown in fig. 9, a first hybrid bonding structure is formed on the isolation dielectric layer 31, and the first hybrid bonding structure includes a first bonding dielectric layer 32 and a first bonding pad 33. The first bonding dielectric layer 32 covers the isolation dielectric layer 31, the second conductive layer 44 and the third conductive layer 45, the first bonding pad 33 is located in the first bonding dielectric layer 32, the top surface of the first bonding pad 33 needs to be exposed out of the first bonding dielectric layer 32, and the first bonding pad 33 is electrically connected with the corresponding second conductive layer 44.
Next, as shown in fig. 10, the second bonding dielectric layer 34 on the first semiconductor substrate 10 is bonded to the first bonding dielectric layer 32 on the second semiconductor substrate 10, and at the same time, the corresponding first bonding pad 33 and second bonding pad 35 are bonded to each other, and the front surface of the first semiconductor substrate 10 is bonded to the back surface of the second semiconductor substrate 10 by the first hybrid bonding structure and the second hybrid bonding structure by using the bonding force between metals and the bonding force between the dielectrics. At this time, the first bonding pad 33, the second bonding pad 35, and the first plug 50 form the first interconnection structure, and the isolation dielectric layer 31, the first bonding dielectric layer 32, and the second bonding dielectric layer 34 form the dielectric layer.
As shown in fig. 11, the support substrate 20 and the second semiconductor substrate 10 are detached from each other, and the support substrate 20 and the temporary bonding layer 21 are removed.
At this time, the step of stacking the second one of the semiconductor substrates 10 on the first one of the semiconductor substrates 10 has been completed.
Next, as shown in fig. 12, the second hybrid bonding structure is formed on the front surface of the second semiconductor substrate 10. The second bonding dielectric layer 34 in the second hybrid bonding structure covers the front surface of the second semiconductor substrate 10, and the second bonding pad 35 in the second hybrid bonding structure is electrically connected to the metal layer 13 of the second semiconductor substrate 10.
As shown in fig. 13, after that, when stacking the next semiconductor substrate 10 on the previous semiconductor substrate 10 in turn and stacking two adjacent semiconductor substrates 10, the isolation medium layer 31, the first plug 50, the electrostatic protection structure, and the first hybrid bonding structure are formed on the back surface of the next semiconductor substrate 10 and the second hybrid bonding structure is formed on the front surface of the previous semiconductor substrate 10; and bonding the previous semiconductor substrate on the next semiconductor substrate by using the first mixed bonding structure on the back surface of the next semiconductor substrate 10 and the second mixed bonding structure on the front surface of the previous semiconductor substrate 10 until all the semiconductor substrates 10 are stacked.
The "preceding semiconductor substrate 10", "succeeding semiconductor substrate 10" refers to two adjacent semiconductor substrates 10, for example, a first semiconductor substrate 10 is the preceding semiconductor substrate 10 and a second semiconductor substrate 10 is the succeeding semiconductor substrate 10, with respect to the first semiconductor substrate 10 and the second semiconductor substrate 10; for the second and third semiconductor substrates 10 and 10, the second semiconductor substrate 10 is the preceding semiconductor substrate 10, and the third semiconductor substrate 10 is the following semiconductor substrate 10. For example, when stacking the third semiconductor substrate 10, the isolation dielectric layer 31, the first plug 50, the electrostatic protection structure and the first hybrid bonding structure are formed on the back surface of the third semiconductor substrate 10; and then bonding the second semiconductor substrate 10 to the third semiconductor substrate 10 by using the second hybrid bonding structure on the front surface of the second semiconductor substrate 10 and the first hybrid bonding structure on the back surface of the third semiconductor substrate 10.
Example two
Fig. 15 to 17 are flowcharts corresponding to respective steps of a method for manufacturing a semiconductor device according to the present embodiment. Fig. 15 to 17 are different from the first embodiment in that, in the present embodiment, when all the semiconductor substrates 10 are stacked, the following semiconductor substrate 10 is stacked on the preceding semiconductor substrate 10 in order.
Specifically, referring to fig. 4 to 9, the isolation dielectric layer 31, the first plug 50, the electrostatic protection structure and the first hybrid bonding structure are formed on the back surface of the first semiconductor substrate 10. The steps of fig. 2 to 3 are referred to as forming the second hybrid bonding structure on the front surface of the second semiconductor substrate 10.
The specific steps for forming the isolation dielectric layer 31, the first plug 50, the electrostatic protection structure, the first hybrid bonding structure and the second hybrid bonding structure are described in detail in the first embodiment, and will not be repeated here.
As shown in fig. 15, the second semiconductor substrate 10 is bonded to the first semiconductor substrate 10 by using the first hybrid bonding structure on the back surface of the first semiconductor substrate 10 and the second hybrid bonding structure on the front surface of the second semiconductor substrate 10.
As shown in fig. 16, the isolation dielectric layer 31, the first plug 50, the electrostatic protection structure, and the first hybrid bonding structure are formed on the back surface of the second semiconductor substrate 10. Thereafter, the second hybrid bonding structure is formed on the front surface of the third semiconductor substrate 10 (not shown in fig. 16), and the third semiconductor substrate 10 is bonded to the second semiconductor substrate 10 using the first hybrid bonding structure on the back surface of the second semiconductor substrate 10 and the second hybrid bonding structure on the front surface of the third semiconductor substrate 10.
As shown in fig. 17, after that, when stacking the next semiconductor substrate 10 on the previous semiconductor substrate 10 in order and stacking two adjacent semiconductor substrates 10, the isolation medium layer 31, the first plug 50, the electrostatic protection structure, and the first hybrid bonding structure are formed on the previous semiconductor substrate 10 and the second hybrid bonding structure is formed on the next semiconductor substrate 10; and bonding the next semiconductor substrate on the previous semiconductor substrate by using the first mixed bonding structure on the back surface of the previous semiconductor substrate and the second mixed bonding structure on the front surface of the next semiconductor substrate until all the semiconductor substrates 10 are stacked.
The "preceding semiconductor substrate 10", "succeeding semiconductor substrate 10" refers to two adjacent semiconductor substrates 10, for example, a first semiconductor substrate 10 is the preceding semiconductor substrate 10 and a second semiconductor substrate 10 is the succeeding semiconductor substrate 10, with respect to the first semiconductor substrate 10 and the second semiconductor substrate 10; for the second and third semiconductor substrates 10 and 10, the second semiconductor substrate 10 is the preceding semiconductor substrate 10, and the third semiconductor substrate 10 is the following semiconductor substrate 10.
Example III
Fig. 18 is a schematic diagram showing the distribution of the first conductive layer 41, the second conductive layer 44, and the dielectric layer 43 according to the present embodiment. As shown in fig. 18, the difference between the first embodiment and the second embodiment is that in the present embodiment, the dielectric layer 43 is provided between each of the second conductive layers 44 and all of the first conductive layers 41. Taking one second conductive layer 44 as an example, the dielectric layer 43 is disposed between each second conductive layer 44 and 4 first conductive layers 41, and the second conductive layers 44, the first conductive layers 41 and the 4 dielectric layers 43 therebetween may be equivalent to 4 capacitors connected in parallel. When the first interconnection structure receives abnormal high voltage (static electricity), channels are formed between two polar plates of the 4 capacitors, static electricity can be conducted to the ground more quickly, and the static electricity protection effect is enhanced.
In summary, in the semiconductor device and the method for manufacturing the same provided in the embodiments of the present invention, the sandwich structure formed by the first conductive layer, the second conductive layer and the dielectric layer therebetween may be equivalent to a capacitor, one electrode plate of the capacitor is grounded, the other electrode plate is connected to the first interconnection structure, under normal conditions, the capacitor may separate the first interconnection structure from ground, so that signal transmission on the first interconnection structure is not affected, when the first interconnection structure receives an abnormally high voltage (static electricity), under a strong electric field, conductive ions in the dielectric layer are activated, a channel is formed between two electrode plates of the capacitor, and static electricity is rapidly introduced into ground by using an electron tunneling effect, thereby realizing a static electricity protection effect. The first conductive layer, the dielectric layer and the second conductive layer are stacked in the dielectric layer, so that the layout area of the electrostatic protection structure can be reduced, wiring resources are not excessively occupied, metal congestion is reduced, noise and inductive parasitic in a transmission path formed by the first interconnection structure are reduced, the reliability of a device is improved, and advantages in performance, power consumption and area are provided for the device. The arrangement of the plurality of first conductive layers can enable the design to be more flexible and the wiring to be simpler, and the substrate in the semiconductor substrate and each first conductive layer can be used as a grounding plate, so that more feasibility is provided for the design of the device. The dielectric layer between the second conductive layer and the first conductive layer can be adjusted, so that the electrostatic protection standard is adjusted, and the margin of device design is increased.
It should be noted that, in the present description, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different manner from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other. For the system disclosed in the embodiment, the description is relatively simple because of corresponding to the method disclosed in the embodiment, and the relevant points refer to the description of the method section.
It should be further noted that although the present invention has been disclosed in the preferred embodiments, the above embodiments are not intended to limit the present invention. Many possible variations and modifications of the disclosed technology can be made by anyone skilled in the art without departing from the scope of the technology, or the technology can be modified to be equivalent. Therefore, any simple modification, equivalent variation and modification of the above embodiments according to the technical substance of the present invention still fall within the scope of the technical solution of the present invention.
It should be further understood that the terms "first," "second," "third," and the like in this specification are used merely for distinguishing between various components, elements, steps, etc. in the specification and not for indicating a logical or sequential relationship between the various components, elements, steps, etc., unless otherwise indicated.
It should also be understood that the terminology described herein is for the purpose of describing particular embodiments only, and is not intended to limit the scope of the present invention. It must be noted that, as used herein and in the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. For example, reference to "a step" or "an apparatus" means a reference to one or more steps or apparatuses, and may include sub-steps as well as sub-apparatuses. All conjunctions used should be understood in the broadest sense. And, the word "or" should be understood as having the definition of a logical "or" rather than a logical "exclusive or" unless the context clearly indicates the contrary. Furthermore, implementation of the methods and/or apparatus in embodiments of the invention may include performing selected tasks manually, automatically, or in combination.
Claims (16)
1. The semiconductor device is characterized by comprising at least two stacked semiconductor substrates, wherein each semiconductor substrate is internally provided with a metal layer, and the metal layers in two adjacent semiconductor substrates are electrically connected through a first interconnection structure; and
A dielectric layer is arranged between two adjacent semiconductor substrates, an electrostatic protection structure is formed in at least part of the dielectric layers, the electrostatic protection structure comprises a first conductive layer and a second conductive layer which are stacked, each of the first conductive layer and the second conductive layer is at least one, each first conductive layer is grounded, a dielectric layer is arranged between each second conductive layer and at least one first conductive layer, conductive ions are doped in each dielectric layer, and each second conductive layer in the dielectric layer is electrically connected with the corresponding first interconnection structure.
2. The semiconductor device according to claim 1, wherein the first conductive layers are in one-to-one correspondence with the second conductive layers with the dielectric layers therebetween.
3. The semiconductor device of claim 1, wherein each of the second conductive layers and each of the first conductive layers has the dielectric layer therebetween.
4. The semiconductor device of claim 1, wherein the material of the dielectric layer is silicon oxynitride, aluminum oxide, silicon nitride, or silicon oxide.
5. The semiconductor device according to claim 1, wherein the conductive ion is a metal ion or a semiconductor ion.
6. The semiconductor device of claim 1, wherein the dielectric layer comprises a stack of an isolation dielectric layer and a bonding dielectric layer, the first conductive layer and the dielectric layer are located within the isolation dielectric layer, the second conductive layer is located between the isolation dielectric layer and the bonding dielectric layer, the dielectric layer is in direct contact with the respective first conductive layer and second conductive layer, and the dielectric layer and the respective first conductive layer and second conductive layer each have an overlap region in a thickness direction along the semiconductor substrate.
7. The semiconductor device of claim 6, wherein the first interconnect structure comprises a first plug and a pair of bond pads, the first plug being located within the isolation dielectric layer and the corresponding semiconductor substrate, the first plug being electrically connected to the second conductive layer in the dielectric layer and the corresponding metal layer within the semiconductor substrate, the pair of bond pads being located within the bonding dielectric layer and being electrically connected to the corresponding second conductive layer and the metal layer.
8. The semiconductor device of claim 6, wherein the first conductive layer in the dielectric layer is grounded through a second interconnect structure comprising a third conductive layer and a second plug, the third conductive layer being located between the isolation dielectric layer and the bonding dielectric layer, and the third conductive layer being grounded, the second plug being located within the isolation dielectric layer and electrically connected to the third conductive layer and the corresponding first conductive layer.
9. The semiconductor device according to claim 1, wherein one of the semiconductor substrates in the semiconductor device is a logic substrate, the other semiconductor substrates are device substrates, the logic substrate is located at the outermost side of all the semiconductor substrates, and the dielectric layer between at least the logic substrate and the device substrates has the electrostatic protection structure.
10. A method of manufacturing a semiconductor device, comprising:
providing at least two semiconductor substrates, wherein each semiconductor substrate is internally provided with a metal layer;
All the semiconductor substrates are stacked together, the metal layers in two adjacent semiconductor substrates are electrically connected through a first interconnection structure, a dielectric layer is arranged between the two adjacent semiconductor substrates, an electrostatic protection structure is formed in at least part of the dielectric layers, the electrostatic protection structure comprises stacked first conductive layers and second conductive layers, at least one first conductive layer is grounded, a dielectric layer is arranged between each second conductive layer and at least one first conductive layer, conductive ions are doped in each dielectric layer, and the second conductive layers in the dielectric layers are electrically connected with the corresponding first interconnection structures.
11. The method of manufacturing a semiconductor device according to claim 10, wherein when stacking all the semiconductor substrates, stacking a subsequent one of the semiconductor substrates on a previous one of the semiconductor substrates in order, when stacking two adjacent semiconductor substrates, forming an insulating dielectric layer, a first plug, the electrostatic protection structure, and a first hybrid bonding structure on the previous one of the semiconductor substrates, and forming a second hybrid bonding structure on the subsequent one of the semiconductor substrates, bonding the subsequent one of the semiconductor substrates to the previous one of the semiconductor substrates by using the first hybrid bonding structure and the second hybrid bonding structure;
The first plug is positioned in the isolation dielectric layer and the corresponding semiconductor substrate and is electrically connected with the metal layer in the corresponding semiconductor substrate and the second conductive layer in the dielectric layer; the electrostatic protection structure is integrally positioned in the isolation medium layer; the first hybrid bonding structure is positioned on the isolation dielectric layer and the static electricity protection structure, and comprises a first bonding dielectric layer and a first bonding pad positioned in the first bonding dielectric layer, the first bonding pad is electrically connected with the corresponding second conductive layer, the second hybrid bonding structure comprises a second bonding dielectric layer and a second bonding pad positioned in the second bonding dielectric layer, and the second bonding pad is electrically connected with the corresponding metal layer; the isolation dielectric layer, the first bonding dielectric layer and the second bonding dielectric layer form the dielectric layer, and the first plug, the first bonding pad and the second bonding pad form the first interconnection structure.
12. The method of manufacturing a semiconductor device according to claim 10, wherein when stacking all the semiconductor substrates, a second semiconductor substrate is stacked on a first semiconductor substrate, and then a next semiconductor substrate is stacked on a previous semiconductor substrate in sequence, and when stacking two adjacent semiconductor substrates, an isolation dielectric layer, a first plug, the electrostatic protection structure, a first hybrid bonding structure, and a second hybrid bonding structure are formed on the next semiconductor substrate, and then the first hybrid bonding structure and the second hybrid bonding structure are used to bond the previous semiconductor substrate to the next semiconductor substrate;
The first plug is positioned in the isolation dielectric layer and the corresponding semiconductor substrate and is electrically connected with the metal layer in the corresponding semiconductor substrate and the second conductive layer in the dielectric layer; the electrostatic protection structure is integrally positioned in the isolation medium layer; the first hybrid bonding structure is positioned on the isolation dielectric layer and the static electricity protection structure, and comprises a first bonding dielectric layer and a first bonding pad positioned in the first bonding dielectric layer, the first bonding pad is electrically connected with the corresponding second conductive layer, the second hybrid bonding structure comprises a second bonding dielectric layer and a second bonding pad positioned in the second bonding dielectric layer, and the second bonding pad is electrically connected with the corresponding metal layer; the isolation dielectric layer, the first bonding dielectric layer and the second bonding dielectric layer form the dielectric layer, and the first plug, the first bonding pad and the second bonding pad form the first interconnection structure.
13. The method of manufacturing a semiconductor device according to claim 11 or 12, wherein the step of forming the isolation dielectric layer, the first plug, and the electrostatic protection structure on the semiconductor substrate comprises:
forming the isolation dielectric layer on the semiconductor substrate, and forming the first conductive layer in the isolation dielectric layer;
etching the isolation dielectric layer and the semiconductor substrate to form a first contact hole exposing the metal layer;
filling conductive material in the first contact hole to form the first plug;
etching the isolation medium layer to form an opening exposing the corresponding first conductive layer;
forming the dielectric layer within the opening; and
And forming the second conductive layer on the isolation dielectric layer, wherein the second conductive layer covers the dielectric layer and the first plug correspondingly.
14. The method of manufacturing a semiconductor device according to claim 13, wherein the conductive ions are implanted in the dielectric layer by an ion implantation process after the dielectric layer is formed.
15. The method for manufacturing a semiconductor device according to claim 13, wherein after the second conductive layer is formed, the method further comprises:
performing a first annealing process to infiltrate conductive ions at an interface of the dielectric layer and the second conductive layer into the dielectric layer; and
And performing a second annealing process to repair the defects of the second conductive layer.
16. The method of manufacturing a semiconductor device according to claim 13, wherein after forming the first plug, before etching the isolation dielectric layer to form the opening, the method further comprising:
Etching the isolation medium layer to form a second contact hole, wherein the second contact hole exposes the corresponding first conductive layer;
Filling conductive material in the second contact hole to form a second plug; and
And when the second conductive layer is formed, a third conductive layer is further formed on the isolation medium layer, the third conductive layer is used for grounding, and the third conductive layer is electrically connected with the second plug.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202411074990.3A CN118588704B (en) | 2024-08-07 | 2024-08-07 | Semiconductor device and method for manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202411074990.3A CN118588704B (en) | 2024-08-07 | 2024-08-07 | Semiconductor device and method for manufacturing the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN118588704A CN118588704A (en) | 2024-09-03 |
| CN118588704B true CN118588704B (en) | 2024-11-12 |
Family
ID=92524864
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202411074990.3A Active CN118588704B (en) | 2024-08-07 | 2024-08-07 | Semiconductor device and method for manufacturing the same |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN118588704B (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9541521B1 (en) * | 2015-10-30 | 2017-01-10 | Nxp Usa, Inc. | Enhanced sensitivity ion sensing devices |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW201640646A (en) * | 2015-05-13 | 2016-11-16 | Advanced Analog Technology Inc | Connection pad electrostatic protection element of integrated circuit |
| KR102411417B1 (en) * | 2015-12-02 | 2022-06-22 | 삼성전자주식회사 | Semiconductor devices having a resistor and semiconductor integrated circuit devices using the same |
| CN112542378B (en) * | 2020-12-01 | 2024-03-26 | 武汉新芯集成电路制造有限公司 | Method for manufacturing semiconductor device and semiconductor device |
| CN116093103A (en) * | 2023-02-28 | 2023-05-09 | 惠科股份有限公司 | Array substrate and display panel |
-
2024
- 2024-08-07 CN CN202411074990.3A patent/CN118588704B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9541521B1 (en) * | 2015-10-30 | 2017-01-10 | Nxp Usa, Inc. | Enhanced sensitivity ion sensing devices |
Also Published As
| Publication number | Publication date |
|---|---|
| CN118588704A (en) | 2024-09-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6544837B1 (en) | SOI stacked DRAM logic | |
| US7098070B2 (en) | Device and method for fabricating double-sided SOI wafer scale package with through via connections | |
| US8778737B2 (en) | Flattened substrate surface for substrate bonding | |
| US10049915B2 (en) | Three dimensional integrated circuit | |
| US8933540B2 (en) | Thermal via for 3D integrated circuits structures | |
| US20110284992A1 (en) | 3d integrated circuit and method of manufacturing the same | |
| US20190267285A1 (en) | Backside contact to a final substrate | |
| KR102547557B1 (en) | Antenna effect protection and electrostatic discharge protection for three-dimensional integrated circuit | |
| US8853816B2 (en) | Integrated circuits separated by through-wafer trench isolation | |
| US10037911B2 (en) | Device layer transfer with a preserved handle wafer section | |
| US20230178478A1 (en) | Interconnect structure of a semiconductor component and methods for producing the structure | |
| WO2021159588A1 (en) | Bonding structure and manufacturing method therefor | |
| TWI817383B (en) | A 3dic device and forming the same | |
| TWI803013B (en) | Method for fabricating semiconductor device | |
| CN118588704B (en) | Semiconductor device and method for manufacturing the same | |
| US20250015066A1 (en) | Semiconductor device and method for making same | |
| US8557677B2 (en) | Stack-type semiconductor device and method for manufacturing the same | |
| CN116613080A (en) | Semiconductor device and method for manufacturing the same | |
| US20220375918A1 (en) | Method of manufacturing three-dimensional system-on-chip and three-dimensional system-on-chip | |
| US20060255389A1 (en) | Semiconductor device with decoupling capacitor and method of fabricating the same | |
| US20220165669A1 (en) | Semiconductor device structure, stacked semiconductor device structure and method of manufacturing semiconductor device structure | |
| KR102642271B1 (en) | Integrated circuit package and method | |
| CN115279014B (en) | A printed circuit board structure and a method for manufacturing the same | |
| US20070194410A1 (en) | Multi-chip device and method for manufacturing the same | |
| CN117253895A (en) | Semiconductor structure and forming method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |