CN118588667B - Chip packaging structure and preparation method thereof - Google Patents
Chip packaging structure and preparation method thereof Download PDFInfo
- Publication number
- CN118588667B CN118588667B CN202411067626.4A CN202411067626A CN118588667B CN 118588667 B CN118588667 B CN 118588667B CN 202411067626 A CN202411067626 A CN 202411067626A CN 118588667 B CN118588667 B CN 118588667B
- Authority
- CN
- China
- Prior art keywords
- chip
- heat dissipation
- micro
- adapter plate
- switching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 22
- 238000002360 preparation method Methods 0.000 title claims abstract description 13
- 230000017525 heat dissipation Effects 0.000 claims abstract description 240
- 238000012546 transfer Methods 0.000 claims abstract description 25
- 238000007789 sealing Methods 0.000 claims description 78
- 238000000034 method Methods 0.000 claims description 53
- 238000005530 etching Methods 0.000 claims description 42
- 238000004891 communication Methods 0.000 claims description 40
- 238000004519 manufacturing process Methods 0.000 claims description 22
- 230000005855 radiation Effects 0.000 claims description 19
- 239000004744 fabric Substances 0.000 claims description 11
- 241000724291 Tobacco streak virus Species 0.000 description 15
- 238000009713 electroplating Methods 0.000 description 14
- 238000000206 photolithography Methods 0.000 description 12
- 239000000463 material Substances 0.000 description 11
- 238000010586 diagram Methods 0.000 description 8
- 238000001259 photo etching Methods 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 6
- 230000010354 integration Effects 0.000 description 6
- 238000010438 heat treatment Methods 0.000 description 5
- 238000005429 filling process Methods 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 3
- 239000007888 film coating Substances 0.000 description 3
- 238000009501 film coating Methods 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- 235000012431 wafers Nutrition 0.000 description 3
- 238000009825 accumulation Methods 0.000 description 2
- 238000004220 aggregation Methods 0.000 description 2
- 230000002776 aggregation Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000004070 electrodeposition Methods 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/46—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids
- H01L23/473—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids by flowing liquids
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
- H01L21/4814—Conductive parts
- H01L21/4871—Bases, plates or heatsinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
- H01L21/4814—Conductive parts
- H01L21/4871—Bases, plates or heatsinks
- H01L21/4882—Assembly of heatsink parts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
本发明公开了一种芯片封装结构及其制备方法。其中，芯片封装结构包括：转接结构、散热结构和第一芯片；转接结构中设置凹槽；凹槽贯穿部分转接结构；第一芯片设置在凹槽中；散热结构设置在转接结构中且沿第一方向与第一芯片交叠；其中，第一方向为转接结构厚度方向；散热结构的热导率大于转接结构的热导率；转接结构中设置微流道孔，微流道孔沿第一方向贯穿转接结构且与凹槽连通；微流道孔在平面的投影至少部分围绕第一芯片在平面的投影；其中，平面与第一方向垂直。本发明的技术方案，通过在转接结构中设置散热结构和微流道孔，提高了转接结构的散热效率，进而提高了第一芯片的性能和寿命。
The present invention discloses a chip packaging structure and a preparation method thereof. The chip packaging structure includes: a transfer structure, a heat dissipation structure and a first chip; a groove is arranged in the transfer structure; the groove penetrates part of the transfer structure; the first chip is arranged in the groove; the heat dissipation structure is arranged in the transfer structure and overlaps with the first chip along a first direction; wherein the first direction is the thickness direction of the transfer structure; the thermal conductivity of the heat dissipation structure is greater than the thermal conductivity of the transfer structure; a microfluidic hole is arranged in the transfer structure, the microfluidic hole penetrates the transfer structure along the first direction and is connected to the groove; the projection of the microfluidic hole on the plane at least partially surrounds the projection of the first chip on the plane; wherein the plane is perpendicular to the first direction. The technical solution of the present invention improves the heat dissipation efficiency of the transfer structure by arranging the heat dissipation structure and the microfluidic hole in the transfer structure, thereby improving the performance and life of the first chip.
Description
Technical Field
The invention relates to the technical field of semiconductor packaging, in particular to a chip packaging structure and a preparation method thereof.
Background
With the development of electronic products toward miniaturization, high performance, high reliability and the like, the integration level of the system is increasingly improved. Through silicon via technology (Through Silicon Via, TSV) is one of the key technologies to realize 2.5D/3D packaging, in which communication is by way of vertical conduction from chip to chip, wafer to wafer.
Although the TSV-based 2.5D/3D integration technology achieves high integration between chips, the heat dissipation capability is also greatly reduced. In the prior art, the heat dissipation capacity of the packaged chip is improved by combining the adapter plate with the micro-channel process, but the heat conduction requirement of the adapter plate is higher, but the heat dissipation capacity of the adapter plate is preferential due to the limitation of materials, so that the heat dissipation requirement of the high-power chip cannot be further met.
Disclosure of Invention
The invention provides a chip packaging structure and a preparation method thereof, which are used for solving the problems that the existing 2.5D/3D integrated chip packaging technology is low in heat dissipation efficiency and cannot meet the heat dissipation requirement of a high-power chip.
According to an aspect of the present invention, there is provided a chip package structure including: the LED comprises an adapter structure, a heat dissipation structure and a first chip;
A groove is arranged in the switching structure; the groove penetrates through the partial switching structure; the first chip is arranged in the groove;
the heat dissipation structure is arranged in the switching structure and overlapped with the first chip along the first direction; wherein the first direction is the thickness direction of the switching structure; the heat conductivity of the heat dissipation structure is greater than that of the switching structure;
the micro-flow channel holes penetrate through the switching structure along the first direction and are communicated with the grooves;
the projection of the micro-channel hole on the plane surrounds the projection of the first chip on the plane; wherein the plane is perpendicular to the first direction.
Optionally, the heat dissipation structure includes a heat dissipation communication layer and a plurality of heat dissipation columns;
the heat dissipation communication layer is arranged between the first chip and the switching structure and is connected with each heat dissipation column.
Optionally, along the first direction, the heat dissipation post penetrates through the adapting structure.
Optionally, the first chip includes a first chip body and a first chip electrode located at one side of the first chip body;
The first chip electrode is positioned at one side of the first chip body close to the heat dissipation structure;
The chip packaging structure also comprises a rewiring structure and a first pin connecting structure; the rewiring structure is electrically connected with the first chip electrode and the first pin connecting structure respectively; the first pin connection structure penetrates through the switching structure along a first direction.
Optionally, the chip package structure further includes a second chip and a second pin connection structure; the second chip and the first chip are arranged in a lamination way, and the second chip is positioned at one side of the first chip far away from the heat dissipation structure;
The second chip comprises a second chip body and a second chip electrode positioned at one side of the second chip body; the second chip electrode is positioned at one side of the second chip body close to the heat dissipation structure;
the second pin connection structure penetrates through the switching structure and is electrically connected with the second chip electrode.
Optionally, the micro-channel hole comprises a first micro-channel subsection and a second micro-channel subsection which penetrate through the micro-channel hole;
the switching structure comprises a first switching plate and a second switching plate which are arranged in a laminated way; the heat dissipation structure and the first micro-channel subsection are arranged in the first adapter plate, and the first micro-channel subsection penetrates through the first adapter plate; the groove and the second micro-channel part penetrate through the second adapter plate, and the second micro-channel part is communicated with the groove;
the first pin connecting structure penetrates through the first adapter plate along a first direction; the rewiring structure is disposed between the first interposer and the second interposer.
Optionally, the chip package structure further includes: a first sealing layer;
the first sealing layer covers at least the upper surface and the side surface of the first chip, the side surface of the second micro flow channel subsection and the upper surface of the second adapter plate.
Optionally, the chip package structure further includes: a second sealing layer;
The second sealing layer is arranged on one side, far away from the first chip, of the first sealing layer and covers the upper surface of the first chip, the micro-channel hole and the upper surface of the second adapter plate.
According to another aspect of the present invention, there is provided a method of manufacturing a chip package structure, for manufacturing a chip package structure; the preparation method comprises the following steps:
Providing a switching structure and etching the switching structure, and forming a groove, a heat dissipation hole and a micro-channel hole in the switching structure;
Growing a heat dissipation structure at least in the heat dissipation holes; the heat conductivity of the heat dissipation structure is greater than that of the switching structure;
A first chip is provided and disposed in the recess.
Optionally, providing a switching structure and etching the switching structure, forming a groove, a heat dissipation hole and a micro-channel hole in the switching structure, including:
Providing a first conversion plate, etching the first conversion plate, and forming a heat dissipation hole, a micro-channel hole and a pin connecting hole in the first conversion plate;
providing a second adapter plate and etching the second adapter plate, and forming a groove in the second adapter plate;
Growing a heat dissipating structure at least in the heat dissipating holes, comprising:
growing a heat radiation column in the heat radiation structure in the heat radiation hole, and growing a first pin connection structure in the pin connection hole;
The second adapter plate is arranged on one side of the first adapter plate.
Optionally, before the second adapter plate is disposed on one side of the first adapter plate, the method further includes:
Growing a wiring layer on the surface of the first adapter plate and etching the wiring layer to form a heat dissipation communication layer and a rewiring structure; the heat dissipation communication layer is connected with each heat dissipation column, and the rewiring structure is electrically connected with the first pin connection structure.
Optionally, the micro-channel hole comprises a first micro-channel subsection and a second micro-channel subsection which penetrate through the micro-channel hole; the second micro-channel part penetrates through the second adapter plate and is communicated with the groove;
after providing the first chip and disposing the first chip in the recess, further comprising:
A first sealing layer is arranged on one side of the first chip far away from the switching structure, and the first sealing layer is etched to enable the first sealing layer to at least cover the upper surface and the side face of the first chip, the side face of the second micro-channel subsection and the upper surface of the second switching plate;
And a second sealing layer is arranged on one side of the first sealing layer far away from the switching structure, so that the second sealing layer covers the upper surface of the first chip, the micro-channel hole and the upper surface of the second switching plate.
According to the technical scheme, the heat dissipation structure and the micro-channel holes are arranged in the switching structure, and the heat conductivity of the heat dissipation structure is larger than that of the switching structure, so that the first chip can conduct out heat through the heat dissipation structure, and the heat dissipation efficiency of the switching structure is improved; and the micro-flow channel holes are arranged around the side surface of the first chip, so that the heat dissipation medium can flow around the first chip, the heat dissipation of the first chip is realized, the heat dissipation efficiency of the switching structure is further improved, and the performance and the service life of the first chip are improved.
It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the invention or to delineate the scope of the invention. Other features of the present invention will become apparent from the description that follows.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a cross-sectional view of a first chip package structure provided according to an embodiment of the present invention;
fig. 2 is a top view of a first chip package structure provided according to an embodiment of the invention;
Fig. 3 is a cross-sectional view of a second chip package structure provided according to an embodiment of the present invention;
fig. 4 is a cross-sectional view of a third chip package structure provided according to an embodiment of the present invention;
fig. 5 is a cross-sectional view of a fourth chip package structure provided according to an embodiment of the present invention;
FIG. 6 is a top view of a first adapter plate provided in accordance with an embodiment of the present invention;
Fig. 7 is a top view of a fourth chip package structure provided according to an embodiment of the invention;
fig. 8 is a cross-sectional view of a fifth chip package structure provided according to an embodiment of the present invention;
Fig. 9 is a flowchart of a method for manufacturing a first chip package structure according to an embodiment of the present invention;
fig. 10 is a block diagram corresponding to a preparation method of a first chip package structure according to an embodiment of the present invention;
FIG. 11 is a flowchart of a method for fabricating a second chip package structure according to an embodiment of the present invention;
Fig. 12 is a block diagram corresponding to a method for manufacturing a second chip package structure according to an embodiment of the present invention;
Fig. 13 is a flowchart of a method for manufacturing a third chip package structure according to an embodiment of the present invention;
fig. 14 is a block diagram corresponding to a preparation method of a third chip package structure according to an embodiment of the present invention;
fig. 15 is a flowchart of a method for manufacturing a fourth chip package structure according to an embodiment of the present invention;
Fig. 16 is a block diagram corresponding to a method for manufacturing a fourth chip package structure according to an embodiment of the present invention
Detailed Description
In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein.
Fig. 1 is a cross-sectional view of a first chip package structure according to an embodiment of the present invention, and fig. 2 is a top view of the first chip package structure according to an embodiment of the present invention. As shown in fig. 1 and 2, the chip package structure includes: the heat dissipation device comprises an adapter structure 1, a heat dissipation structure 2 and a first chip 3;
a groove 4 is arranged in the switching structure 1; the groove 4 penetrates through part of the switching structure 1; the first chip 3 is arranged in the groove 4;
The heat dissipation structure 2 is arranged in the switching structure 1 and overlapped with the first chip 3 along the first direction x; wherein, the first direction x is the thickness direction of the switching structure 1; the heat conductivity of the heat dissipation structure 2 is greater than that of the switching structure 1;
The micro-channel hole 5 is arranged in the switching structure 1, and the micro-channel hole 5 penetrates through the switching structure 1 along the first direction x and is communicated with the groove 4;
the projection of the micro flow channel hole 5 on the plane surrounds the projection of the first chip 3 on the plane; wherein the plane is perpendicular to the first direction x.
The transfer structure 1 may be composed of a transfer plate, and the transfer structure 1 may lead in or out an electrode of the first chip 3 through TSV technology, and connect the electrode of the first chip 3 with other wirings, so as to realize vertical conduction between chips, and between wafers. The transfer structure 1 includes a groove 4, the groove 4 can be realized by etching the transfer structure 1, the groove 4 partially penetrates through the transfer structure 1 along the first direction x, and the first chip 3 is disposed in the groove 4, so that the first chip 3 can be connected with other wires through the transfer structure 1 with TSVs.
Because the transfer structure 1 is generally made of an insulating material, when the first chip 3 is disposed in the groove 4 of the transfer structure 1, heat generated by the first chip 3 needs to be dissipated through the transfer structure 1, so that the thermal conductivity of the transfer structure 1 is related to the heat dissipation efficiency of the chip package structure. The heat dissipation structure 2 is disposed in the adapting structure 1, the heat conductivity of the heat dissipation structure 2 is greater than that of the adapting structure 1, and the heat dissipation structure 2 can be made of metal. The heat dissipation structure 2 may be formed by etching the through structure 1 to form the heat dissipation hole 20 and filling at least the heat dissipation hole 20 with a metal material. Because the thermal conductivity of the metal material is greater than that of the insulating material, the first chip 3 is arranged in the groove 4, and the heat dissipation structure 2 is overlapped with the first chip 3 along the first direction x, so that heat in the first chip 3 can be directly dissipated through the heat dissipation structure 2, and the heat dissipation efficiency of the first chip 3 in the packaging structure is improved. It will be appreciated that the specific position and size of the heat dissipation structure 2 may be determined according to the position and size of the first chip 3, which is not limited in the embodiment of the present invention.
The micro-channel holes 5 can be used for inputting a heat dissipation medium to dissipate heat, and can be realized by etching the switching structure 1. The micro-channel hole 5 is arranged on the adapter plate, penetrates through the adapter structure 1 along the first direction x and is communicated with the groove 4, and the projection of the micro-channel hole 5 on the plane surrounds the projection of the first chip 3 on the plane. It can be understood that, since the first chip 3 is disposed in the groove 4, and the micro-channel hole 5 is disposed around the first chip 3, the heat dissipation medium introduced into the micro-channel hole 5 can take away the heat of the first chip 3, so as to further improve the heat dissipation efficiency of the adapting structure 1. In some embodiments, the micro flow channel hole 5 may include a first micro flow channel part 51 and a second micro flow channel part 52 that are communicated, the first micro flow channel part 51 penetrates through a portion covered by the projection of the groove 4 on the plane along the first direction x, and the second micro flow channel part 52 is communicated with the groove 4. In addition, the heat dissipation hole 20 and the micro flow channel hole 5 can be prepared in the same process flow by adopting the same processing technology, and are completely compatible with the existing technology and equipment.
Illustratively, the interposer fabric 1 includes a recess 4, the recess 4 partially extending through the interposer fabric 1, and the first chip 3 is disposed in the recess 4. The heat dissipation structure 2 is disposed in the interposer fabric 1 and a projection of the first chip 3 on a plane covers the heat dissipation structure 2. The micro-channel hole 5 is arranged in the switching structure 1, the first micro-channel subsection 51 of the micro-channel hole 5 penetrates through the switching structure 1, and the projection of the first micro-channel subsection 51 on the plane is not overlapped with the projection of the first chip 3 on the plane; the second microchannel portion 52 communicates with the groove 4 and with the first microchannel portion 51. The heat dissipation medium can enter the second micro-channel part 52 through the first micro-channel part 51 and flow through the path of the second micro-channel part 52, and the heat dissipation medium can fully contact the surface of the first chip 3 because the second micro-channel part 52 is communicated with the groove 4, so that the heat on the surface of the first chip 3 is quickly taken away and flows out along the first micro-channel part 51. It will be appreciated that in the embodiment of the present invention, a first micro flow channel section 51 may be provided, and serve as both an inlet and an outlet for the heat dissipation medium; two micro-channel sections may be provided as an inlet and an outlet for the heat dissipation medium, respectively, which is not limited in the embodiment of the present invention. According to the technical scheme provided by the embodiment of the invention, the first chip 3 can rapidly conduct out heat through the heat radiation structure 2, and meanwhile, the heat can also be conducted out through the heat radiation medium in the micro-channel hole 5, so that the heat radiation efficiency of the switching structure 1 is greatly improved.
According to the technical scheme, the heat dissipation structure and the micro-channel holes are arranged in the switching structure, and the heat conductivity of the heat dissipation structure is larger than that of the switching structure, so that the first chip can conduct heat out through the heat dissipation structure, and the heat dissipation efficiency of the switching structure is improved; and the micro-flow channel holes are arranged around the side surface of the first chip, so that the heat dissipation medium can flow around the first chip, the heat dissipation of the first chip is realized, the heat dissipation efficiency of the switching structure is further improved, and the performance and the service life of the first chip are improved.
Optionally, with continued reference to fig. 1, the heat dissipation structure 2 includes a heat dissipation communication layer 21 and a plurality of heat dissipation posts 22;
The heat dissipation communication layer 21 is disposed between the first chip 3 and the interposer fabric 1 and connected to each heat dissipation post 22.
The heat dissipation post 22 may be disposed in the adapting structure 1, and the heat dissipation communication layer 21 may be disposed on the surface of the adapting structure 1 or in the adapting structure 1. The heat dissipation communication layer 21 connects each heat dissipation post 22 such that heat in each heat dissipation post 22 can be transferred to the heat dissipation communication layer 21, and the heat dissipation communication layer 21 further dissipates the heat.
Specifically, in the actual process of preparing the heat dissipation structure 2, the heat dissipation hole, which may be a TSV hole, is formed in the heat dissipation structure 1 by first etching the heat dissipation structure 1, and the heat dissipation hole may be filled with an electroplating process to form the heat dissipation column 22. Further, the heat dissipation communication layer 21 is manufactured by adopting processes such as photoetching, electroplating and etching, the heat dissipation communication layer 21 can be manufactured on the surface of the adapting structure 1, and the heat dissipation communication layer 21 is communicated with each heat dissipation column 22, so that heat in the chip is dissipated. It can be understood that the heat dissipation communication layer 21 is disposed between the first chip 3 and the adapting structure 1, so that the heat dissipation communication layer 21 can rapidly conduct out the heat of the first chip 3 to the heat dissipation post 22, thereby avoiding the heat aggregation from affecting the normal operation of the first chip 3.
In some embodiments, fig. 3 is a cross-sectional view of a second chip package structure according to an embodiment of the present invention, as shown in fig. 3, along a first direction x, a heat dissipation post 22 penetrates through the interposer fabric 1. The arrangement is such that the heat-dissipating studs 22 can transfer heat out of the adapter structure 1 quickly, avoiding accumulation in the adapter structure 1. The heat dissipation communication layers 21 can be further arranged at two ends of the heat dissipation column 22, namely the heat dissipation communication layers 21 are arranged on the surface, close to the first chip 3, of the switching structure 1 and the surface, far away from the first chip 3, of the switching structure 1, so that the heat dissipation communication layers 21 on the upper surface can rapidly guide out the heat of the first chip 3 to the heat dissipation column 22, the heat dissipation column 22 rapidly guides out the heat to the heat dissipation communication layers 21 on the lower surface, the heat dissipation communication layers 21 on the lower surface are further caused to rapidly dissipate the heat, the heat dissipation efficiency of the heat dissipation structure 2 is further improved, and the influence of heat aggregation on the performance and the service life of the first chip 3 is avoided.
According to the technical scheme, the heat dissipation structure comprises the heat dissipation communication layer and the plurality of heat dissipation columns, so that the heat dissipation communication layer conducts heat of the first chip to the heat dissipation columns, and then the heat dissipation columns in the adapter plate conduct heat, so that heat accumulation in the first chip is prevented from damaging the adapter structure and the first chip, and the heat dissipation performance of the chip packaging structure is improved.
Alternatively, as shown in fig. 2 and 3, the first chip 3 includes a first chip body 31 and a first chip electrode 32 located at one side of the first chip body 31;
The first chip electrode 32 is located at one side of the first chip body 31 close to the heat dissipation structure 2;
The chip package structure further includes a rewiring structure 6 and a first pin connection structure 71; the rewiring structure 6 is electrically connected to the first chip electrode 32 and the first pin connection structure 71, respectively; the first pin connection structure 71 penetrates through the switching structure 1 along the first direction x.
The first chip 3 includes a first chip body 31 and a first chip electrode 32 located at one side of the first chip body 31, and the connection between the first chip 3 and other wiring structures can be achieved through the switching structure 1. The first chip electrode 32 is located on the side of the first chip body 31 close to the heat dissipation structure 2, so that the first chip 3 is connected to the interposer fabric 1 in a flip-chip manner.
The first pin connection structure 71 may be realized by etching the adapting structure 1 to form a pin connection hole and electroplating the filling metal, and the first pin connection structure 71 needs to penetrate through the adapting structure 1 along the first direction x to realize the connection function of the first chip 3 and other wirings. The redistribution structure 6 may be implemented on the surface of the interposer by using processes such as photolithography, electroplating, and etching, where the redistribution structure 6 needs to connect the first pin connection structure 71 with an electrode of the first chip 3, so as to implement a connection function between the first chip 3 and other wirings.
It can be understood that, since the electrode position of the first chip 3 is related to the placement position of the first chip 3 and the model of the first chip 3, the rerouting structure 6 can be fabricated according to the electrode preset position of the first chip 3 to ensure the connection relationship of the rerouting structure 6.
In some embodiments, the heat dissipation holes, the pin connection holes and the micro flow channel holes 5 may be etched in the same step, and when the heat dissipation structure 2 and the first pin connection structure 71 are made of the same material, the heat dissipation pillars 22 and the first pin connection structure 71 may also be implemented in the same step by using an electroplating process. Meanwhile, the heat dissipation communication layer 21 and the rerouting structure 6 can be manufactured by adopting photolithography, electroplating, etching and other works in the same step, so that the process compatibility is improved.
According to the technical scheme provided by the embodiment of the invention, the first chip is connected with the first pin connection structure in a flip-chip manner by the arrangement of the rewiring structure and the first pin connection structure, so that the first chip is vertically conducted in the chip packaging structure, the 2.5D/3D packaging of the first chip is further realized, and the integration level of the chip packaging is improved.
Optionally, fig. 4 is a cross-sectional view of a third chip package structure provided according to an embodiment of the present invention, and as shown in fig. 4, the chip package structure further includes a second chip 8 and a second pin connection structure 72; the second chip 8 is arranged in a lamination manner with the first chip 3, and the second chip 8 is positioned at one side of the first chip 3 far away from the heat dissipation structure 2;
The second chip 8 includes a second chip body 81 and a second chip electrode 82 located at one side of the second chip body 81; the second chip electrode 82 is located at one side of the second chip body 81 close to the heat dissipation structure 2;
the second pin connection structure 72 penetrates through the adapting structure 1 and is electrically connected with the second chip electrode 82.
The second chip 8 is stacked with the first chip 3, and the second pin connection structure 72 penetrates through the second chip electrode 82 of the switching structure 1, so that the second chip 8 is connected with the switching structure 1 in a flip-chip manner.
The second pin connection structure 72 can be realized by etching the switching structure 1 to form pin connection holes and electroplating filling metal, and the second pin connection structure 72 needs to penetrate through the switching structure 1 along the first direction x to realize the connection function of the second chip 8 and other wirings.
It can be understood that, on the basis of the switching structure 1, the second chip 8 and the first chip 3 are stacked, and the second chip 8 and the first chip 3 can be vertically conducted in the same switching structure 1, so that the multi-chip stacked package based on 2.5D/3D is realized, the heat dissipation efficiency is ensured, and meanwhile, the integration level of the chip package is further improved.
Alternatively, fig. 5 is a cross-sectional view of a fourth chip package structure provided according to an embodiment of the present invention, and fig. 6 is a cross-sectional view of a first adapter plate provided according to an embodiment of the present invention, and as shown in conjunction with fig. 5 and 6, the micro flow channel hole 5 includes a first micro flow channel section 51 and a second micro flow channel section 52 penetrating therethrough;
The switching structure 1 comprises a first switching plate 11 and a second switching plate 12 which are arranged in a laminated mode; the heat dissipation structure 2 and the first micro flow path section 51 are provided in the first adapter plate 11 and the first micro flow path section 51 penetrates the first adapter plate 11; the groove 4 and the second micro flow channel subsection 52 penetrate through the second adapter plate 12, and the second micro flow channel subsection 52 is communicated with the groove 4;
The first pin connection structure 71 penetrates through the first adapter plate 11 along the first direction x; the rewiring structure 6 is arranged between the first interposer 11 and the second interposer 12.
The switching structure 1 includes a first switching plate 11 and a second switching plate 12, and the first switching plate 11 and the second switching plate 12 may be the same or different in size, and the first switching plate 11 and the second switching plate 12 are stacked to form the switching structure 1. The first adapter plate 11 and the second adapter plate 12 may be manufactured in steps.
Since the micro flow channel hole 5 is a through hole and penetrates through the first adapter plate 11 and the second adapter plate 12, the micro flow channel hole 5 is divided into a first micro flow channel part 51 and a second micro flow channel part 52, the first micro flow channel part 51 penetrates through the first adapter plate 11, and the second micro flow channel part 52 penetrates through the second adapter plate 12, and the micro flow channel can be manufactured in steps.
Specifically, first, the first adapter plate 11 is first prepared, and the heat dissipation holes, the pin connection holes, and the first micro flow channel portions 51 may be formed on the first adapter plate 11 by using processes such as temporary bonding, thinning, photolithography, and TSV etching, and the material is filled at least in the heat dissipation holes to form the heat dissipation posts 22 by using a plating filling process, and the material is filled in the pin connection holes to form the first pin connection structures 71. And then the preparation of the heat dissipation communication layer 21 and the rerouting structure 6 is completed on the surface of the first adapter plate 11 by adopting the processes of photoetching, electroplating, etching and the like. And preparing a second adapter plate 12, preparing a groove 4 on the second adapter plate 12 by adopting the processes of temporary bonding, thinning, photoetching, TSV etching and the like, wherein the size of the groove 4 is larger than that of the first chip 3. The second interposer 12 is disposed on the side of the rerouting structure 6 remote from the first interposer 11, and the electrodes of the first chip 3 are connected to the rerouting structure 6 in a bonding manner. Since the size of the first chip 3 is smaller than the size of the groove 4, when the first chip 3 is connected to the first adapter plate 11, a gap exists between the groove 4 and the first chip 3, and the gap is the second micro flow channel portion 52, and the second micro flow channel portion 52 is communicated with the first micro flow channel portion 51, so that the package connection of the first chip 3 is completed. In addition, the gap between the first chip 3 and the first adapter plate 11 may be filled in an underfill manner, so as to prevent vapor from entering and affecting the normal operation of the first chip 3.
According to the technical scheme, the heat dissipation structure and the first micro-channel subsection are arranged in the first adapter plate, the grooves and the second micro-channel subsection are arranged in the second adapter plate, the first adapter plate and the second adapter plate are arranged in a laminated mode, and the second micro-channel subsection is formed by utilizing the gaps between the first chip and the grooves, so that gaps between the second adapter plate and the first chip are effectively utilized, the size requirement on the chip packaging structure is smaller, the chip packaging structure is miniaturized, and meanwhile the purpose of heat dissipation is achieved.
Optionally, fig. 7 is a top view of a fourth chip package structure provided according to an embodiment of the present invention, and as shown in conjunction with fig. 5 and fig. 7, the chip package structure further includes: a first sealing layer 91;
The first sealing layer 91 covers at least the upper surface and the side surfaces of the first chip 3, the side surfaces of the second micro flow path section 52, and the upper surface of the second interposer 12.
When the heat dissipation medium in the micro flow channel hole 5 is a liquid medium and the first chip 3 has no waterproof performance, the heat dissipation medium affects the normal operation of the first chip 3, so the chip package structure includes a first sealing layer 91, and the first sealing layer 91 can be used for isolating the first chip 3 from contact with the heat dissipation medium. The first sealing layer 91 is disposed to cover at least the upper surface and the side surface of the first chip 3, so that the first sealing layer 91 plays a role in protecting the first chip 3, and at the same time, the first sealing layer 91 covers the side surface of the second micro flow channel subsection 52 and the upper surface of the second interposer 12, so that the first sealing layer 91 plays a role in protecting the second interposer 12.
Specifically, the first sealing layer 91 may be prepared by using a film-covered and heated photolithography process to prepare the first sealing layer 91, so that the first sealing layer 91 covers the upper surface and the side surface of the first chip 3, the side surface of the second micro flow channel part 52 and the upper surface of the second adapter plate 12, and simultaneously exposes the first micro flow channel part 51, so that the heat dissipation medium of the first micro flow channel part 51 may enter the second micro flow channel part 52, and meanwhile, the medium of the second micro flow channel part 52 may avoid contact with the first chip 3, thereby ensuring the performance and the service life of the first chip 3.
According to the technical scheme, the first sealing layer is arranged, so that the first sealing layer covers the upper surface and the side surface of the first chip, the side surface of the second micro-channel subsection and the upper surface of the second adapter plate, the first chip is isolated from the heat dissipation medium, the heat dissipation medium is prevented from directly contacting the first chip, and the performance and the service life of the first chip are guaranteed.
Optionally, fig. 8 is a cross-sectional view of a fifth chip package structure provided according to an embodiment of the present invention, and as shown in fig. 8, the chip package structure further includes: a second sealing layer 92;
The second sealing layer 92 is disposed on the side of the first sealing layer 91 away from the first chip 3, and covers the upper surface of the first chip 3, the micro flow channel hole 5, and the upper surface of the second interposer 12.
The materials of the second sealing layer 92 and the first sealing layer 91 may be the same or different, so that the heat dissipation medium may be isolated. The second sealing layer 92 is disposed on a side of the first sealing layer 91 away from the first chip 3, and covers the upper surface of the first chip 3, the micro-fluidic channel hole 5 and the upper surface of the second adapter plate 12, so that the micro-fluidic channel hole 5 forms a semi-closed structure, that is, the surface of the micro-fluidic channel hole 5 close to the second adapter plate 12 is sealed by the second sealing layer 92, the surface of the micro-fluidic channel hole 5 close to the first adapter plate 11 is not sealed, and the heat dissipation medium can enter from below the first adapter plate 11 to flow along the path of the second micro-fluidic channel subsection 52 and then flow out along below the first adapter plate 11 to take away heat, so that the heat dissipation medium cannot flow out from the surface of the side of the second adapter plate 12 away from the first adapter plate 11, and the heat dissipation medium is prevented from affecting the structure or the chip of the side of the second adapter plate 12 away from the first adapter plate 11, and the circulation path of the heat dissipation medium is fixed. Meanwhile, the second sealing layer 92 covers the upper surface of the first chip 3 and the upper surface of the second adapter plate 12, so that heat dissipation medium is prevented from flowing out along a gap between the first adapter plate 11 and the second adapter plate 12, and the semi-tightness of the micro flow channel is ensured.
It can be understood that the covering positions of the first sealing layer 91 and the second sealing layer 92 are different, so that the setting process is different, and the second sealing layer 92 can adopt a film-covering process but not heating process, so as to ensure the sealing effect of the second sealing layer 92.
The embodiment of the invention can comprise a plurality of first chips 3, and the plurality of first chips 3 can be provided with a plurality of corresponding heat dissipation structures 2 and micro-channel holes 5 so as to ensure the heat dissipation effect of the chips.
According to the technical scheme, the second sealing layer is arranged, so that the second sealing layer covers the upper surface of the first chip, the micro-channel holes and the upper surface of the second adapter plate, and the micro-channel holes are of a semi-closed structure by combining with the first sealing layer, so that the circulation path of a heat dissipation medium is ensured, the heat dissipation medium is prevented from affecting other structures and normal work of the chip, and meanwhile, the heat dissipation performance of the heat dissipation medium on the first chip is ensured.
Based on the same inventive concept, fig. 9 is a flowchart of a method for manufacturing a first chip package structure according to an embodiment of the present invention, and fig. 10 is a structure diagram corresponding to the method for manufacturing a first chip package structure according to an embodiment of the present invention, and further provides a method for manufacturing a chip package structure, where, in conjunction with fig. 9 and fig. 10, the method for manufacturing includes:
S10, providing a switching structure and etching the switching structure, wherein grooves, heat dissipation holes and micro-channel holes are formed in the switching structure.
Wherein, the recess 4, the heat dissipation hole 20 and the micro flow channel hole 5 may be formed in the interposer fabric 1 by using processes such as temporary bonding, thinning, photolithography and TSV etching, as shown in step (a) of fig. 10. The recess 4 partially penetrates the switching structure 1 along the first direction x, the micro-channel hole 5 completely penetrates the switching structure 1 along the first direction x, and the heat dissipation hole 20 may partially or completely penetrate the switching structure 1 along the first direction x. The micro-channel holes 5 can be used for inputting a heat dissipation medium to realize heat dissipation.
S11, growing a heat dissipation structure at least in the heat dissipation holes. Wherein the heat conductivity of the heat dissipation structure 2 is greater than the heat conductivity of the interposer fabric 1.
Wherein, the heat-dissipating structure 2 is grown by electroplating and filling process, and the heat-dissipating studs 22 are formed in the heat-dissipating holes 20, as shown in step (b) of fig. 10. In order to improve the heat dissipation efficiency of the interposer fabric 1, the heat dissipation structure 2 needs to have a thermal conductivity greater than that of the interposer fabric 1.
S12, providing a first chip and arranging the first chip in the groove.
Wherein, set up the first chip 3 in recess 4, the heat in the first chip 3 can utilize heat radiation structure 2 and micro flow channel hole 5 to dispel.
Specifically, the heat dissipation hole 20, the groove 4 and the micro flow channel hole 5 may be formed on the adapting structure 1 by using processes such as temporary bonding, thinning, photolithography and TSV etching, as shown in step (c) of fig. 10, and at least the heat dissipation hole 20 is filled with a material by using a plating filling process to form the heat dissipation structure 2. The first chip 3 is connected with the switching structure 1 in a bonding mode, a heat dissipation medium is introduced into the micro-channel hole 5, and heat of the first chip 3 is discharged by utilizing the heat dissipation medium and the heat dissipation structure 2.
According to the technical scheme, the heat dissipation structure and the micro-channel holes are prepared in the switching structure, and the heat conductivity of the heat dissipation structure is larger than that of the switching structure, so that the first chip can conduct heat out through the heat dissipation structure, and the heat dissipation efficiency of the switching structure is improved; and meanwhile, the micro-channel holes are formed to surround the side surface of the first chip, so that the heat dissipation medium can flow around the first chip, the heat dissipation of the first chip is realized, the heat dissipation efficiency of the switching structure is further improved, and the performance and the service life of the first chip are improved.
On the basis of the foregoing embodiment, fig. 11 is a flowchart of a method for manufacturing a second chip package structure according to an embodiment of the present invention, and fig. 12 is a structure diagram corresponding to a method for manufacturing a second chip package structure according to an embodiment of the present invention, where, in combination with fig. 11 and fig. 12, the manufacturing method includes:
S20, providing a first adapter plate, etching the first adapter plate, and forming a heat dissipation hole, a micro-channel hole and a pin connecting hole in the first adapter plate.
Wherein, the heat dissipation holes 20, the micro flow path holes 5, and the pin connection holes 7 may be formed on the first adapter plate 11 using processes such as temporary bonding, thinning, photolithography, and TSV etching, as shown in step (d) of fig. 12. Since the heat dissipation hole 20, the micro flow channel hole 5, and the pin connection hole 7 may be through holes of the first adapter plate 11, they may be provided in the same step.
S21, providing a second adapter plate, etching the second adapter plate, and forming a groove in the second adapter plate.
Wherein, the recess 4 may be formed on the second interposer 12 using temporary bonding, thinning, photolithography, TSV etching, and the like, as shown in step (e) of fig. 12. The dimensions of the first adapter plate 11 and the second adapter plate 12 may be the same or different, which is not limited in the embodiment of the present invention.
S22, growing a heat radiation column in the heat radiation structure in the heat radiation hole, and growing a first pin connection structure in the pin connection hole.
As shown in step (f) of fig. 12, the heat dissipation post 22 and the first pin connection structure 71 may be grown in the heat dissipation hole 20 and the pin connection hole 7 at the same time by electroplating metal.
S23, arranging the second adapter plate on one side of the first adapter plate.
As shown in step (g) of fig. 12, the second interposer 12 is disposed on the first interposer 11 side, and may be connected by bonding. The pin connection holes 7 may also be prepared in the first interposer 11 and the second interposer 12, and plated to form the third pin connection structure 721 and the fourth pin connection structure 722, respectively, and the third pin connection structure 721 and the fourth pin connection structure 722 are bonded to form the connection of the first interposer 11 and the second interposer 12. The second pin connection structure 72 may be divided into a third pin connection structure 721 and a fourth pin connection structure 722.
S24, providing a first chip and arranging the first chip in the groove. As shown in step (h) of fig. 12.
Specifically, first, the first adapter plate 11 is first prepared, the heat dissipation hole 20, the micro flow channel hole 5 and the pin connection hole 7 may be formed on the first adapter plate 11 by using processes such as temporary bonding, thinning, photolithography and TSV etching, and the material is filled at least in the heat dissipation hole 20 to form the heat dissipation post 22 by using a process of electroplating filling, and the material is filled in the pin connection hole 7 to form the first pin connection structure 71. And preparing a second adapter plate 12, preparing a groove 4 on the second adapter plate 12 by adopting the processes of temporary bonding, thinning, photoetching, TSV etching and the like, wherein the size of the groove 4 is larger than that of the first chip 3. The second interposer 12 is disposed on one side of the first interposer 11, and connects the first chip 3 with the first lead connection structure 71 in a bonding manner, thereby completing the chip package.
According to the technical scheme provided by the embodiment of the invention, the first pin connection structure is prepared while the heat dissipation structure is prepared, and the first chip is connected with the first pin connection structure in a flip-chip manner, so that the first chip is vertically conducted in the chip packaging structure, the 2.5D/3D packaging of the first chip is further realized, and the integration level of the chip packaging is improved.
On the basis of the foregoing embodiment, fig. 13 is a flowchart of a method for manufacturing a third chip package structure according to an embodiment of the present invention, and fig. 14 is a structure diagram corresponding to a method for manufacturing a third chip package structure according to an embodiment of the present invention, where, in combination with fig. 13 and fig. 14, the manufacturing method includes:
s30, providing a first adapter plate, etching the first adapter plate, and forming a heat dissipation hole, a micro-channel hole and a pin connecting hole in the first adapter plate. As shown in step (i) of fig. 14.
And S31, providing a second adapter plate, etching the second adapter plate, and forming a groove in the second adapter plate. As shown in step (j) of fig. 14.
S32, growing a heat radiation column in the heat radiation structure in the heat radiation hole, and growing a first pin connection structure in the pin connection hole. As shown in step (k) of fig. 14.
And S33, growing a wiring layer on the surface of the first adapter plate and etching the wiring layer to form a heat dissipation communication layer and a re-wiring structure. Wherein the heat dissipation communication layer 21 is connected to each heat dissipation post 22, and the rewiring structure 6 is electrically connected to the first pin connection structure 71. As shown in step (l) of fig. 14.
The redistribution structure 6 may be implemented on the surface of the interposer by using processes such as photolithography, electroplating, and etching, where the redistribution structure 6 needs to connect the first pin connection structure 71 with an electrode of the first chip 3, so as to implement a connection function between the first chip 3 and other wirings. The heat dissipation communication layer 21 connects each heat dissipation post 22 such that heat in each heat dissipation post 22 can be transferred to the heat dissipation communication layer 21, and the heat dissipation communication layer 21 further dissipates the heat.
S34, arranging the second adapter plate on one side of the first adapter plate. As shown in step (m) of fig. 14.
S35, providing a first chip and arranging the first chip in the groove. As shown in step (n) of fig. 14.
Specifically, in the process of actually preparing the heat dissipation communication layer 21 and the rerouting structure 6, after the heat dissipation posts 22 and the first pin connection structure 71 are prepared, the heat dissipation communication layer 21 and the rerouting structure 6 are manufactured by adopting processes such as photolithography, electroplating, etching and the like, the heat dissipation communication layer 21 is manufactured on the surface of the adapting structure 1, and the heat dissipation communication layer 21 is communicated with each heat dissipation post 22, so that heat in the chip is dissipated. The rerouting structure 6 is connected to the first pin connection structure 71, and the electrode of the first chip 3 is bonded to the rerouting structure 6 to complete the connection of the first pin connection structure 71 to the first chip 3.
According to the technical scheme provided by the embodiment of the invention, the rewiring structure and the heat dissipation communication layer are prepared in the same process flow, so that the heat dissipation of the switching structure is improved, the process flow is not increased, and the process compatibility is improved.
On the basis of the above embodiment, fig. 15 is a flowchart of a method for manufacturing a fourth chip package structure according to an embodiment of the present invention, and fig. 16 is a structure diagram corresponding to a method for manufacturing a fourth chip package structure according to an embodiment of the present invention, and as shown in fig. 15 and 16, the micro flow channel hole 5 includes a first micro flow channel portion 51 and a second micro flow channel portion 52 penetrating therethrough; the second micro flow channel subsection 52 penetrates through the second adapter plate 12 and is communicated with the groove 4; the preparation method comprises the following steps:
S40, providing a first adapter plate, etching the first adapter plate, and forming a heat dissipation hole, a micro-channel hole and a pin connecting hole in the first adapter plate. As shown in step (o) of fig. 16.
S41, providing a second adapter plate, etching the second adapter plate, and forming a groove in the second adapter plate. As shown in step (p) of fig. 16.
S42, growing a heat radiation column in the heat radiation structure in the heat radiation hole, and growing a first pin connection structure in the pin connection hole. As shown in step (q) of fig. 16.
S43, arranging the second adapter plate on one side of the first adapter plate. As shown in step (r) of fig. 16.
S44, providing a first chip and arranging the first chip in the groove. As shown in step(s) of fig. 16.
S45, a first sealing layer is arranged on one side, far away from the switching structure, of the first chip, and the first sealing layer is etched so that the first sealing layer at least covers the upper surface and the side face of the first chip, the side face of the second micro-channel subsection and the upper surface of the second switching plate. As shown in step (t) of fig. 16.
Since the micro flow channel hole 5 is a through hole and penetrates through the first adapter plate 11 and the second adapter plate 12, the micro flow channel hole 5 is divided into a first micro flow channel part 51 and a second micro flow channel part 52, the first micro flow channel part 51 penetrates through the first adapter plate 11, and the second micro flow channel part 52 penetrates through the second adapter plate 12, and the micro flow channel can be manufactured in steps.
When the heat dissipation medium in the micro flow channel hole 5 is a liquid medium and the first chip 3 has no waterproof performance, the heat dissipation medium can affect the normal operation of the first chip 3, so the chip packaging structure is provided with the first sealing layer 91, and the first sealing layer 91 can be prepared by adopting a film-covered heating photoetching process, so that the first sealing layer 91 covers the upper surface and the side surface of the first chip 3, the side surface of the second micro flow channel part 52 and the upper surface of the second adapter plate 12, and simultaneously the first micro flow channel part 51 is exposed by etching, so that the heat dissipation medium of the first micro flow channel part 51 can enter the second micro flow channel part 52, and meanwhile, the middle heat dissipation medium of the second micro flow channel part 52 can avoid contacting with the first chip 3, thereby ensuring the performance and the service life of the first chip 3.
And S46, arranging a second sealing layer on one side of the first sealing layer far away from the switching structure, so that the second sealing layer covers the upper surface of the first chip, the micro-channel hole and the upper surface of the second switching plate. As shown in step (u) of fig. 16.
In some embodiments, a second chip 8 may be further disposed on a side of the second sealing layer 92 away from the first chip 3, and an electrode of the second chip 8 is connected to the second pin connection structure 72 in the second interposer 12, so as to implement a stack package of the first chip 3 and the second chip 8. As shown in step (v) of fig. 16.
The materials of the second sealing layer 92 and the first sealing layer 91 may be the same or different, so that the heat dissipation medium may be isolated. The second sealing layer 92 may be disposed on the side of the first sealing layer 91 away from the first chip 3 by a film coating process but not heating, and covers the upper surface of the first chip 3, the micro-fluidic channel hole 5 and the upper surface of the second adapter plate 12, so that the micro-fluidic channel hole 5 forms a semi-closed structure, that is, the surface of the micro-fluidic channel hole 5 close to the second adapter plate 12 is sealed by the second sealing layer 92, the surface of the micro-fluidic channel hole 5 close to the first adapter plate 11 is not sealed, and the heat dissipation medium can enter from below the first adapter plate 11, flow along the path of the second micro-fluidic channel part 52, and then flow out from below the first adapter plate 11, so that the heat dissipation medium cannot flow out from the surface of the side of the second adapter plate 12 away from the first adapter plate 11, thereby preventing the heat dissipation medium from affecting the structure or the chip of the side of the second adapter plate 12 away from the first adapter plate 11, and fixing the circulation path of the heat dissipation medium. Meanwhile, the second sealing layer 92 covers the upper surface of the first chip 3 and the upper surface of the second adapter plate 12, so that heat dissipation medium is prevented from flowing out along a gap between the first adapter plate 11 and the second adapter plate 12, and the semi-tightness of the micro flow channel is ensured.
Illustratively, first, the first adapter plate 11 is first prepared, the heat dissipation holes 20, the pin connection holes 7, and the first micro flow channel portions 51 may be formed on the first adapter plate 11 using temporary bonding, thinning, photolithography, TSV etching, and the like, and the heat dissipation pillars 22 may be formed by filling at least the heat dissipation holes 20 with a material using a plating filling process, and the first pin connection structures 71 may be formed by filling the pin connection holes 7 with a material. And then the preparation of the heat dissipation communication layer 21 and the rerouting structure 6 is completed on the surface of the first adapter plate 11 by adopting the processes of photoetching, electroplating, etching and the like. And preparing a second adapter plate 12, preparing a groove 4 on the second adapter plate 12 by adopting the processes of temporary bonding, thinning, photoetching, TSV etching and the like, wherein the size of the groove 4 is larger than that of the first chip 3. The second interposer 12 is disposed on the side of the rerouting structure 6 remote from the first interposer 11, and the electrodes of the first chip 3 are connected to the rerouting structure 6 in a bonding manner. Since the size of the first chip 3 is smaller than the size of the groove 4, when the first chip 3 is connected to the first adapter plate 11, a gap exists between the groove 4 and the first chip 3, and the gap is the second micro flow channel portion 52, and the second micro flow channel portion 52 is communicated with the first micro flow channel portion 51. Further, the gap between the first chip 3 and the first adapter plate 11 is filled in an underfill mode, so that the normal operation of the first chip 3 is affected by the entering of waterproof vapor. The first sealing layer 91 is then prepared using a photolithographic process of film-coating heating such that the first sealing layer 91 covers the upper surface and side surfaces of the first chip 3, the side surfaces of the second micro flow path sections 52 and the upper surface of the second interposer 12 and exposes the rerouting structures 6 and the first micro flow path sections 51. And then preparing the second sealing layer 92 by adopting a film-coating non-heating process, so that the second sealing layer 92 covers the upper surface of the first chip 3, the micro-channel holes 5 and the upper surface of the second adapter plate 12, and semi-closed preparation of the micro-channel holes 5 is completed. In addition, when the package structure includes the second chip 8, the second interposer 12 needs to be etched to expose the second pin connection structure 72, and the electrodes of the second chip 8 are bonded to the second pin connection structure 72, so as to complete the multi-chip package.
According to the technical scheme, the first sealing layer and the second sealing layer are arranged, so that the first sealing layer covers the upper surface and the side surface of the first chip, the side surface of the second micro-channel subsection and the upper surface of the second adapter plate, the second sealing layer covers the upper surface of the first chip, the micro-channel holes and the upper surface of the second adapter plate, and the micro-channel holes are formed in a semi-closed structure through combination of the first sealing layer and the second sealing layer, so that the circulation path of a heat dissipation medium is ensured, the heat dissipation medium is prevented from affecting other structures and normal work of the chip, and meanwhile, the heat dissipation performance of the heat dissipation medium on the first chip is ensured.
The above embodiments do not limit the scope of the present invention. It will be apparent to those skilled in the art that various modifications, combinations, sub-combinations and alternatives are possible, depending on design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of the present invention.
Claims (11)
1. A chip package structure, comprising: the LED comprises an adapter structure, a heat dissipation structure and a first chip;
A groove is arranged in the switching structure; the groove penetrates through part of the switching structure; the first chip is arranged in the groove;
The heat dissipation structure is arranged in the switching structure and overlapped with the first chip along a first direction; wherein the first direction is the thickness direction of the switching structure; the heat conductivity of the heat dissipation structure is greater than that of the switching structure;
The micro-channel holes penetrate through the switching structure along the first direction and are communicated with the grooves;
The projection of the micro-channel hole on the plane surrounds the projection of the first chip on the plane; wherein the plane is perpendicular to the first direction;
The micro-channel hole comprises a first micro-channel subsection and a second micro-channel subsection which penetrate through the micro-channel hole;
The switching structure comprises a first switching plate and a second switching plate which are arranged in a laminated mode; the heat dissipation structure and the first micro-channel subsection are arranged in the first adapter plate, and the first micro-channel subsection penetrates through the first adapter plate; the groove and the second micro-channel subsection penetrate through the second adapter plate, and the second micro-channel subsection is communicated with the groove;
The chip packaging structure further comprises: a first sealing layer;
The first sealing layer at least covers the upper surface and the side surface of the first chip, the side surface of the second micro flow channel subsection and the upper surface of the second adapter plate.
2. The chip package structure of claim 1, wherein the heat dissipation structure comprises a heat dissipation communication layer and a plurality of heat dissipation pillars;
the heat dissipation communication layer is arranged between the first chip and the switching structure and is connected with each heat dissipation column.
3. The chip package structure of claim 2, wherein the heat spreader pillar extends through the interposer fabric along the first direction.
4. The chip package structure according to claim 1, wherein the first chip includes a first chip body and a first chip electrode located at one side of the first chip body;
The first chip electrode is positioned at one side of the first chip body close to the heat dissipation structure;
The chip packaging structure further comprises a rewiring structure and a first pin connecting structure; the rewiring structure is electrically connected with the first chip electrode and the first pin connecting structure respectively; the first pin connection structure penetrates through the switching structure along the first direction.
5. The chip package structure of claim 4, further comprising a second chip and a second pin connection structure; the second chip and the first chip are arranged in a stacked manner, and the second chip is positioned at one side of the first chip far away from the heat dissipation structure;
the second chip comprises a second chip body and a second chip electrode positioned at one side of the second chip body; the second chip electrode is positioned at one side of the second chip body close to the heat dissipation structure;
The second pin connection structure penetrates through the switching structure and is electrically connected with the second chip electrode.
6. The chip package structure of claim 4, wherein the first pin connection structure extends through the first interposer along the first direction; the rewiring structure is disposed between the first interposer and the second interposer.
7. The chip package structure according to claim 1, further comprising: a second sealing layer;
the second sealing layer is arranged on one side, far away from the first chip, of the first sealing layer and covers the upper surface of the first chip, the micro-channel hole and the upper surface of the second adapter plate.
8. A method for manufacturing a chip package structure, characterized by being used for manufacturing the chip package structure according to any one of claims 1 to 7; the preparation method comprises the following steps:
providing a switching structure and etching the switching structure, wherein a groove, a heat dissipation hole and a micro-channel hole are formed in the switching structure;
growing a heat dissipation structure at least in the heat dissipation holes; wherein, the heat conductivity of the heat dissipation structure is greater than the heat conductivity of the switching structure;
providing a first chip and arranging the first chip in the groove;
providing a transfer structure and etching the transfer structure, forming a groove, a heat dissipation hole and a micro-channel hole in the transfer structure, and comprising:
providing a first adapter plate, etching the first adapter plate, and forming a heat dissipation hole, a micro-channel hole and a pin connecting hole in the first adapter plate;
providing a second adapter plate and etching the second adapter plate, and forming a groove in the second adapter plate;
the micro-channel hole comprises a first micro-channel part and a second micro-channel part which penetrate through the micro-channel hole; the second micro-channel part penetrates through the second adapter plate and is communicated with the groove;
After providing the first chip and disposing the first chip in the groove, the method further includes:
And a first sealing layer is arranged on one side of the first chip far away from the switching structure, and the first sealing layer is etched so that the first sealing layer at least covers the upper surface and the side surface of the first chip, the side surface of the second micro-channel part and the upper surface of the second switching plate.
9. The method according to claim 8, wherein,
Growing a heat dissipation structure at least in the heat dissipation holes, comprising:
growing a heat radiation column in the heat radiation structure in the heat radiation hole, and growing a first pin connection structure in the pin connection hole;
And arranging the second adapter plate at one side of the first adapter plate.
10. The method of manufacturing according to claim 9, wherein the second adapter plate is provided before the first adapter plate side, further comprising:
growing a wiring layer on the surface of the first adapter plate and etching the wiring layer to form a heat dissipation communication layer and a re-wiring structure; the heat dissipation communication layer is connected with each heat dissipation column, and the rewiring structure is electrically connected with the first pin connection structure.
11. The method according to claim 8, wherein,
After providing the first chip and disposing the first chip in the groove, the method further includes:
And a second sealing layer is arranged on one side, far away from the switching structure, of the first sealing layer, so that the second sealing layer covers the upper surface of the first chip, the micro-channel hole and the upper surface of the second switching plate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202411067626.4A CN118588667B (en) | 2024-08-06 | 2024-08-06 | Chip packaging structure and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202411067626.4A CN118588667B (en) | 2024-08-06 | 2024-08-06 | Chip packaging structure and preparation method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN118588667A CN118588667A (en) | 2024-09-03 |
| CN118588667B true CN118588667B (en) | 2024-11-19 |
Family
ID=92534541
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202411067626.4A Active CN118588667B (en) | 2024-08-06 | 2024-08-06 | Chip packaging structure and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN118588667B (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116013885A (en) * | 2023-01-05 | 2023-04-25 | 华进半导体封装先导技术研发中心有限公司 | Chip heat dissipation packaging structure and forming method thereof |
| CN116230667A (en) * | 2022-12-28 | 2023-06-06 | 江苏中科智芯集成科技有限公司 | Semiconductor packaging structure and preparation method |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108766897B (en) * | 2018-06-12 | 2020-05-08 | 厦门大学 | Encapsulation method of three-dimensional heterostructure for realizing high-power GaN device layer heat dissipation |
-
2024
- 2024-08-06 CN CN202411067626.4A patent/CN118588667B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116230667A (en) * | 2022-12-28 | 2023-06-06 | 江苏中科智芯集成科技有限公司 | Semiconductor packaging structure and preparation method |
| CN116013885A (en) * | 2023-01-05 | 2023-04-25 | 华进半导体封装先导技术研发中心有限公司 | Chip heat dissipation packaging structure and forming method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN118588667A (en) | 2024-09-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI515846B (en) | Package and method of conducting heat in package | |
| KR102585621B1 (en) | Integrated circuit package and method | |
| CN109786340B (en) | Integrated fan-out package and method of forming the same | |
| US7015572B2 (en) | Three-dimensionally mounted semiconductor module and three-dimensionally mounted semiconductor system | |
| CN107342277B (en) | Packaging part and forming method thereof | |
| CN102214641B (en) | Wafer-level semiconductor package with stacking capability | |
| CN113658944B (en) | Semiconductor package and method of forming the same | |
| CN100411169C (en) | Apparatus and method for cooling semiconductor integrated circuit chip package | |
| JP2022027650A (en) | Package semiconductor device including liquid cooling lid and formation method | |
| JP5298762B2 (en) | Stacked semiconductor device, manufacturing method of stacked semiconductor device, and semiconductor substrate | |
| TWI582917B (en) | Multi-chip package having encapsulation body to replace substrate core | |
| TW201701404A (en) | Package structure and method thereof | |
| CN202384323U (en) | Semiconductor Package Structure | |
| JP6083516B2 (en) | Micro-channel heat exchange device and electronic equipment | |
| US9418976B2 (en) | Chip stack with electrically insulating walls | |
| CN106486459A (en) | Face-up semiconductor assembly having semiconductor device in dielectric recess | |
| CN207800597U (en) | Semiconductor device | |
| KR102774034B1 (en) | Info packages including thermal dissipation blocks | |
| CN221102070U (en) | Package | |
| KR102573008B1 (en) | Semiconductor devices and methods of manufacture | |
| US20190295909A1 (en) | Package substrate for semiconductor package, semiconductor package including the same and method of manufacturing the same | |
| CN118588667B (en) | Chip packaging structure and preparation method thereof | |
| TW202125732A (en) | Package structure and method of forming the same | |
| CN220400576U (en) | Device package and semiconductor package | |
| CN222896685U (en) | Semiconductor packaging |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |