CN118588129B - Magnetic storage structure and magnetic storage module - Google Patents

Abstract

The embodiments of the present application provide a magnetic storage structure and a magnetic storage module, which are applied to the field of magnetic electronic devices. A current parallel or antiparallel to the magnetization direction of the magnetic tunnel junction is passed under the magnetic tunnel junction to deflect the magnetic direction of the magnetic tunnel junction. By withdrawing the current, the magnetization direction of the magnetic tunnel junction can be randomly flipped to the same or opposite direction as the original magnetization direction, and the random probability is close to 50%. Data is then stored through the magnetic tunnel junction to realize PUF-based data storage.

Description

Magnetic storage structure and magnetic storage module

Technical Field

The embodiment of the application relates to the field of magnetic electronic devices. And more particularly to a magnetic memory structure and a magnetic memory module.

Background

Physical entity encryption is an important research topic for guaranteeing equipment information security. In the related art, physical entity encryption is generally based on a physical unclonable function (Physical Unclonable Function, PUF), converting process variations and physical randomness into random codes for key generation and authentication.

The random code calculated based on the time delay characteristic of the silicon-based transistor is easy to crack, the safety of the random code is generally improved by adopting the equipment randomness of a nonvolatile memory (such as a Magnetic Random Access Memory (MRAM)), but the equipment randomness causes that a storage part for realizing the random code can not store information, and the storable space of the memory is reduced. Accordingly, there is a need to provide a storage structure that performs encryption and storage simultaneously.

Disclosure of Invention

The embodiment of the application provides a magnetic storage structure and a magnetic storage module, which aim to solve the technical problems.

In a first aspect, an embodiment of the present application provides a magnetic storage structure, including:

A magnetic tunnel junction, a bottom electrode layer disposed below the magnetic tunnel junction;

The bottom electrode layer is connected with PUF current parallel or antiparallel to the magnetization direction of the magnetic tunnel junction, and the magnetization direction of the magnetic tunnel junction is randomly turned over;

the magnetic tunnel junction stores data.

In the technical scheme, current parallel or antiparallel to the magnetization direction of the magnetic tunnel junction is introduced below the magnetic tunnel junction so as to deflect the magnetic direction of the magnetic tunnel junction, the magnetization direction of the magnetic tunnel junction can be randomly turned to be the same or opposite to the original magnetization direction through the operation of withdrawing the current, the random probability is close to 50%, and data is stored through the magnetic tunnel junction, so that data storage based on the PUF is realized.

Optionally, the aspect ratio of the magnetic tunnel junction is greater than a preset threshold;

The magnetization direction of the magnetic tunnel junction is the long axis direction.

Optionally, the magnetic tunnel junction comprises a free layer;

the magnetic storage structure further includes:

an antiferromagnetic layer disposed between the free layer and the bottom electrode layer;

the antiferromagnetic layer and the free layer form an exchange bias;

The magnetic tunnel junction has an arbitrary aspect ratio.

In the technical scheme, the antiferromagnetic layer is arranged between the free layer and the bottom electric layer and can form exchange bias with the free layer, so that the magnetic moment arrangement of the free layer can be enhanced, the diamagnetism of the free layer is enhanced, the antiferromagnetic layer is not influenced by an external magnetic field, and the antiferromagnetic magnetic sequence of the antiferromagnetic layer is not influenced by the shape, so that the magnetic tunnel junction has any length-width ratio, the length-width ratio of the magnetic tunnel junction can be adjusted according to the production requirement of the magnetic storage structure, and the production flexibility of the magnetic storage structure based on the PUF is enhanced.

Optionally, the bottom electrode layer is fed with the PUF current to demagnetize the counter magnet layer, and the PUF current is a thermal current.

Optionally, the bottom electrode layer includes a first bottom electrode structure and a second bottom electrode structure, the first bottom electrode structure and the second bottom electrode structure being arranged crosswise;

the magnetic tunnel junctions are located in overlapping regions of intersection;

The first bottom electrode structure is connected with the PUF current, the second bottom electrode structure is connected with the write current, and the write current direction is perpendicular to the PUF current direction so as to store data.

Optionally, the magnetic storage structure further comprises a top electrode layer electrically connected over the magnetic tunnel junction;

Write current is controlled from a direction perpendicular to the PUF current through the top electrode layer to store data.

Optionally, the magnetic storage structure further comprises a top electrode layer electrically connected over the magnetic tunnel junction;

A direction of a write current from the top electrode layer to the bottom electrode layer is controlled through the magnetic tunnel junction to store data.

In a second aspect, an embodiment of the present application provides a magnetic memory module, including: a plurality of array-distributed magnetic memory cells; the magnetic memory unit comprises a magnetic memory structure and a PUF write circuit; the magnetic storage structure includes: a magnetic tunnel junction, a bottom electrode layer disposed below the magnetic tunnel junction;

The bottom electrode layer is connected with PUF current parallel or antiparallel to the magnetization direction of the magnetic tunnel junction, and the magnetization direction of the magnetic tunnel junction is randomly turned over;

the magnetic tunnel junction stores data;

The PUF write circuit includes a first write transistor and a second write transistor;

one end of the bottom electrode layer of the magnetic storage structure is electrically connected with the first writing transistor, and the other end of the bottom electrode layer of the magnetic storage structure is electrically connected with the second writing transistor;

The control ends of the first writing transistor and the second writing transistor are connected to a first word line;

And enabling a PUF current to flow through the bottom electrode layer by controlling the conduction of the first writing transistor and the second writing transistor, wherein the direction of the PUF current is parallel or antiparallel to the magnetization direction of the magnetic storage structure so as to randomly flip the magnetization direction of the magnetic tunnel junction.

Optionally, in the magnetic storage structure, the bottom electrode layer includes a first bottom electrode structure and a second bottom electrode structure, and the first bottom electrode structure and the second bottom electrode structure are arranged in a crossing manner;

One end of the first bottom electrode structure is electrically connected with the first writing transistor, and the other end of the first bottom electrode structure is electrically connected with the second writing transistor;

the magnetic tunnel junctions are located in overlapping regions of intersection;

The magnetic memory cell further includes a memory circuit;

The memory circuit includes a first memory transistor and a second memory transistor;

One end of the second bottom electrode structure is electrically connected with the first storage transistor, and the other end of the second bottom electrode structure is electrically connected with the second storage transistor;

A write current is caused to flow through the second bottom electrode structure by controlling the conduction of the first and second storage transistors, the write current being in a direction perpendicular to the PUF current direction, to store data in the magnetic tunnel junction.

Optionally, the magnetic storage structure includes a top electrode layer electrically connected over the magnetic tunnel junction;

The magnetic memory cell further includes a memory circuit;

The memory circuit includes a first memory transistor and a second memory transistor;

one end of the top electrode layer is electrically connected with the first storage transistor, and the other end of the top electrode layer is electrically connected with the second storage transistor;

A write current is caused to flow through the top electrode layer by controlling the conduction of the first and second storage transistors, the write current being in a direction perpendicular to the PUF current direction, to store data in the magnetic tunnel junction.

Optionally, the magnetic memory cell further comprises a first read transistor, a first transistor, and a second transistor;

One end of the first reading transistor is electrically connected to the top of the top electrode layer electrically connected above the magnetic tunnel junction, and the control end is electrically connected to a reading word line;

the first transistor is electrically connected to the read word line and the first word line between the first write transistor and the second write transistor, the second transistor being disposed on the first word line between the first write transistor and the second write transistor;

When reading, the first transistor is turned on, and the second transistor is turned off.

In a third aspect, an embodiment of the present application provides a magnetic memory module, including: a plurality of array-distributed magnetic memory cells; the magnetic memory unit comprises a magnetic memory structure and a PUF write circuit; the magnetic storage structure includes: a magnetic tunnel junction, a bottom electrode layer disposed below the magnetic tunnel junction;

The bottom electrode layer is connected with PUF current parallel or antiparallel to the magnetization direction of the magnetic tunnel junction, and the magnetization direction of the magnetic tunnel junction is randomly turned over;

the magnetic tunnel junction stores data;

The magnetic memory structure further includes a top electrode layer disposed over the reference layer;

the PUF write circuit includes a first write transistor;

One end of a bottom electrode layer of the magnetic storage structure is electrically connected with the first writing transistor, and the other end of the bottom electrode layer of the magnetic storage structure is electrically connected with a source line;

And enabling a PUF current to flow through the bottom electrode layer by controlling the conduction of the first writing transistor and the source line, wherein the direction of the PUF current is parallel or antiparallel to the magnetization direction of the magnetic storage structure so as to randomly flip the magnetization direction of the magnetic tunnel junction.

Optionally, the magnetic memory unit further comprises a memory circuit;

The memory circuit includes a first memory transistor;

one end of the first memory transistor is electrically connected to the top electrode layer of the magnetic memory structure;

The write current is directed from the top electrode layer to the bottom electrode layer through the magnetic tunnel junction by controlling conduction of the first storage transistor and the source line to store data.

In the magnetic storage structure and the magnetic storage module provided by the embodiment of the application, current parallel or antiparallel to the magnetization direction of the magnetic tunnel junction is introduced below the magnetic tunnel junction so as to deflect the magnetic direction of the magnetic tunnel junction, the magnetization direction of the magnetic tunnel junction can be randomly turned to be the same as or opposite to the original magnetization direction through the operation of withdrawing the current, the random probability is close to 50%, and then data is stored through the magnetic tunnel junction, so that the data storage based on the PUF is realized.

Drawings

For a clearer description of an embodiment of the present application or an implementation in the related art, the drawings that are required to be used in the embodiment or the related art description will be briefly introduced, and it is apparent that the drawings in the following description are some embodiments of the present application, and other drawings may be obtained according to the drawings for those of ordinary skill in the art.

FIG. 1A is a schematic diagram of a magnetic storage structure provided in accordance with some embodiments;

FIG. 1B is a schematic diagram of another magnetic storage structure provided in accordance with other embodiments;

FIG. 1C is a schematic cross-sectional view of a magnetic storage structure provided in accordance with some embodiments;

FIG. 2A is a schematic diagram of a magnetic memory structure including an antiferromagnetic layer provided in accordance with other embodiments;

FIG. 2B is a schematic diagram of another magnetic memory structure including an antiferromagnetic layer provided in accordance with other embodiments;

FIG. 2C is a schematic cross-sectional view of a magnetic memory structure including an antiferromagnetic layer provided in accordance with some embodiments;

FIG. 3A is a power-up schematic view of a magnetic memory structure with a top electrode layer writing data provided in accordance with some embodiments;

FIG. 3B is a schematic diagram of the write current versus the PUF current in a magnetic memory structure provided in accordance with other embodiments;

FIG. 4A is a schematic diagram of a circuit configuration of a magnetic memory cell with a top electrode layer for writing data according to some embodiments;

FIG. 4B is a schematic circuit diagram of a magnetic memory module with a top electrode layer for writing data according to some embodiments;

FIG. 5A is a power-up schematic view of a magnetic memory structure with a bottom electrode layer for writing data, provided in accordance with further embodiments;

FIG. 5B is a schematic diagram of the directional relationship of write current and PUF current in another magnetic memory structure provided in accordance with other embodiments;

FIG. 6A is a schematic diagram of a circuit configuration of a magnetic memory cell with a bottom electrode layer for writing data according to further embodiments;

FIG. 6B is a schematic diagram of a circuit configuration of a magnetic memory module with a bottom electrode layer for writing data according to further embodiments;

FIG. 7 is a power-on schematic diagram of a magnetic memory structure based on spin transfer torque writing provided in accordance with further embodiments;

FIG. 8A is a schematic diagram of a circuit configuration of a magnetic memory cell based on spin transfer torque writing according to further embodiments;

FIG. 8B is a schematic circuit diagram of a magnetic memory module based on spin transfer torque writing according to further embodiments.

Specific embodiments of the present application have been shown by way of example in the drawings and will be described in more detail below. These drawings and the written description are not intended to limit the scope of the inventive concept in any way, but to illustrate the inventive concept to those skilled in the art by reference to specific embodiments.

Detailed Description

For the purposes of making the objects, embodiments and advantages of the present application more apparent, the exemplary embodiments of the present application will be described clearly and fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments of the present application are shown, it being apparent that the exemplary embodiments are illustrated only by way of example, and not by way of example, in all embodiments of the application.

It is to be noted that the brief description of the terminology in the present application is for the purpose of facilitating understanding of the embodiments described below only and is not intended to limit the embodiments of the present application. Unless otherwise indicated, these terms should be construed in their ordinary and customary meaning.

Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a product or apparatus that comprises a list of elements is not necessarily limited to those elements expressly listed but may include other elements not expressly listed or inherent to such product or apparatus.

Physical entity encryption is an important research topic for guaranteeing equipment information security. In the related art, physical entity encryption is generally based on a physical unclonable function PUF, and converts process variation and physical randomness into random codes for key generation and identity verification.

The random code calculated based on the delay characteristic of the silicon-based transistor is easy to crack due to the internal linear characteristic of the silicon-based transistor, the safety of the random code is generally improved by adopting the randomness of the device of a nonvolatile memory (such as a Magnetic Random Access Memory (MRAM)), but the randomness of the device causes that a storage part for realizing the random code can not store information, the storable space of the memory is reduced, and the size of a memory chip is generally required to be increased to realize the target storage space, so that the cost is increased. Accordingly, there is a need to provide a storage structure that performs encryption and storage simultaneously.

In order to solve the technical problems, the application provides a magnetic storage structure and a magnetic storage module. The technical conception of the application is as follows: and a current parallel or antiparallel to the magnetization direction of the magnetic tunnel junction is introduced below the magnetic tunnel junction so as to deflect the magnetic direction of the magnetic tunnel junction, the magnetization direction of the magnetic tunnel junction can be randomly turned to be the same as or opposite to the original magnetization direction through the operation of withdrawing the current, and then data is stored through the magnetic tunnel junction, so that the data storage based on the PUF is realized.

The magnetic memory structure provided by the present application is explained below.

FIG. 1A is a schematic diagram of a magnetic memory structure provided in accordance with some embodiments, including a magnetic tunnel junction 11, a bottom electrode layer 15 disposed below the magnetic tunnel junction 11, as shown in FIG. 1A. The bottom electrode layer 15 is supplied with PUF current parallel or antiparallel to the magnetization direction of the magnetic tunnel junction 11, and randomly inverts the magnetization direction of the magnetic tunnel junction 11;

In some embodiments, the magnetic tunnel junction 11 includes, from top to bottom, a reference layer 111, a barrier layer 112, a free layer 113, which are stacked, as shown in FIG. 1A;

In other embodiments, the magnetic tunnel junction 11 includes a pinned layer 13, a reference layer 111, a barrier layer 112, and a free layer 113 stacked from top to bottom, as shown in FIG. 1B.

Referring to the structure shown in fig. 1A, when the magnetization directions of the reference layer 111 and the free layer 113 are x-axis directions, i.e., directions from left to right, the magnetization direction of the free layer 113 can be inverted by writing a PUF current between the two ends a and B of the bottom electrode layer 15. In fig. 1A and 1B, the directions of the arrows in the reference layer 111 and the free layer 113 indicate the magnetization directions, and the directions of the arrows in the bottom electrode layer 15 indicate the directions of PUF currents.

When the direction of the PUF current is the same as the magnetization direction, the free layer 113 is rotated in the Y-axis direction due to the oersted field generated by the PUF current or spin polarization caused by spin-orbit torque (SOT) effect; when the PUF electrode current is removed, the above-mentioned oersted field or SOT effect is removed, and the magnetization direction of the free layer 113 will be reversed to its own magnetization direction or opposite direction, i.e. randomly reversed to the x-axis direction, or-x-axis direction.

In some embodiments, a magnetic field may be placed around the magnetic tunnel junction 11 to change the magnetization direction of the free layer 113 of the magnetic tunnel junction 11, changing the resistance, enabling data to be stored at the magnetic tunnel junction 11.

The magnetic tunnel junction 11, with the magnetization direction in-plane (x or y direction), has a disadvantage in information calculation or storage: the coercive field is small and easily changed by the external magnetic field environment, affecting the computing or memory functions. Therefore, in order to maintain the magnetic moment direction, the magnetic tunnel junction 11 needs to be prepared in a shape of a certain aspect ratio. The magnetic tunnel junction 11 is required to be prepared as a structure having an aspect ratio greater than a preset threshold, and the long axis direction of the magnetic tunnel junction 11 is the magnetization direction thereof. The preset threshold is a ratio set according to actual production design requirements, the ratio being a ratio of a length of the magnetic tunnel junction 11 in a long axis direction to a length in a non-long axis direction, the preset threshold being > 1.

As shown in fig. 1C, the magnetization direction of the magnetic tunnel junction 11 is x-axis direction, and the PUF current direction is also x-axis direction, with reference to the coordinate axes applied in fig. 1A and 1B. The long axis direction of the magnetic tunnel junction 11 is the x axis direction, and thus the ratio of the length of the magnetic tunnel junction 11 in the x axis direction to the length in the y axis direction is greater than a preset threshold.

In some embodiments, the shape of the magnetic tunnel junction 11 is elliptical or rectangular, which may also include rounded rectangles.

The above structure has a longer occupation size of each magnetic tunnel junction 11 in the magnetization direction, and a memory chip constructed based thereon has a large occupation area and a certain size ratio limitation.

In some embodiments, the present application further proposes a magnetic storage structure as shown in FIGS. 2A and 2B.

Referring to the structure shown in fig. 2A, the magnetic memory structure further includes an antiferromagnetic layer 14 disposed between the free layer 113 and the bottom electrode layer 15, the antiferromagnetic layer 14 and the free layer 113 forming an exchange bias to strengthen the magnetic moment alignment of the free layer 113 and enhance the coercive field thereof, thereby enhancing the diamagnetism of the free layer 113, as compared to the structure shown in fig. 1A.

The structure shown in fig. 2B is similar, with an antiferromagnetic layer 14 added between the free layer 113 and the bottom electrode layer 15, relative to the structure shown in fig. 1B.

Since the antiferromagnetic order of the antiferromagnetic layer 14 is not affected by the shape, the magnetic tunnel junction 11 has an arbitrary aspect ratio.

In order to simplify the production process, the device can be directly manufactured in a circular or square shape, as shown in the cross-sectional schematic diagram of fig. 2C, where the magnetic tunnel junction 11 has a constant dimension in the y-axis direction, the dimension in the x-axis is reduced, but still the PUF function as proposed above can be achieved.

In fig. 2A and 2B, the directions of the arrows in the reference layer 111, the free layer 113, and the antiferromagnetic layer 14 indicate magnetization directions, and the directions of the arrows in the bottom electrode layer 15 indicate the directions of PUF currents.

With the structure shown in fig. 2A or 2B, the bottom electrode layer 15 is supplied with a thermal current before the PUF current is supplied thereto, and heats the antiferromagnetic layer 14, demagnetizes the antiferromagnetic layer 14, and reduces the exchange bias. PUF current is sequentially introduced and withdrawn from the bottom electrode layer 15 along the magnetization direction, and the free layer 113 is turned over by the oersted field or the SOT effect generated by the current, so that the magnetization direction of the free layer 113 can be randomly turned over.

In some embodiments, the PUF current flowing through the bottom electrode layer 15 is a thermal current, and then the bottom electrode layer may heat the antiferromagnetic layer 14 to demagnetize the antiferromagnetic layer 14, and then the free layer 113 is flipped based on the PUF current. The present embodiment can reduce the amount of current passing through the bottom electrode layer 15 and simplify the control logic.

In some embodiments, the material of antiferromagnetic layer 14 is one of a collinear antiferromagnetic material and a non-collinear antiferromagnetic material, including IrMn, ptMn, irMn ₃、Mn₃ Sn.

In some embodiments, bottom electrode layer 15 comprises at least one of a conductive layer with strong spin-orbit coupling effect, a heavy metal material with negative spin hall angle, or a topological insulator;

The conductive layer with strong spin-orbit coupling effect comprises one or more combinations of Pt, pd, hf, au, auPt, ptHf, ptCr, ptMn, feMn, niMn;

The heavy metal material with the negative spin hall angle comprises one or more of Ta, W, hf, ir, irMn, W, WO _x, WN, W (O, N), taN and TaB;

The topological insulator comprises one or more combinations of Bi _xSe_1-x,Bi_xSb_1-x,(Bi,Sb)₂Te₃.

The data storage method and the related circuit structure of the magnetic storage structure are explained below.

Referring to the circuit structure shown in fig. 3A and 3B, the magnetic memory structure further includes a top electrode layer 12 electrically connected over the magnetic tunnel junction 11.

Write current can be controlled from a direction not parallel to the PUF current through the top electrode layer 12 to store data. One directional relationship between the write current and the PUF current can be referred to as a schematic diagram shown in fig. 3B, where the arrow direction from the D-end to the E-end of the top electrode layer 12 is the direction of the write current, and the arrow direction from the a-end to the B-end of the bottom electrode layer 15 is the direction of the PUF current.

The write current direction may be the direction from the E-terminal to the D-terminal of the top electrode layer 12, and the PUF current direction may be the direction from the B-terminal to the A-terminal of the bottom electrode layer 15.

The write current through the top electrode layer 12 includes a vertical current component perpendicular to the PUF current direction, which can adjust the magnetization direction of the free layer 113 based on the SOT effect or the oersted field constructed by the write current, realizing deterministic inversion to store data;

Preferably, the write current and the PUF current are oriented perpendicular to each other.

When the write current direction is the y-axis direction, the magnetic field direction generated by the current is the x-axis direction, thereby adjusting the magnetization direction of the free layer 113; when the write current direction is the-y-axis direction, the magnetic field direction generated by the current is the-x-axis direction, thereby adjusting the magnetization direction of the free layer 113. Wherein, the magnitude of the magnetic field can be adjusted by adjusting the magnitude of the current value of the write current, thereby adjusting the probability of turning over the magnetization direction. The arrow direction in the magnetic tunnel junction 11 shown in fig. 3A is a magnetization direction, the arrow direction in the bottom electrode layer 15 is a PUF current direction, "·" and "x" in the bottom electrode layer 12 indicate possible directions of write current, and at each moment of writing current, the write current has only one direction.

When the magnetization directions of the free layer 113 and the reference layer 111 are identical, called a parallel state (P-state), the magnetic tunnel junction 11 assumes a low resistance state; when the magnetization directions of the free layer 113 and the reference layer 111 are not uniform, referred to as an antiparallel state (AP state), the magnetic tunnel junction 11 exhibits a high resistance state. The magnetization direction can be determined by reading the resistance value of the magnetic tunnel junction 11, thereby determining the data stored in the magnetic tunnel junction 11.

Based on the structure shown in fig. 3A, the present application provides a magnetic memory module including: a plurality of array-distributed magnetic memory cells; the magnetic memory cell includes a magnetic memory structure and PUF write circuit as shown in fig. 3A, and when the antiferromagnetic layer 14 is included in the magnetic memory structure, the circuit structure of the magnetic memory cell is as shown in fig. 4A. Wherein the arrow in the magnetic memory structure indicates the magnetization direction.

The PUF write circuit comprises a first write transistor T1 and a second write transistor T2;

One end of the bottom electrode layer 15 of the magnetic memory structure is electrically connected to the first writing transistor T1, and the other end is electrically connected to the second writing transistor T2;

the control terminals of the first writing transistor T1 and the second writing transistor T2 are connected to the first word line WPWL;

by controlling the conduction of the first write transistor T1 and the second write transistor T2, a PUF current is caused to flow through the bottom electrode layer 15, the PUF current direction being parallel or antiparallel to the magnetization direction of the magnetic storage structure, to randomly flip the magnetization direction of the magnetic tunnel junction 11.

More specifically, the bottom electrode layer 15 of the magnetic memory structure is provided with an a end and a B end, the first end of the first writing transistor T1 is electrically connected to the first bit line PBL provided on the magnetic memory module, the second end is electrically connected to the a end of the bottom electrode layer 15, the control end is electrically connected to the first word line WPWL provided on the magnetic memory module, the first writing transistor T1 obtains a first control signal from its control end, obtains a first electrical signal from its first end, controls its conduction by the first control signal, and outputs the first electrical signal from the second end. The transistor shown in fig. 4A is an N-type transistor, and the first control signal obtained at the control terminal thereof is turned on when it is a high-level electrical signal, and turned off when it is a low-level electrical signal; when the transistor is a P-type transistor, the first control signal obtained by the control end of the transistor is turned on when the first control signal is a low-level electric signal, and turned off when the first control signal is a high-level electric signal. The following explanation will be made with N-type transistors, and examples of P-type transistors will not be explained in detail.

The first end of the second write transistor T2 is electrically connected to the B end of the bottom electrode layer 15, the second end is electrically connected to the source line SL provided on the magnetic memory module, the control end is electrically connected to the first word line WPWL, the second write transistor T2 obtains a first control signal from its control end, obtains a second electrical signal from its second end, is controlled to be turned on by the first control signal, and outputs a second electrical signal from its first end;

The bottom electrode layer 15 writes a PUF current based on the first electrical signal and the second electrical signal to randomly adjust the magnetization direction of the magnetic tunnel junction 11. When the voltage value of the first electric signal is larger than that of the second electric signal, the PUF current direction is the x-axis direction; when the voltage value of the first electric signal is smaller than that of the second electric signal, the PUF current direction is the-x axis direction.

In some embodiments, the magnetic memory cell further comprises a memory circuit; the memory circuit includes a first memory transistor T3 and a second memory transistor T4.

One end of the top electrode layer 12 is electrically connected to the first memory transistor T3, and the other end is electrically connected to the second memory transistor T4;

By controlling the conduction of the first memory transistor T3 and the second memory transistor T4 such that a write current flows through the top electrode layer 12, the direction of the write current crosses the direction of the PUF current to store data in the magnetic tunnel junction 11.

Preferably, the direction of the write current flowing through the top electrode layer 12 is perpendicular to the direction of the PUF current.

More specifically, the top electrode layer 12 of the magnetic memory structure is provided with a D terminal and an E terminal, the first terminal of the first memory transistor T3 is electrically connected to the third bit line MBL provided on the magnetic memory module, the second terminal is electrically connected to the D terminal of the top electrode layer 12, the control terminal is electrically connected to the second word line WMWL provided on the magnetic memory module, the first memory transistor T3 obtains the second control signal from its control terminal, obtains the third electrical signal from its first terminal, is controlled to be turned on by the second control signal, and outputs the third electrical signal from its second terminal;

The first terminal of the second memory transistor T4 is electrically connected to the E terminal of the top electrode layer 12, the second terminal is electrically connected to the source line SL, the control terminal is electrically connected to the second word line WMWL, the second memory transistor T4 obtains a second control signal from its control terminal, obtains a fourth electrical signal from its second terminal, is controlled to be turned on by the second control signal, and outputs the fourth electrical signal from its first terminal;

The top electrode layer 12 passes a write current based on the third electrical signal and the fourth electrical signal to store data in the magnetic tunnel junction 11. When the voltage value of the third electric signal is larger than that of the fourth electric signal, the writing current direction is the-y axis direction; when the voltage value of the third electric signal is smaller than that of the fourth electric signal, the writing current direction is the y-axis direction.

In some embodiments, the magnetic memory cell further comprises a read circuit;

The read circuit includes a first read transistor T5, one end of the first read transistor T5 is electrically connected to the top of the top electrode layer 12, and the control end is electrically connected to the read word line RWL.

One write transistor connected to the bottom electrode layer 15 is provided to be turned on simultaneously with the first read transistor T5 so that a read current passes through the magnetic tunnel junction 11 in a direction from the top electrode layer 12 to the bottom electrode layer 15 to read data.

More specifically, a first terminal of the first read transistor T5 is electrically connected to the first bit line PBL, a control terminal is electrically connected to the read word line RWL provided on the magnetic memory module, a second terminal is electrically connected to the point C of the top electrode layer 12 of the magnetic memory structure, the first read transistor T5 obtains a fifth electric signal from its first terminal, obtains a third control signal from its control terminal, and outputs the fifth electric signal controlled by the third control signal;

The control terminal of the first read transistor T5 is electrically connected to the control terminal of the second read transistor, which is a transistor electrically connected to the bottom electrode layer 15. The second read transistor is configured to obtain a third control signal from its control terminal, to be controlled to be turned on by the third control signal, and to output a read electrical signal obtained from its first terminal from its second terminal to determine the resistance state of the magnetic tunnel junction 11;

The read electrical signal is a current signal output after the fifth electrical signal passes through the magnetic tunnel junction 11 in the direction from the top electrode layer 12 to the bottom electrode layer 15.

To achieve the functional multiplexing, the second write transistor T2 may be used as a second read transistor that is turned on simultaneously with the first read transistor T5, as shown in the circuit configuration shown in fig. 4A. In another embodiment, the second read transistor may also be the first write transistor T1.

In order to prevent the phenomenon of read-write path crosstalk in the above-described circuit configuration, the magnetic memory cell further includes a first transistor D1 and a second transistor D2;

the first transistor D1 is electrically connected to the read word line RWL and the first word line WPWL between the first write transistor T1 and the second write transistor T2, and the second transistor D2 is disposed on the first word line WPWL between the first write transistor T1 and the second write transistor T2;

during writing, the second transistor D2 is turned on, and the first transistor D1 is turned off; during reading, the second transistor D2 is turned off, and the first transistor D1 is turned on.

In some embodiments, the first transistor D1 and the second transistor D2 are diodes, and one terminal of the same type of the first transistor D1 and the second transistor D2 is electrically connected. The same type of terminal is connected in such a way that it is related to the transmission flow direction of the control signal, and when the cathodes of the first transistor D1 and the second transistor D2 are connected together, the direction of the transmission signal on the first word line WPWL is from left to right, and the read word line RWL transmits the control signal to the first word line WPWL; when the anodes of the first and second transistors D1 and D2 are connected together, the direction of the transfer signal on the first word line WPWL is from right to left, and the first word line WPWL transfers the control signal to the read word line RWL.

The first transistor D1 and the second transistor D2 are diodes, which are only examples, and other controllable transistors, such as transistors, field effect transistors, etc., may be applied in the present application, and are not limited herein.

Further, the position where the first word line WPWL is connected in series with the second transistor D2 is related to the selection of a transistor for receiving a read signal, the second transistor D2 is connected between the write transistor for avoiding signal crosstalk and the read word line RWL, and when the read current is transmitted by using the first write transistor T1, the second transistor D2 is connected in series on the side close to the second write transistor T2.

The array of magnetic memory structures is distributed and connected with a plurality of word lines arranged transversely and a plurality of bit lines arranged longitudinally to form the magnetic memory module shown in fig. 4B. In the circuit structure shown in fig. 4B, n rows and n columns of magnetic memory cells are disposed on the magnetic memory module, n first bit lines PBL1 to PBLn, third bit lines MBL1 to MBLn, source lines SL1 to SLn, read word lines RWL1 to RWLn, first word lines WPWL1 to WPWLn, and second word lines WMWL1 to WMWLn are disposed correspondingly, and corresponding electrical signals are transmitted to the corresponding magnetic memory cells, respectively.

The magnetic memory cell reads the current, transmits the current to the read-write drive, passes through the sense amplifier SA, enters the PUF encryption module, and generates a PUF response, thereby outputting PUF data, wherein the line connected to the read-write drive is a line connected to a transistor outputting the read current, and in this embodiment, is the first bit line PBL or the source line SL.

In other embodiments, the magnetic memory structure may be as shown with reference to fig. 5A and 5B, the bottom electrode layer 15 comprising a first bottom electrode structure and a second bottom electrode structure, the first bottom electrode structure and the second bottom electrode structure being arranged to intersect at an angle θ, which may be 0 ° < θ < 180 °.

The first bottom electrode structure and the second bottom electrode structure can form a crossed integral structure or can be separate polar plates, and the first bottom electrode structure and the second bottom electrode structure are arranged in a crossed way; the magnetic tunnel junction 11 is located in the overlapping region of the intersection. The bottom electrode layer 15 may be a common metal or a material with a strong SOT effect.

The first bottom electrode structure may be supplied with PUF current from the a-terminal to the B-terminal, and the second bottom electrode structure may be supplied with write current from the D-terminal to the E-terminal, to store data. The first bottom electrode structure can also be supplied with PUF current from the B-terminal to the a-terminal, and the second bottom electrode structure can also be supplied with write current from the E-terminal to the D-terminal. In which the arrow direction in the magnetic tunnel junction 11 shown in fig. 5A indicates the magnetization direction, and the arrow direction under the bottom electrode layer 15 indicates the PUF current direction.

When the crossing angle theta of the first bottom electrode structure and the second bottom electrode structure is 90 degrees, the first bottom electrode structure and the second bottom electrode structure are perpendicular to each other, and a crisscross Crossbar structure can be constructed. The direction of the PUF current flowing in the first bottom electrode structure is perpendicular to the direction of the write current flowing in the second bottom electrode structure, the direction of the PUF current is parallel or antiparallel to the magnetization direction of the magnetic tunnel junction 11, and the direction of the write current is perpendicular to the magnetization direction of the magnetic tunnel junction 11. The write current may adjust the magnetization direction of the free layer 113 based on the SOT effect or the oersted field constructed by the write current to store data.

Referring to fig. 5B, in the bottom electrode layer 15, the arrow direction in the a-to-B-ends of the first bottom electrode structure is the PUF current direction, the arrow direction in the E-to-D-ends of the second bottom electrode structure is the write current direction, and the arrow direction in the circle in the middle overlap region indicates the magnetization direction of the free layer 113.

When the crossing angle θ of the first bottom electrode structure and the second bottom electrode structure is not 90 °, the first bottom electrode structure and the second bottom electrode structure are not perpendicular to each other, the PUF current direction of the first bottom electrode structure and the write current direction of the second bottom electrode structure are not perpendicular to each other, the PUF current direction is parallel or antiparallel to the magnetization direction of the magnetic tunnel junction 11, the write current direction and the magnetization direction of the magnetic tunnel junction 11 are not perpendicular, the write current includes a perpendicular current component perpendicular to the PUF current, and the perpendicular current component can adjust the magnetization direction of the free layer 113 to realize deterministic inversion, so as to store data.

This structure allows a memory current to flow through the bottom electrode layer 15, and the manufacturing process of the magnetic memory structure is simpler than in the previous embodiment.

The magnetic memory module provided by the present application will be explained below by taking the PUF current flowing from the a-terminal to the B-terminal of the first bottom electrode structure as an example.

Based on the structure shown in fig. 5A, the present application provides a magnetic memory module including: a plurality of array-distributed magnetic memory cells; the magnetic memory cell includes a magnetic memory structure and PUF write circuit as shown in fig. 5A, and when the antiferromagnetic layer 14 is included in the magnetic memory structure, the circuit structure of the magnetic memory cell is as shown in fig. 6A, wherein the arrow in the magnetic memory structure indicates the magnetization direction.

The PUF write circuit is electrically connected to the first bottom electrode structure, where the circuit structure of the PUF write circuit, the electrical connection relationship between the PUF write circuit and the first word line WPWL, the first bit line PBL, and the source line SL, and the driving manner of the PUF write circuit are the same as those of the embodiment corresponding to fig. 4A, and the electrical connection manner between the PUF write circuit and the first bottom electrode structure is the same as that between the PUF write circuit and the bottom electrode layer 15 in the embodiment corresponding to fig. 4A, which is not described herein.

In some embodiments, the magnetic memory cell further comprises a memory circuit; the memory circuit includes a first memory transistor T3 and a second memory transistor T4;

one end of the second bottom electrode structure is electrically connected to the first storage transistor T3, and the other end of the second bottom electrode structure is electrically connected to the second storage transistor T4; by controlling the conduction of the first memory transistor T3 and the second memory transistor T4 such that a write current flows through the second bottom electrode structure, the direction of the write current crosses the direction of the PUF current to store data in the magnetic tunnel junction 11.

Preferably, the direction of the write current is perpendicular to the direction of the PUF current.

More specifically, the first terminal of the first memory transistor T3 is electrically connected to the third bit line MBL provided on the magnetic memory module, the second terminal is electrically connected to the D terminal of the second bottom electrode structure, the control terminal is electrically connected to the second word line WMWL provided on the magnetic memory module, and is configured to obtain the second control signal from the control terminal thereof, obtain the third electrical signal from the first terminal thereof, control its turn-on by the second control signal, and output the third electrical signal from the second terminal thereof;

the first terminal of the second memory transistor T4 is electrically connected to the E terminal of the second bottom electrode structure, the second terminal is electrically connected to the source line SL, and the control terminal is electrically connected to the second word line WMWL, and is configured to obtain a second control signal from the control terminal thereof, obtain a fourth electrical signal from the second terminal thereof, control the conduction thereof by the second control signal, and output the fourth electrical signal from the first terminal thereof;

The second bottom electrode structure passes a write current based on the third electrical signal and the fourth electrical signal to store data in the magnetic tunnel junction 11. When the voltage value of the third electric signal is larger than that of the fourth electric signal, the writing current direction is the-y axis direction; when the voltage value of the third electric signal is smaller than that of the fourth electric signal, the writing current direction is the y-axis direction.

In some embodiments, the magnetic memory cell further comprises a read circuit; the circuit connection relationship of the first reading transistor T5 and the fifth transistor T5 is the same as that of the corresponding embodiment of fig. 4A, and will not be repeated here.

The first read transistor T5 may be turned on simultaneously with the second read transistor electrically connected to the bottom electrode layer 15 to allow a read current to pass through the magnetic tunnel junction 11 from the top electrode layer 12 to the bottom electrode layer 15 to read data. The second read transistor is any transistor electrically connected to the bottom electrode layer 15.

Taking the circuit structure shown in fig. 6A as an example, the first read transistor T5 and the second write transistor T2 are turned on simultaneously.

The first end of the first read transistor T5 is electrically connected with the first bit line PBL, the control end is electrically connected with the read word line RWL arranged on the magnetic memory module, the second end is electrically connected with the point C of the top electrode layer 12 of the magnetic memory structure, the first end is configured to obtain a fifth electric signal, the control end is configured to obtain a third control signal, and the third control signal is configured to control the third electric signal to output the fifth electric signal;

The control terminal of the first read transistor T5 is electrically connected to the control terminal of the second write transistor T2, the second write transistor T2 is configured to obtain a third control signal from the control terminal thereof, to be turned on by the third control signal, and to output a read electrical signal obtained from the first terminal thereof from the second terminal thereof to determine the resistance state of the magnetic tunnel junction 11;

The read electrical signal is a current signal output after the fifth electrical signal passes through the magnetic tunnel junction 11 along the direction from the top electrode layer 12 to the bottom electrode layer 15;

When the other transistors electrically connected to the bottom electrode layer 15 and the first read transistor T5 are turned on at the same time to transmit the read electrical signal, the control logic of the other transistors is the same as that of the second write transistor T2, and will not be described herein.

In order to prevent the phenomenon of read-write path crosstalk in the above-described circuit configuration, the magnetic memory cell further includes a first transistor D1 and a second transistor D2; a transistor that is turned on simultaneously with the first read transistor T5 to transmit a read electric signal is determined as a second read transistor, the first transistor D1 is electrically connected between the read word line RWL electrically connected to the first read transistor T5 and the target word line electrically connected to the control terminal of the second read transistor, and the second transistor D2 is electrically connected in series on the target word line between the second read transistor and the other transistors electrically connected to the target word line.

In the circuit structure shown in fig. 6A, the second read transistor is the second write transistor T2, the first transistor D1 is electrically connected between the read word line RWL electrically connected to the first read transistor T5 and the first word line WPWL located between the second write transistor T2 and the control terminal of the first write transistor T1, and the second transistor D2 is electrically connected in series to the first word line WPWL between the second write transistor T2 and the first write transistor T1 to prevent crosstalk.

Since the second write transistor T2 is a transistor for transmitting a read electric signal, the second transistor D2 is disposed on the first word line WPWL between the first write transistor T1 and the connection point of the first transistor D1 and the first word line WPWL.

One terminal of the same type of the first transistor D1 and the second transistor D2 is electrically connected.

When the read electric signal is transmitted by the first write transistor T1, the second transistor D2 is disposed on the first word line WPWL between the second write transistor T2 and the connection point of the first transistor D1 and the first word line WPWL.

When the first memory transistor T3 transmits a read electric signal, the first transistor D1 is electrically connected between the read word line RWL electrically connected to the first read transistor T5 and the second word line WMWL located between the control terminals of the first memory transistor T3 and the second memory transistor T4, and the second transistor D2 electrically connected in series on the second word line WMWL between the first memory transistor T3 and the second memory transistor T4 to prevent crosstalk; more specifically, the second transistor D2 is disposed on the second word line WMWL between the second memory transistor T4 and the connection point of the first transistor D1 and the second word line WMWL.

When the read electric signal is transmitted using the second memory transistor T4, the second transistor D2 is disposed on the second word line WMWL between the first memory transistor T3 and the connection point of the first transistor D1 and the second word line WMWL.

The types of the first transistor D1 and the second transistor D2 are not particularly limited, and may be diodes.

During writing, the second transistor D2 is turned on, and the second transistor D1 is turned off; during reading, the second transistor D2 is turned off, and the first transistor D1 is turned on.

The array of magnetic memory structures described above is distributed and connected to a plurality of word lines disposed laterally and a plurality of bit lines disposed longitudinally, forming a magnetic memory module as shown in fig. 6B. In the circuit structure shown in fig. 6B, n rows and n columns of magnetic memory cells are disposed on the magnetic memory module, n first bit lines PBL1 to PBLn, third bit lines MBL1 to MBLn, source lines SL1 to SLn, read word lines RWL1 to RWLn, first word lines WPWL1 to WPWLn, and second word lines WMWL1 to WMWLn are disposed correspondingly, and corresponding electrical signals are transmitted to the corresponding magnetic memory cells, respectively.

The magnetic memory cell reads the current, transmits the current to the read-write drive, passes through the sense amplifier SA, enters the PUF encryption module, and generates a PUF response, thereby outputting PUF data, wherein the line connected with the read-write drive is a line connected with a transistor outputting the read current, and in this embodiment, is the first bit line PBL, the third bit line MBL or the source line SL.

In some embodiments, the magnetic memory structure may refer to the structure shown in FIG. 7, further comprising a top electrode layer 12 electrically connected over the magnetic tunnel junction 11;

The direction of write current from the top electrode layer 12 to the bottom electrode layer 15 may be controlled through the magnetic tunnel junction 11 to store data. The direction of the write current is shown in fig. 7 as the direction of the arrow along the z-axis or along the-z-axis.

More specifically, based on a spin transfer Torque (SPIN TRANSFER Torque, STT) scheme, a deterministic inversion of the magnetic moment of the free layer 113 is achieved by a write current in a direction from the top electrode layer 12 to the bottom electrode, aided by a spin transfer Torque effect, to store data.

Based on the structure shown in fig. 7, the present application provides a magnetic memory module including: a plurality of array-distributed magnetic memory cells; the magnetic memory cell includes a magnetic memory structure and PUF write circuit shown in fig. 7; when the antiferromagnetic layer 14 is included in the magnetic memory structure, the circuit structure of the magnetic memory cell is shown in fig. 8A, in which an arrow in the magnetic memory structure indicates a magnetization direction.

The PUF write circuit includes a first write transistor T1;

In some embodiments, one end of the bottom electrode layer 15 of the magnetic memory structure is electrically connected to the first write transistor T1, and the other end is electrically connected to the source line SL;

by controlling the conduction of the first write transistor T1 and the source line SL, a PUF current is caused to flow through the bottom electrode layer 15, the PUF current direction being parallel or antiparallel to the magnetization direction of the magnetic storage structure, to randomly flip the magnetization direction of the magnetic tunnel junction 11.

More specifically, the bottom electrode layer 15 of the magnetic memory structure is provided with an a terminal and a B terminal, the first terminal of the first write transistor T1 is electrically connected to the bit line BL provided on the magnetic memory module, the second terminal is electrically connected to the a terminal of the bottom electrode layer 15, the control terminal is electrically connected to the word line WWL provided on the magnetic memory module, and is configured to obtain a first control signal from the control terminal thereof, obtain a first electrical signal from the first terminal thereof, control the conduction thereof by the first control signal, and output the first electrical signal;

The B terminal of the bottom electrode layer 15 is electrically connected to the source line SL, a second electrical signal is obtained from the source line SL, and the bottom electrode layer 15 writes a PUF current based on the first electrical signal and the second electrical signal to randomly adjust the magnetization direction of the magnetic tunnel junction 11. Referring to fig. 7, the direction of the arrow in the bottom electrode layer 15 is the direction of the PUF current and is the same as the direction of the arrow representing the magnetization direction in the magnetic tunnel junction 11, and in other embodiments the direction of the arrow in the bottom electrode layer 15 may be opposite to the direction of the arrow of the free layer 113 in the magnetic tunnel junction 11.

In other embodiments, the bit line BL is electrically connected to the a terminal of the bottom electrode layer 15, and the first writing transistor T1 is electrically connected between the B terminal of the bottom electrode layer 15 and the source line SL, and the driving manner is the same as that of the previous embodiment, which is not described herein.

The magnetic memory cell further includes a memory circuit; the memory circuit includes a first memory transistor T3;

One end of the first memory transistor T3 is electrically connected to the top electrode layer 12 of the magnetic memory structure, and write current is passed through the magnetic tunnel junction 11 in a direction from the top electrode layer 12 to the bottom electrode layer 15 by controlling conduction of the first memory transistor T3 and the source line SL to store data.

More specifically, the first end of the first memory transistor T3 is electrically connected to the bit line BL, the control end is electrically connected to the read word line RWL provided on the magnetic memory module, the second end is electrically connected to the point C of the top electrode layer 12 of the magnetic memory structure, and is configured to obtain a second control signal from the control end thereof, obtain a second electrical signal from the first end thereof, be turned on by the second control signal, and output the second electrical signal to the top electrode layer 12;

The magnetic memory structure is based on a second electric signal, and write current is introduced in a spin transfer torque manner from the top electrode layer 12 to the bottom electrode layer 15, and the magnetic moment deterministic inversion of the free layer 113 is realized by the spin transfer torque effect assistance to store data.

The first memory transistor T3 is further configured to obtain a third electrical signal from its first terminal, to be turned on by the second control signal, and to output a read electrical signal to the B terminal of the bottom electrode layer 15 to determine the resistance state of the magnetic tunnel junction 11.

The array of magnetic memory structures described above is distributed and connected to a plurality of word lines disposed laterally and a plurality of bit lines disposed longitudinally, forming a magnetic memory module as shown in fig. 8B. In the circuit structure shown in fig. 8B, n rows and n columns of magnetic memory cells are disposed on the magnetic memory module, and n bit lines BL1 to BLn, source lines SL1 to SLn, read word lines RWL1 to RWLn, and word lines WWL1 to WWLn are disposed to correspond to each other, so as to transmit corresponding electrical signals to the corresponding magnetic memory cells.

After the magnetic memory unit reads the current, the current is transmitted to a read-write drive through a source line SL, and enters a PUF encryption module after passing through a sense amplifier SA to generate a PUF response, so that PUF data is output.

Compared with the first two embodiments, the structure only needs 2 transistor driving, thereby greatly reducing the circuit area and the cost.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present application, and not for limiting the same; while the application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the application.

The foregoing description, for purposes of explanation, has been presented in conjunction with specific embodiments. However, the illustrative discussions above are not intended to be exhaustive or to limit the embodiments to the precise forms disclosed above. Many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles and the practical application, to thereby enable others skilled in the art to best utilize the embodiments and various embodiments with various modifications as are suited to the particular use contemplated.

Claims (13)

1. A magnetic memory structure comprising:

A magnetic tunnel junction, a bottom electrode layer disposed below the magnetic tunnel junction;

The bottom electrode layer is connected with PUF current parallel or antiparallel to the magnetization direction of the magnetic tunnel junction, and the magnetization direction of the magnetic tunnel junction is randomly turned over; the shape of the bottom electrode layer is set to be rectangular;

the magnetic tunnel junction stores data; the aspect ratio of the magnetic tunnel junction is greater than a preset threshold.

2. The magnetic storage structure of claim 1, wherein;

The magnetization direction of the magnetic tunnel junction is the long axis direction.

3. The magnetic storage structure of claim 1, wherein the magnetic tunnel junction comprises a free layer;

the magnetic storage structure further includes:

an antiferromagnetic layer disposed between the free layer and the bottom electrode layer;

the antiferromagnetic layer and the free layer form an exchange bias.

4. The magnetic memory structure of claim 3, wherein the bottom electrode layer is energized by the PUF current to demagnetize the antiferromagnetic layer, the PUF current being a thermal current.

5. The magnetic memory structure of any of claims 1 to 4, wherein the bottom electrode layer comprises a first bottom electrode structure and a second bottom electrode structure, the first bottom electrode structure and the second bottom electrode structure being arranged crosswise;

the magnetic tunnel junctions are located in overlapping regions of intersection;

The first bottom electrode structure is connected with the PUF current, the second bottom electrode structure is connected with the write current, and the write current direction is perpendicular to the PUF current direction so as to store data.

6. The magnetic memory structure of any of claims 1-4, further comprising a top electrode layer electrically connected over the magnetic tunnel junction;

Write current is controlled from a direction perpendicular to the PUF current through the top electrode layer to store data.

7. The magnetic memory structure of any of claims 1-4, further comprising a top electrode layer electrically connected over the magnetic tunnel junction;

A direction of a write current from the top electrode layer to the bottom electrode layer is controlled through the magnetic tunnel junction to store data.

8. A magnetic memory module, comprising: a plurality of array-distributed magnetic memory cells; the magnetic memory cell comprising a magnetic memory structure and PUF write circuit as in claim 1;

The PUF write circuit includes a first write transistor and a second write transistor;

one end of the bottom electrode layer of the magnetic storage structure is electrically connected with the first writing transistor, and the other end of the bottom electrode layer of the magnetic storage structure is electrically connected with the second writing transistor;

The control ends of the first writing transistor and the second writing transistor are connected to a first word line;

And enabling a PUF current to flow through the bottom electrode layer by controlling the conduction of the first writing transistor and the second writing transistor, wherein the direction of the PUF current is parallel or antiparallel to the magnetization direction of the magnetic storage structure so as to randomly flip the magnetization direction of the magnetic tunnel junction.

9. The magnetic memory module of claim 8, wherein in the magnetic memory structure, the bottom electrode layer comprises a first bottom electrode structure and a second bottom electrode structure, the first bottom electrode structure and the second bottom electrode structure being arranged crosswise;

One end of the first bottom electrode structure is electrically connected with the first writing transistor, and the other end of the first bottom electrode structure is electrically connected with the second writing transistor;

The magnetic tunnel junctions are located in overlapping regions of intersection; the magnetic memory cell further includes a memory circuit;

The memory circuit includes a first memory transistor and a second memory transistor;

One end of the second bottom electrode structure is electrically connected with the first storage transistor, and the other end of the second bottom electrode structure is electrically connected with the second storage transistor;

A write current is caused to flow through the second bottom electrode structure by controlling the conduction of the first and second storage transistors, the write current being in a direction perpendicular to the PUF current direction, to store data in the magnetic tunnel junction.

10. The magnetic memory module of claim 8, wherein the magnetic memory structure comprises a top electrode layer electrically connected over the magnetic tunnel junction;

The magnetic memory cell further includes a memory circuit;

The memory circuit includes a first memory transistor and a second memory transistor;

one end of the top electrode layer is electrically connected with the first storage transistor, and the other end of the top electrode layer is electrically connected with the second storage transistor;

A write current is caused to flow through the top electrode layer by controlling the conduction of the first and second storage transistors, the write current being in a direction perpendicular to the PUF current direction, to store data in the magnetic tunnel junction.

11. The magnetic memory module of claim 9 or 10, wherein the magnetic memory cell further comprises a first read transistor, a first transistor, and a second transistor;

One end of the first reading transistor is electrically connected to the top of the top electrode layer electrically connected above the magnetic tunnel junction, and the control end is electrically connected to a reading word line;

the first transistor is electrically connected to the read word line and the first word line between the first write transistor and the second write transistor, the second transistor being disposed on the first word line between the first write transistor and the second write transistor;

When reading, the first transistor is turned on, and the second transistor is turned off.

12. A magnetic memory module, comprising: a plurality of array-distributed magnetic memory cells; the magnetic memory cell comprising a magnetic memory structure and PUF write circuit as in claim 7;

the PUF write circuit includes a first write transistor;

One end of a bottom electrode layer of the magnetic storage structure is electrically connected with the first writing transistor, and the other end of the bottom electrode layer of the magnetic storage structure is electrically connected with a source line;

And enabling a PUF current to flow through the bottom electrode layer by controlling the conduction of the first writing transistor and the source line, wherein the direction of the PUF current is parallel or antiparallel to the magnetization direction of the magnetic storage structure so as to randomly flip the magnetization direction of the magnetic tunnel junction.

13. The magnetic memory module of claim 12, wherein the magnetic memory cell further comprises a memory circuit;

The memory circuit includes a first memory transistor;

one end of the first memory transistor is electrically connected to the top electrode layer of the magnetic memory structure;

The write current is directed from the top electrode layer to the bottom electrode layer through the magnetic tunnel junction by controlling conduction of the first storage transistor and the source line to store data.