CN118585460B - Block addressing method, device, storage control chip and storage medium - Google Patents
Block addressing method, device, storage control chip and storage medium Download PDFInfo
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Abstract
本申请公开了一种块寻址方法、装置、存储控制芯片及存储介质。该方法包括：读取并加载预先存储的块地址表；将当前绑定块的块序号作为索引因子，定位出当前绑定块位于块地址表所属的信息区；基于当前绑定块所属的信息区匹配的参数数据，按照寻址算法计算得到块地址；根据当前绑定块对应的块地址，完成对Flash的写入或者读取。通过绑定块的块序号作为索引因子在块地址表中快速定位出绑定块所属的信息区，并根据绑定块匹配信息区的参数数据，按照寻址算法得到块地址，能够快速得到绑定块的块地址，提高寻址效率，实现读写加速。
The present application discloses a block addressing method, device, storage control chip and storage medium. The method includes: reading and loading a pre-stored block address table; using the block sequence number of the current binding block as an index factor to locate the information area to which the current binding block belongs in the block address table; calculating the block address according to the addressing algorithm based on the parameter data matched by the information area to which the current binding block belongs; and completing the writing or reading of the Flash according to the block address corresponding to the current binding block. By using the block sequence number of the binding block as an index factor to quickly locate the information area to which the binding block belongs in the block address table, and according to the parameter data of the information area matched by the binding block, the block address is obtained according to the addressing algorithm, so that the block address of the binding block can be quickly obtained, the addressing efficiency is improved, and the reading and writing acceleration is realized.
Description
Technical Field
The present invention relates to the field of flash memory technologies, and in particular, to a block addressing method, a block addressing device, and a memory control chip.
Background
NAND FLASH is one of the mainstream storage media, and is widely used in various types of storage products, such as a usb disk, an SD card, and the like. NAND FLASH is sequentially divided into a Bank, a layer by layer Plane,
Block and Page, where Block is the NAND FLASH smallest unit of erase and Page is the NAND FLASH smallest unit of read and write.
Multi-planes is a NAND FLASH operation to improve read-write performance, which requires binding blocks from different planes into bound blocks in advance according to a configured binding rule. When the reading and writing of data is performed,
When data is read from and written to the binding block, transmission time between CACHE REGISTER and PAGE REGISTER in NAND FLASH is shortened, and read-write acceleration is realized.
The binding block is composed of blocks from different planes, and the block addresses of the binding block contain a plurality of blocks, and the block addresses can generate a block address table for unified management in the mass production stage. In the related art, when a read/write operation is performed
When in use, the memory control chip needs to load the whole block address table to address, so as to realize the reading and writing of data, but because the whole block address table needs to be loaded every time of reading and writing, the addressing efficiency of the binding block is lower, and the memory is stored
The random read-write performance of the product can be affected.
Disclosure of Invention
The invention aims to overcome the defects in the prior art and provide a block addressing method, a device, a storage control chip and a storage medium, which can improve addressing efficiency and speed up read-write performance.
A first aspect of the application provides a block addressing method comprising:
Reading and loading a pre-stored block address table;
Using the block serial number of the current binding block as an index factor to locate that the current binding block is positioned in an information area to which the block address table belongs;
Calculating to obtain a block address according to an addressing algorithm based on the parameter data matched with the information area of the current binding block;
And according to the block address corresponding to the current binding block, finishing writing or reading the Flash.
Further, in one embodiment, the calculating, according to an addressing algorithm, the block address based on the parameter data matched with the information area to which the current binding block belongs includes:
Analyzing a flash memory block contained in the current binding block;
reading parameter data of an information area to which each flash memory block belongs, wherein the parameter data comprises CE to which the current flash memory block belongs, bank to which the current flash memory block belongs, and the current flash memory block
The method comprises the steps of a total number of blocks of the planes, a total number of planes of a Bank of the current flash memory block, a position sequence number of a template bit of the block corresponding to the current flash memory block and the planes of the current flash memory block;
and calculating the block address of the current binding block according to the parameter data.
Further, in one embodiment, after parsing the block templates corresponding to planes in Flash, the method further includes:
And if the block templates corresponding to the planes are the same, storing one of the block templates as the block template corresponding to the planes.
Further, in one embodiment, the pre-stored block address table is generated as follows:
Analyzing a block template corresponding to each Plane in Flash;
Classifying each block template into different information areas according to preset dividing rules, and adding index identifiers for each information area to generate a block address table, wherein the preset dividing rules comprise dividing based on CE (customer) to which a current Bank belongs, a Bank to which a current Plane belongs and a binding relation;
The block address table is stored.
A second aspect of the present application provides a block addressing apparatus comprising:
the loading module is used for reading and loading a pre-stored block address table;
the index module is used for taking the block sequence number of the current binding block as an index factor and locating that the current binding block is positioned in an information area to which the block address table belongs;
the addressing module is used for calculating to obtain a block address according to an addressing algorithm based on the information data matched with the information area to which the current binding block belongs;
And the read-write module is used for completing the writing or reading of the Flash according to the block address corresponding to the current binding block.
Further, in one embodiment, the addressing module includes:
the analyzing unit is used for analyzing the flash memory blocks contained in the current binding blocks;
The reading unit is used for reading parameter data of an information area to which each flash memory block belongs, wherein the parameter data comprises CE to which the current flash memory block belongs, bank to which the current flash memory block belongs, total block number of planes to which the current flash memory block belongs, total Plane number of the Bank to which the current flash memory block belongs, position serial numbers of template bits corresponding to the current flash memory block and planes to which the current flash memory block belongs;
And the address calculation unit is used for calculating the block address of the current binding block according to the parameter data.
Further, in one embodiment, the addressing module further includes:
and the compression unit is used for storing one of the block templates as the block template corresponding to each Plane if the block templates corresponding to each Plane are identical.
Further, in one embodiment, the pre-stored block address table is generated as follows:
Analyzing a block template corresponding to each Plane in Flash;
Classifying each block template into different information areas according to preset dividing rules, and adding index identifiers for each information area to generate a block address table, wherein the preset dividing rules comprise dividing based on CE (customer) to which a current Bank belongs, a Bank to which a current Plane belongs and a binding relation;
The block address table is stored.
A third aspect of the present application provides a memory control chip comprising the block addressing apparatus described above.
A fourth aspect of the application provides a computer readable storage medium storing executable code which, when executed by a processor of an electronic device, causes the processor to perform a block addressing method as described above.
The technical scheme includes that a pre-stored block address table is read and loaded, a block serial number of a current binding block is used as an index factor, the current binding block is located in an information area of the block address table, a block address is calculated according to an addressing algorithm based on parameter data matched with the information area of the current binding block, and writing or reading of Flash is completed according to the block address corresponding to the current binding block. The information area of the binding block is rapidly positioned in the block address table by taking the block serial number of the binding block as an index factor, and the block address is obtained according to the parameter data of the matching information area of the binding block and the addressing algorithm, so that the block address of the binding block can be rapidly obtained, the addressing efficiency is improved, and the acceleration of reading and writing is realized.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of a block addressing method according to an embodiment of the present application;
FIG. 2 is a schematic diagram of a block addressing apparatus according to an embodiment of the present application;
FIG. 3 is a schematic diagram of a memory product according to an embodiment of the present application;
FIG. 4 is a schematic diagram illustrating a memory control chip according to an embodiment of the application;
FIG. 5 is a schematic diagram of an electronic device according to an embodiment of the application;
fig. 6 is a schematic diagram showing a correspondence relationship between a flash memory block and a binding block according to an embodiment of the application.
Detailed Description
In order that the invention may be understood more fully, the invention will be described with reference to the accompanying drawings. The drawings illustrate preferred embodiments of the invention. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
It will be understood that when an element is referred to as being "fixed to" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. The terms "vertical," "horizontal," "left," "right," and the like are used herein for illustrative purposes only and are not meant to be the only embodiment.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.
In the related art, when performing read-write operation, the storage control chip needs to load the whole block address table to address, so as to realize the read-write of data, but the addressing efficiency of the binding block is low because the whole block address table needs to be loaded every time of read-write, and the random read-write performance of the storage product is affected.
Therefore, in order to solve the technical problems, the application provides a block addressing method which can improve addressing efficiency and speed up read-write performance.
The technical scheme of the application is described in detail below with reference to the accompanying drawings.
Referring to fig. 1, a block addressing method includes the steps of:
step S110, reading and loading a pre-stored block address table.
The block address table is rather important administrative data as data for managing NAND FLASH, and is used for recording the management table of the block addresses of the blocks in NAND FLASH. Since NAND FLASH contains a large number of blocks, and each block address generally requires 2 bytes of space to be allocated for storage, a certain amount of storage space is required to store the block address table according to the prior art approach. In this embodiment, in consideration of the above situation, the generation manner of the block address table in the prior art is optimized, and the length of the block address table is compressed as much as possible.
The block address table in the embodiment can be generated by analyzing a block template corresponding to each Plane in Flash, classifying each block template into different information areas according to a preset dividing rule, and adding an index identifier to each information area to generate the block address table, wherein the preset dividing rule comprises dividing based on CE (customer) to which a current Bank belongs, bank to which the current Plane belongs and binding relation, and storing the block address table.
Block template-is a binary sequence used to express which blocks are good blocks and which blocks are bad blocks under the current Plane. The template will be the underlying data that will be obtained when a full-disk scan is performed on the mass production stage of NAND FLASH.
In addition, the mass production stage scans a series of basic data for describing NAND FLASH, where the basic data includes a relation between a Bank and a CE (channel), a relation between a Bank and a Plane, a binding relation between a Plane and a Plane, a number of good blocks contained in a Plane, and the like.
According to NAND FLASH basic data obtained in the mass production stage, in this embodiment, each block template may be categorized into different information areas according to a preset division rule, and an index identifier may be added to each information area to form a block address table, and the block address table may be stored. The specific preset dividing rules comprise dividing based on CE (customer line) to which the current Bank belongs, bank to which the current Plane belongs and binding relation.
In order to better understand the technical solution of the present embodiment, a specific column is used for the following description.
Fig. 3 is a schematic diagram showing the structure of the memory product 30 in this embodiment. Memory product 30 includes memory control chip 310 and memory granule 320, memory control chip 310 selects NAND FLASH or NAND FLASH322 through chip select port CE 0. Each NAND FLASH contains 2 planes, with NAND FLASH321 corresponding to A1, A2, NAND FLASH322 corresponding to B1 and B2. In addition, each Plane contains 5 blocks, A11-A15, A21-A25, B11-B15, and B21-B25, respectively.
Mass production scans gave block templates as shown in table 1 below:
wherein, "0" represents that the block is a bad block, and reading and writing of data can not be performed, and "1" represents that the block is a good block, and reading and writing of data can be performed. Additionally, the Plane A1 and the Plane A2 have a binding relationship, and the Plane B1 and the Plane B2 have a binding relationship.
Further, as a preferred embodiment, if the block templates corresponding to the planes are identical, one of the block templates is stored as the block template corresponding to the planes. It should be noted that, when the block templates corresponding to the planes are the same, that is, the block templates A1, A2, B1 and B2 are the same, only one block template may be stored as the block template corresponding to the other planes, which aims to further compress the length of the block address table, and complete multiple multiplexing of the same block template.
Because the block templates A1 and A2 are located under Bank0 and the planes A1 and A2 have a binding relationship, the block templates B1 and B2 are located under Bank1 and the planes B1 and B2 have a binding relationship, and Bank0 and Bank1 are located under CE 0. Therefore, the data of table 1 is divided according to a preset division rule, and an index identifier is added to generate a block address information table as shown in table 2.
The "information area" is an area in which the block template is stored, and is divided based on CE to which the current Bank belongs, bank to which the current Plane belongs, and a binding relationship between planes. "wStartBlkIndex" is one of the index identifications representing the start block number of the binding block in the information area. "wBlkcnt" is another index identity representing the number of binding blocks in the information area.
In this embodiment, A1 and A2 can perform binding, and 3 binding blocks can be obtained after binding A1 and A2 by using the block template, and the sequence numbers of the binding blocks correspond to 0,1 and 2, so that index identifier wStartBlkIndex =0 of info_0, wblcnt=3. B1 Binding can be executed similarly to B2, and after B1 and B2 are bound, 2 binding blocks can be obtained through the block template, and the binding block sequence numbers correspond to 3 and 4, so that index identifier wStartBlkIndex =3 of info_1, wblcnt=2. A total of 5 binding blocks are obtained, wherein basic information of the binding blocks 0-2 can be found in INFO_0, basic information of the binding blocks 3-4 can be found in INFO_1, and the generation of the block address table is completed through the mode.
The generation of the block address table belongs to the pre-process, and is a block address table that needs to be created before step S110, and after the block address table is created, the block address table is stored in NAND FLASH. When the memory control chip 310 needs to write or read data, the read/write operation of each block in NAND FLASH can be implemented by loading the block address table. Since the block template of this embodiment is a binary representation of the sequence, NAND FLASH does not occupy too much NAND FLASH of the memory space even if it contains many blocks. The "division information" and "index mark" added to different information areas are distinguished, and the storage space of NAND FLASH is not occupied too much.
Assuming that each Plane in NAND FLASH includes 2000 blocks, according to the technical solution of the present embodiment, a total of 2000×4=8000 bits, that is, 1000 bytes, each entry of the "partition information" and the "index identifier" is configured to store 2 bytes at most, and a total of 2 information areas consumes=1k+8×4=1032 bytes. Compared to the related art, which uses a manner that each block address requires 2 bytes to manage, the block address table=2000×4×4=16000 bytes. It can be seen that the present application can compress the block address table as much as possible to occupy the memory space NAND FLASH, and simultaneously, when the memory control chip 310 performs the read-write operation on NAND FLASH, the loading speed of the block address table in the RAM of the memory control chip can be greatly increased, so as to greatly improve the random read-write performance of NAND FLASH.
And step 120, using the block serial number of the current binding block as an index factor to locate that the current binding block is positioned in the information area to which the block address table belongs.
After the block address table is created and stored, when the storage control chip needs to write a data to NAND FLASH, the address of the binding block needs to be quickly located, so that the writing is completed. Since it has been determined that A1 and A2 in NAND FLASH210 have a binding relationship in the mass production stage, B1 and B2 in NAND FLASH220 have a binding relationship. At the management level, the bound planes will use a unified Partition (Partition) to manage it, i.e., in this embodiment, A1, A2, B1, and B2 will have a specific Partition0 to manage.
From this, the correspondence relationship (assumed to be sequential binding) between the flash block and the binding block as shown in fig. 6 can be derived.
Partition0 is a Partition for managing two planes A1 and A2, and has 3 binding blocks (S0 to S2) inside, wherein:
Block address of binding block S0 = block address of flash block a12 + block address of flash block a 21;
Block address of binding block S1 = block address of flash block a13 + block address of flash block a 24;
the block address of the binding block S2=the block address of the flash block a 15+the block address of the flash block a 25.
Partition0 is a Partition for managing two planes B1 and B2, and has 2 binding blocks (S3 to S4) inside, wherein:
Block address of binding block S3 = block address of flash block B11 + block address of flash block B21;
the block address of the binding block S4=the block address of the flash block B12+the block address of the flash block B24.
The above correspondence corresponds to the column "index identification" in table 1.
Further, as a preferred embodiment, for planes B1 and B2, the number of binding blocks formed by the binding is 2 blocks, and the binding is implemented in a sequential binding manner, that is, the binding is performed with the blocks of other planes according to the arrangement sequence of the blocks under the current Plane, that is, the flash block B11 and the flash block B21 are bound to form a binding block S3, and the flash block B12 and the flash block B24 are bound to form a binding block S4.
However, in practical applications, in order to better perform the read-write performance of the binding blocks, it is necessary to preferentially select and bind the flash memory blocks with good quality to form the binding blocks. A good quality flash block can be analyzed by determining the size of the ECC, with smaller ECC representing a better quality flash block and larger ECC representing a worse quality flash block. Because the flash memory block comprises a plurality of pages, each page corresponds to an ECC, all the ECCs of the pages are read, and the ECC of the current flash memory block is calculated by adopting a mean value calculation mode. If the current flash block contains 10 pages, the ECC of each page is 50, 60, 40, 30, 20, 60, 50, 40, respectively, so the ECC of the current flash block= (50+60+40+30+20+60+50+40)/8≡44, so the current flash block
ECC is equal to 44. If it is determined that the quality of the flash block B12 is not the same as that of the flash block B13, the flash block B13 and the flash block B24 are preferentially bound to form a binding block S3.
The memory control chip 310 is now ready to write a new copy of data to the memory granule 320, which needs to be written to the binding block S1. The RAM of the memory control chip 310 loads the block address table, rapidly locates in the block address table according to the index "wBlkIndex" of the binding block S1, and calculates the block address of the binding block S1.
In this embodiment, since the classification of the information area has been made for each binding block according to the "division information" and the "index identification". Thus, letting wBlkIndex =1, wblkindex be wStartBlkIndex, and < wStartBlkIndex + wBlkcnt, determining that the binding block S1 is located in the information area info_0, the fast locating of the binding block S1 is completed.
And step 130, calculating to obtain a block address according to an addressing algorithm based on the parameter data matched with the information area to which the current binding block belongs.
In this embodiment, when the binding block S1 is located in the information area info_0, the parameter data matched with the information area is read according to the information area info_0, and the block address is calculated according to the addressing algorithm. The addressing algorithm can be realized as follows:
The method comprises the steps of obtaining a current binding block, analyzing a flash memory block contained in the current binding block, reading parameter data of an information area to which each flash memory block belongs, wherein the parameter data comprise a Bank to which the current flash memory block belongs, the total block number of planes to which the current flash memory block belongs, the total Plane number of the Bank to which the current flash memory block belongs, a position sequence number of a template bit of the block corresponding to the current flash memory block and the planes to which the current flash memory block belongs, and calculating according to the parameter data to obtain a block address of the current binding block.
Since the block address of the binding block S1 is composed of the block address of the flash block a13 and the block address of the flash block a24, the block addresses of the flash block a13 and the flash block a24 are calculated, respectively, so that the block address of the binding block S1 can be obtained.
In the Bank0 to which the flash block a13 belongs, the total number of flash blocks in the Plane A1 to which the flash block a13 belongs is 5 blocks, the total number of planes in the Bank0 to which the flash block a13 belongs is 2, the bit of the flash block a13 based on the block template "01101" is "1", and the Plane A1 sequence number to which the flash block a13 belongs is 0, and therefore, the block address of the flash block a13 is calculated by the formula 1) according to the above parameter data.
Block address=INFO[i].Bank[j]*wBlkPerBank+Planecnt*x+Plane[k] 1)
Wherein:
"Block address" represents the address of the current flash Block;
"INFO [ i ]" represents the information area to which the current flash block belongs;
"Bank [ j ]" represents the Bank to which the current flash block belongs;
"wBlkPerBank" represents the total number of blocks of the Bank to which the current flash block belongs;
"Planecnt" represents the total number of planes under the Bank to which the current flash block belongs;
"x" represents the position number of the template bit of the corresponding block of the current flash block;
"Plane [ k ]" represents in which Plane under the belonging Bank the current flash block is located.
In this embodiment, INFO [ i ]. Bank [ j ] =0, wblkperbank=5, planecnt= 2;x =1;
Plane k=0, the address of flash block a13 can be calculated:
Address=0×5+2×2+0=4 of flash block a 13.
Similarly, the block address of flash block a24 is calculated according to equation 1):
Address=0×5+2×3+1=7 of flash block a 24.
According to the above steps, the address of the binding block S1 can be obtained, and it should be noted that the address of the binding block S1 is composed of the addresses of the flash memory block a13 and the flash memory block a 24.
And step 140, according to the block address corresponding to the current binding block, writing or reading the Flash is completed.
Through the above steps, the block address of the binding block can be obtained, and the storage control chip 310 can implement the write operation to Flash according to the block address of the binding block S1. Note that, the principle of calculating the block address of the binding block is the same regardless of whether the writing or the reading is performed, and therefore, in the case of the present embodiment, only the writing is described as an example.
According to the technical scheme, the information area of the binding block is rapidly located in the block address table by taking the block sequence number of the binding block as an index factor, the block address is obtained according to the parameter data of the matching information area of the binding block and the addressing algorithm, the block address of the binding block can be rapidly obtained, the addressing efficiency is improved, and the acceleration of reading and writing is realized.
Corresponding to the method embodiment, the application also provides a block addressing device and a corresponding embodiment.
Fig. 2 is a schematic diagram of a block addressing apparatus according to an embodiment of the present application.
Referring to fig. 2, a block addressing apparatus 200 includes a loading module 210, an indexing module 220, an addressing module 230, and a read/write module 240. Wherein:
the loading module 210 is configured to read and load a pre-stored block address table.
The method includes the steps of storing a block address table, and storing a block address table, wherein the block address table is stored in advance, the block address table is stored in advance and can be generated and analyzed to be corresponding to each Plane in Flash, the block templates are classified into different information areas according to a preset dividing rule, index marks are added to each piece of information, and the block address table is generated, wherein the preset dividing rule comprises dividing based on a band and a binding relation of the current Plane, and the block address table is stored.
The indexing module 220 is configured to locate, using the block number of the current binding block as an index factor, that the current binding block is located in an information area to which the block address table belongs.
The addressing module 230 is configured to calculate a block address according to an addressing algorithm based on the parameter data matched with the information area to which the current binding block belongs.
The read-write module 240 is configured to complete writing or reading of Flash according to a block address corresponding to the current binding block.
Further, in one embodiment, the addressing module 230 includes a parsing unit 231, a compressing unit 232, a reading unit 233, and an addressing unit 234. Wherein:
the parsing unit 231 is configured to parse out the flash memory blocks included in the current binding block.
The compressing unit 232 is configured to store one of the block templates as the block template corresponding to each Plane if the block templates corresponding to each Plane are identical.
The reading unit 233 is configured to read parameter data of an information area to which each flash block belongs, where the parameter data includes a Bank to which a current flash block belongs, a total number of blocks of planes to which the current flash block belongs, a total number of planes of the Bank to which the current flash block belongs, a position sequence number of a template bit of a block corresponding to the current flash block, and a Plane to which the current flash block belongs.
The address calculation unit 234 is configured to calculate a block address of the current binding block according to the parameter data.
The block addressing method implemented by the block addressing apparatus disclosed in this embodiment is as described in the above embodiment, and thus will not be described in detail herein. Alternatively, each module in the present embodiment and the other operations or functions described above are respectively for realizing the method in the foregoing embodiment.
Fig. 4 is a schematic diagram illustrating a memory control chip according to an embodiment of the present application.
Referring to fig. 4, a memory control chip 310 includes the block addressing apparatus 200 described above.
It should be noted that, the storage control chip 310 of this embodiment uses the block serial number of the binding block as an index factor to quickly locate the information area to which the binding block belongs in the block address table, and obtains the block address according to the addressing algorithm according to the parameter data of the matching information area of the binding block, so that the block address of the binding block can be quickly obtained, the addressing efficiency is improved, and the acceleration of reading and writing is realized.
Referring to FIG. 5, another embodiment of the application shows a computing electronic device 500 comprising a processor 510 and a memory 520.
The Processor 510 may be a central processing unit (Central Processing Unit, CPU), but may also be other general purpose processors, digital signal processors (DIGITAL SIGNAL Processor, DSP), application SPECIFIC INTEGRATED Circuit (ASIC), field programmable gate array (Field Programmable GATE ARRAY, FPGA) or other programmable logic device, discrete gate or transistor logic device, discrete hardware components, or the like.
A general purpose processor may be a microprocessor or the processor may be any conventional processor 510 that may include various types of storage elements, such as system memory, read Only Memory (ROM), and persistent storage.
Where the ROM may store static data or instructions that are required by the processor 510 or other modules of the computer. The persistent storage may be a readable and writable storage. The persistent storage may be a non-volatile memory device that does not lose stored instructions and data even after the computer is powered down. In some embodiments, the persistent storage device employs a mass storage device (e.g., magnetic or optical disk, flash memory) as the persistent storage device.
In other embodiments, the persistent storage may be a removable storage device (e.g., diskette, optical drive). The system memory may be a read-write memory device or a volatile read-write memory device, such as dynamic random access memory. The system memory may store instructions and data that are required by some or all of the processors at runtime.
Furthermore, memory 520 may include any combination of computer-readable storage media, including various types of semiconductor memory chips (e.g., DRAM, SRAM, SDRAM, flash memory, programmable read-only memory), magnetic disks, and/or optical disks may also be employed.
In some embodiments, memory 520 may include readable and/or writable removable storage devices such as Compact Discs (CDs), digital versatile discs (e.g., DVD-ROM, dual layer DVD-ROM), blu-ray discs read only, super-dense discs, flash memory cards (e.g., SD cards, min SD cards, and Micro-SD cards, etc.), magnetic floppy disks, and the like. The computer readable storage medium does not contain a carrier wave or an instantaneous electronic signal transmitted by wireless or wired transmission. The memory 520 has stored thereon executable code that, when processed by the processor 510, can cause the processor 510 to perform some or all of the methods described above.
Furthermore, the method according to the application may also be implemented as a computer program or computer program product comprising computer program code instructions for performing part or all of the steps of the above-described method of the application.
Or the application may also be embodied as a computer-readable storage medium (or non-transitory machine-readable storage medium or machine-readable storage medium) having stored thereon executable code (or a computer program or computer instruction code) which, when executed by a processor of an electronic device (or server, etc.), causes the processor to perform some or all of the steps of the above-described method according to the application.
The foregoing description of embodiments of the application has been presented for purposes of illustration and description, and is not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the various embodiments described. The terminology used herein was chosen in order to best explain the principles of the embodiments, the practical application, or the improvement of technology in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
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| CN114448890B (en) * | 2021-12-22 | 2023-10-10 | 天翼云科技有限公司 | Addressing methods, devices, electronic equipment and storage media |
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