CN118585021A - Bias voltage generation circuit - Google Patents

Abstract

A bias generating circuit includes a first circuit subunit, a second circuit subunit and a third circuit subunit. The first circuit subunit is used to generate a first bias voltage at a first node in response to a first current and a first input voltage. The second circuit subunit is coupled to the first circuit subunit to receive the first bias voltage and generate a second current flowing through a second node, wherein the second current is mirrored from the first current. The third circuit subunit is coupled to the second node to generate a second bias voltage at a third node in response to the second current and a second input voltage.

Description

Bias voltage generation circuit

Technical Field

The present invention relates to a bias voltage generating circuit, and more particularly to a bias voltage generating circuit for generating a stable bias voltage required by a power amplifier circuit.

Background Art

Amplifier circuits are commonly used in communication systems to increase the output power of signals. Amplifier circuits usually obtain their energy source through a power supply, control the waveform of the output signal to be consistent with the input signal, and increase its amplitude, thereby producing a proportionally larger signal at the output end.

Generally speaking, the design of an amplifier circuit requires a trade-off between power consumption and linearity. For example, a nonlinear amplifier circuit generally has a higher power amplifier efficiency (PAE), while a linear amplifier circuit generally has a relatively lower PAE.

By properly designing the bias voltage, the amplifier circuit can achieve a better balance between linearity and amplification efficiency. In addition, if the DC current inside the amplifier circuit can be precisely controlled, the power consumption of the amplifier circuit can be effectively adjusted, and the same amplifier circuit implemented by different chips can have similar performance.

Therefore, how to generate the stable bias voltage and precise DC current required by the power amplifier circuit is a topic worthy of attention in the field of amplifier circuit design.

Summary of the invention

An object of the present invention is to provide a bias voltage generating circuit to generate a stable bias voltage and a precise direct current required by a power amplifier circuit.

According to one embodiment of the present invention, a bias generating circuit includes a first circuit subunit, a second circuit subunit and a third circuit subunit. The first circuit subunit is used to generate a first bias voltage at a first node in response to a first current and a first input voltage. The second circuit subunit is coupled to the first circuit subunit to receive the first bias voltage and generate a second current flowing through a second node, wherein the second current is mirrored from the first current. The third circuit subunit is coupled to the second node to generate a second bias voltage at a third node in response to the second current and a second input voltage.

According to another embodiment of the present invention, a bias generating circuit includes a first circuit subunit, a second circuit subunit and a third circuit subunit. The first circuit subunit is used to generate a first bias voltage at a first node in response to a first current and a first input voltage. The second circuit subunit is coupled to the first circuit subunit to receive the first bias voltage and generate a second current flowing through a second node, wherein the second current is mirrored from the first current. The third circuit subunit is coupled to the second node to generate a second bias voltage at a third node in response to the second current and a second input voltage. The first node is also coupled to a first bias input terminal of a power amplifier circuit to supply the first bias voltage to the power amplifier circuit, and the third node is also coupled to a second bias input terminal of the power amplifier circuit to supply the second bias voltage to the power amplifier circuit.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram showing an example of a bias voltage generating circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing an example of a bias voltage generating circuit according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing an example of a power amplifier according to an embodiment of the present invention.

DETAILED DESCRIPTION

FIG1 is a circuit diagram showing an example of a bias generating circuit according to a first embodiment of the present invention. The bias generating circuit 100 may include a first circuit subunit 110, a second circuit subunit 120, and a third circuit subunit 130. The first circuit subunit 110 is used to generate a bias voltage VGP-1 at a node N11 in response to a current I1_dc and an input voltage V1_dc. The second circuit subunit 120 is coupled to the first circuit subunit 110 to receive the bias voltage VGP-1 and generate a current I1'_dc flowing through a node N12, wherein the current I1'_dc is mirrored from the current I1_dc. The third circuit subunit 130 is coupled to the node N12 to generate a bias voltage VGN-1 at a node N13 in response to the current I1'_dc and the input voltage V1'_dc.

The first circuit subunit 110 may include an amplifier circuit OP11, a transistor T11 and a current source IS-1. The amplifier circuit OP11 includes a non-inverting input terminal, an inverting input terminal and an output terminal. The non-inverting input terminal of the amplifier circuit OP11 receives an input voltage V1_dc. The transistor T11 includes a first electrode coupled to the output terminal of the amplifier circuit OP11, a second electrode coupled to the inverting input terminal of the amplifier circuit OP11, and a third electrode coupled to a first voltage source. According to one embodiment of the present invention, the transistor T11 may be a P-type metal oxide semiconductor field effect transistor (Metal Oxide Semiconductor Field Effect Transistor, abbreviated as MOSFET), referred to as a PMOS transistor, and the first electrode may be a gate of the PMOS transistor, the second electrode may be a source of the PMOS transistor, and the third electrode may be a drain of the PMOS transistor. In addition, in the first embodiment of the present invention, the first voltage source may be a voltage source for providing a ground voltage. The current source IS-1 is used to provide a current I1_dc.

In the embodiment of the present invention, the gate of the transistor T11 is coupled to the output terminal of the amplifier circuit OP11 and the node N11 at the same time, and is further coupled to the second circuit sub-unit 120 through the node N11.

According to one embodiment of the present invention, assuming that the amplifier circuit OP11 has a very large gain, its inverting input terminal and non-inverting input terminal will be a virtual short circuit (virtual ground). Therefore, the voltage at the inverting input terminal of the amplifier circuit OP11, which is a voltage generated at the second electrode (e.g., the source) of the transistor T11 in response to the current I1_dc and the input voltage V1_dc, will be equal to or substantially equal to the input voltage V1_dc.

The second circuit subunit 120 may include a transistor T12. The transistor T12 includes a first electrode coupled to the output terminal of the amplifier circuit OP11, a second electrode coupled to the node N12, and a third electrode coupled to the first voltage source. According to one embodiment of the present invention, the transistor T12 may be a PMOS transistor, and the first electrode may be the gate of the PMOS transistor, the second electrode may be the source of the PMOS transistor, and the third electrode may be the drain of the PMOS transistor. The first electrode of the transistor T12 may be electrically connected to the first electrode of the transistor T11, and is coupled to the output terminal of the amplifier circuit OP11 and the node N11 at the same time. In an embodiment of the present invention, the transistor T11 and the transistor T12 may be designed to have the same width, for example, Mp=1 marked in the figure. Since transistor T11 and transistor T12 are designed to have the same width, and the gate voltage and drain voltage of transistor T11 and transistor T12 are the same, the current I1’_dc flowing through transistor T12 can be a mirror current of current I1_dc, and the current magnitude of current I1’_dc can be equal to or substantially equal to the current magnitude of current I1_dc.

The third circuit subunit 130 may include an amplifier circuit OP12 and a transistor T13. The amplifier circuit OP12 includes a non-inverting input terminal, an inverting input terminal and an output terminal. The non-inverting input terminal of the amplifier circuit OP11 can receive an input voltage V1'_dc. The transistor T13 includes a first electrode coupled to the output terminal of the amplifier circuit OP12, a second electrode coupled to the inverting input terminal of the amplifier circuit OP12, and a third electrode coupled to a second voltage source. According to one embodiment of the present invention, the transistor T13 may be an N-type metal oxide semiconductor field effect transistor, referred to as an NMOS transistor, and the first electrode may be the gate of the NMOS transistor, the second electrode may be the source of the NMOS transistor, and the third electrode may be the drain of the NMOS transistor. In addition, in the first embodiment of the present invention, the second voltage source may be a voltage source for providing a voltage VDD, and the second electrode of the transistor T13 is coupled to the node N12, and the first electrode of the transistor T13 is coupled to the node N13 to provide a bias voltage VGN-1.

Assuming that the amplifier circuit OP12 has a very large gain, its inverting input terminal and non-inverting input terminal will be a virtual short circuit (virtual ground), so the voltage at the inverting input terminal of the amplifier circuit OP12 will be equal to or substantially equal to the input voltage V1'_dc. According to one embodiment of the present invention, the amplifier circuits OP11 and OP12 can be operational amplifiers.

According to an embodiment of the present invention, the input voltage V1_dc received by the first circuit sub-unit 110 and the input voltage V1'_dc received by the third circuit sub-unit 130 may be the same voltage. In addition, in the embodiment of the present invention, the current source IS-1 is used to provide a direct current I1_dc, wherein the current I1_dc may be generated by a bandgap circuit. Therefore, in the embodiment of the present invention, the current I1_dc may be a very precise direct current.

According to the first embodiment of the present invention, the first circuit sub-unit 110 is used to establish a stable I1_dc at the second electrode of the transistor T11, and mirror the current I1_dc to the second circuit sub-unit 120. Since the transistor T12 of the second circuit sub-unit 120 and the transistor T13 of the third circuit sub-unit 130 are coupled to the node N12, the mirrored stable current I1'_dc will flow through the transistor T12 and the transistor T13. In addition, in the embodiment of the present invention, the bias generating circuit 100 can provide the bias voltages VGP-1 and VGN-1 to a power amplifier circuit (not shown in FIG. 1) through the nodes N11 and N13, respectively, as its bias input, thereby providing the stable bias required by the power amplifier circuit. The stable bias voltage can further enable the power amplifier circuit to mirror another stable current in response to the current I1’_dc flowing through transistors T12 and T13, and the current size inside the power amplifier circuit can be a multiple of the current I1’_dc, thereby generating the precise DC current required by the power amplifier circuit.

It should be noted that the present invention is not limited to the transistor type shown in Figure 1. In the second embodiment of the present invention, a stable direct current can also be established by an NMOS transistor.

FIG2 is a circuit diagram showing an example of a bias generating circuit according to a second embodiment of the present invention. The bias generating circuit 200 may include a first circuit subunit 210, a second circuit subunit 220, and a third circuit subunit 230. The first circuit subunit 210 is used to generate a bias voltage VGN-2 at a node N21 in response to a current I2_dc and an input voltage V2_dc. The second circuit subunit 220 is coupled to the first circuit subunit 210 to receive the bias voltage VGN-2 and generate a current I2'_dc flowing through a node N22, wherein the current I2'_dc is mirrored from the current I2_dc. The third circuit subunit 230 is coupled to the node N22 to generate a bias voltage VGP-2 at a node N23 in response to the current I2'_dc and the input voltage V2'_dc.

The first circuit subunit 210 may include an amplifier circuit OP21, a transistor T21 and a current source IS-2. The amplifier circuit OP21 includes a non-inverting input terminal, an inverting input terminal and an output terminal. The non-inverting input terminal of the amplifier circuit OP21 receives an input voltage V2_dc. The transistor T21 includes a first pole coupled to the output terminal of the amplifier circuit OP21, a second pole coupled to the inverting input terminal of the amplifier circuit OP21, and a third pole coupled to a first voltage source. According to one embodiment of the present invention, the transistor T21 may be an NMOS transistor, and the first pole may be the gate of the NMOS transistor, the second pole may be the source of the NMOS transistor, and the third pole may be the drain of the NMOS transistor. In addition, in a second embodiment of the present invention, the first voltage source may be a voltage source for providing a voltage VDD. The current source IS-2 is used to provide a current I2_dc.

In the embodiment of the present invention, the gate of the transistor T21 is coupled to the output terminal of the amplifier circuit OP21 and the node N21 at the same time, and is further coupled to the second circuit sub-unit 220 through the node N21.

According to one embodiment of the present invention, assuming that the amplifier circuit OP21 has a very large gain, its inverting input terminal and non-inverting input terminal will be a virtual short circuit (virtual ground). Therefore, the voltage at the inverting input terminal of the amplifier circuit OP21, which is a voltage generated at the second electrode (e.g., source) of the transistor T21 in response to the current I2_dc and the input voltage V2_dc, will be equal to or substantially equal to the input voltage V2_dc.

The second circuit subunit 220 may include a transistor T22. The transistor T22 includes a first electrode coupled to the output end of the amplifier circuit OP21, a second electrode coupled to the node N22, and a third electrode coupled to the first voltage source. According to one embodiment of the present invention, the transistor T22 may be an NMOS transistor, and the first electrode may be the gate of the NMOS transistor, the second electrode may be the source of the NMOS transistor, and the third electrode may be the drain of the NMOS transistor. The first electrode of the transistor T22 may be electrically connected to the first electrode of the transistor T21, and is coupled to the output end of the amplifier circuit OP21 and the node N21 at the same time. In an embodiment of the present invention, the transistor T21 and the transistor T22 may be designed to have the same width, for example, Mn=1 marked in the figure. Since the transistor T21 and the transistor T22 are designed to have the same width, and the gate voltage and the drain voltage of the transistor T21 and the transistor T22 are the same, the current I2’_dc flowing through the transistor T22 can be a mirror current of the current I2_dc, and the current magnitude of the current I2’_dc can be equal to or substantially equal to the current magnitude of the current I2_dc.

The third circuit subunit 230 may include an amplifier circuit OP22 and a transistor T23. The amplifier circuit OP22 includes a non-inverting input terminal, an inverting input terminal and an output terminal. The non-inverting input terminal of the amplifier circuit OP21 can receive an input voltage V2'_dc. The transistor T23 includes a first electrode coupled to the output terminal of the amplifier circuit OP22, a second electrode coupled to the inverting input terminal of the amplifier circuit OP22, and a third electrode coupled to a second voltage source. According to one embodiment of the present invention, the transistor T23 may be a PMOS transistor, and the first electrode may be the gate of the PMOS transistor, the second electrode may be the source of the PMOS transistor, and the third electrode may be the drain of the PMOS transistor. In addition, in the second embodiment of the present invention, the second voltage source may be a voltage source for providing a ground voltage, and the second electrode of the transistor T23 is coupled to the node N22, and the first electrode of the transistor T23 is coupled to the node N23 to provide a bias voltage VGP-2.

Assuming that the amplifier circuit OP22 has a very large gain, its inverting input terminal and non-inverting input terminal will be a virtual short circuit (virtual ground), so the voltage at the inverting input terminal of the amplifier circuit OP22 will be equal to or substantially equal to the input voltage V2'_dc. According to one embodiment of the present invention, the amplifier circuits OP21 and OP22 can be operational amplifiers.

According to an embodiment of the present invention, the input voltage V2_dc received by the first circuit sub-unit 210 and the input voltage V2'_dc received by the third circuit sub-unit 230 may be the same voltage. In addition, in the embodiment of the present invention, the current source IS-2 is used to provide a direct current I2_dc, wherein the current I2_dc may be generated by a bandgap circuit. Therefore, in the embodiment of the present invention, the current I2_dc may be a very precise direct current.

According to the second embodiment of the present invention, the first circuit sub-unit 210 is used to establish a stable current I2_dc at the second electrode of the transistor T21, and mirror the current I2_dc to the second circuit sub-unit 220. Since the transistor T22 of the second circuit sub-unit 220 and the transistor T23 of the third circuit sub-unit 230 are coupled to the node N22, the mirrored stable current I2'_dc will flow through the transistor T22 and the transistor T23. In addition, in the embodiment of the present invention, the bias generating circuit 200 can provide the bias voltages VGP-2 and VGN-2 to a power amplifier circuit (not shown in FIG. 2) through the nodes N21 and N23, respectively, as its bias input, thereby providing the stable bias required by the power amplifier circuit. The stable bias voltage can further enable the power amplifier circuit to mirror another stable current in response to the current I2’_dc flowing through transistors T22 and T23, and the current size inside the power amplifier circuit can be a multiple of the current I2’_dc, thereby generating the precise DC current required by the power amplifier circuit.

FIG3 is a circuit diagram of an example of a power amplifier according to an embodiment of the present invention. The power amplifier circuit 300 may include a signal input terminal IN, bias input terminals Bias_1 and Bias_2, an amplifier circuit 310, and a matching circuit 320. The signal input terminal IN is used to receive an input signal Iin, wherein the input signal Iin may be a current signal. The bias input terminals Bias_1 and Bias_2 are used to receive bias voltages VGN and VGP, respectively, wherein the bias voltage VGN may be the bias voltage VGN-1 generated by the bias generating circuit 100 or the bias voltage VGN-2 generated by the bias generating circuit 200, and the bias voltage VGP may be the bias voltage VGP-1 generated by the bias generating circuit 100 or the bias voltage VGP-2 generated by the bias generating circuit 200.

The amplifier circuit 310 is coupled to the input terminal IN to receive the input signal Iin and generate currents Idn and Idp. The matching circuit 320 is coupled to the amplifier circuit 310 to match the output impedance of the power amplifier circuit 300 with the impedance of the antenna. According to an embodiment of the present invention, the matching circuit 320 can also be used to combine the currents Idn and Idp to generate an output signal Io. The output signal Io can be further coupled to the antenna terminal via a coupling circuit coupled to the antenna. The output signal finally provided to the antenna can be generated through the coupling effect.

According to one embodiment of the present invention, the bias input terminals Bias_1 and Bias_2 of the power amplifier circuit 300 can be respectively coupled to corresponding nodes of the bias generating circuit. For example, the bias input terminal Bias_1 can be coupled to the node N13 of the bias generating circuit 100 or to the node N21 of the bias generating circuit 200, and the bias input terminal Bias_2 can be coupled to the node N11 of the bias generating circuit 100 or to the node N23 of the bias generating circuit 200, so as to be supplied with or applied with corresponding bias.

In addition, in an embodiment of the present invention, the transistors T13 and T12 in the bias generating circuit 100 or the transistors T22 and T23 in the bias generating circuit 200 can be respectively combined to form a mirror circuit to mirror the current I1’_dc or I2’_dc to the power amplifier circuit 300.

In response to the supply of bias voltage VGN (i.e., bias voltage VGN-1 or VGN-2) and the action of the aforementioned mirror circuit, current Idn is generated in power amplifier circuit 300. Similarly, in response to the supply of bias voltage VGP (i.e., bias voltage VGP-1 or VGP-2) and the action of the aforementioned mirror circuit, current Idp is generated in power amplifier circuit 300, wherein current Idn and current Idp are mirrored from current I1'_dc flowing through transistors T13 and T12 or from current I2'_dc flowing through transistors T23 and T22.

According to one embodiment of the present invention, the amplifier circuit 310 may be a push-pull amplifier circuit and may include transistors T1 and T2. The transistors T1 and T2 may be transistors of different types. For example, in one embodiment of the present invention, the transistor T1 is an NMOS transistor and the transistor T2 is a PMOS transistor. In one embodiment of the present invention, the bias voltage VGN (i.e., the bias voltage VGN-1 generated by the bias generating circuit 100 or the bias voltage VGN-2 generated by the bias generating circuit 200) is supplied to a first electrode of the transistor T1, such as a gate electrode, and the bias voltage VGP (i.e., the bias voltage VGP-1 generated by the bias generating circuit 100 or the bias voltage VGP-2 generated by the bias generating circuit 200) is supplied to a first electrode of the transistor T2, such as a gate electrode.

In addition, according to an embodiment of the present invention, the width of transistor T1 can be designed to be greater than the width of the transistor (e.g., transistor T13 or T22) in the bias voltage generating circuit for generating the corresponding bias voltage VGN-1 or VGN-2. For example, the width of transistor T1 can be N times that of transistors T13 and T22, such as Mn=N marked in the figure, where N is a positive number. Similarly, the width of transistor T2 can be designed to be greater than the width of the transistor (e.g., transistor T12 or T23) in the bias voltage generating circuit for generating the corresponding bias voltage VGP-1 or VGP-2. For example, the width of transistor T2 can be N times that of transistors T12 and T23, such as Mp=N marked in the figure. It should be noted that there are many methods for designing transistors of different widths in this art. For example, transistors of different widths can be directly configured in the circuit. As mentioned above, the width of transistor T1 is designed to be N times the width of transistor T13 or T22, and the width of transistor T2 is designed to be N times the width of transistor T12 or T23. Alternatively, transistors of the same width are configured in the circuit, but the number of transistors connected in parallel is positively correlated with the multiple of the width. For example, if the width of the transistor in the bias generating circuit is (1/N) times the width of the transistor in the corresponding power amplifier circuit, then in the power amplifier circuit, it can be implemented by coupling in parallel N transistors with the same width as the corresponding transistor in the bias generating circuit. Therefore, the M in Mn=1, Mp=1, Mn=N and Mp=N marked in the figure represents the meaning of multiple transistors, n or p represents the transistor type, the value after the equal sign represents the multiple of the width or the number of transistors with equal width, and the gates of the N transistors with equal width coupled in parallel are commonly coupled to a gate contact, the sources are commonly coupled to a source contact, and the drains are commonly coupled to a drain contact.

In the embodiment of the present invention, the width of transistors T1 and T2 is designed to be larger than the width of the transistors in the bias generating circuit for generating the bias voltage received by them, so as to achieve the effect of amplifying the mirror current. For example, assuming that the width of transistors T1 and T2 is designed to be N times the width of the transistors in the bias generating circuit for generating the corresponding bias voltage, the current Idn and the current Idp will be N times I1'_dc or I2'_dc respectively. If the current Idc is used to represent the current I1'_dc flowing through transistors T13 and T12 and the current I2'_dc flowing through transistors T23 and T22, the magnitude relationship between the currents of the power amplifier circuit and the bias generating circuit can be expressed as follows:

Idn = N * Idc;

Idp=N*Idc.

The current Idn and the current Idp are also precise DC currents. Once the current Idn and the current Idp and the bias voltages VGN and VGP are precisely controlled, the bias voltage Vdc can be naturally generated at the signal input terminal IN. In one embodiment of the present invention, the bias voltage Vdc generated in the power amplifier circuit 300 is equal to or substantially equal to the input voltage V1_dc/V2_dc of the bias generating circuit.

In the embodiment of the present invention, by precisely controlling the voltage levels of the bias voltage Vdc, the bias voltage VGN, and the bias voltage VGP, the amplifier circuit 310 can be biased in class A, class AB, or deep class A amplification operation. In addition, by precisely controlling these bias voltages, the power amplifier circuit 300 can achieve a better balance between linearity and amplification efficiency. In addition, by precisely controlling these bias voltages, the DC current of the power amplifier circuit can also be stabilized.

It should be noted that the present invention is not limited to applying the proposed bias generating circuit to the power amplifier circuit shown in FIG3. The bias generating circuit proposed in the present invention, for example, the bias generating circuit 100/200, can also be applied to other power amplifier circuits to provide a corresponding bias voltage and utilize its internal stable small DC current to cause the power amplifier circuit to generate a corresponding mirror current, and the mirror current can be a relatively large and stable DC current.

In summary, the bias voltage generating circuit proposed in the present invention utilizes two input signals (e.g., input voltage V1_dc/V2_dc and current I1_dc/I2_dc) to generate a stable bias voltage and a DC current, and then provides the stable bias voltage to a power amplifier circuit. By controlling the bias voltage, the power amplifier circuit can be biased in a specific type (e.g., class A, class AB, or deep class A) amplification operation. In addition, by providing the bias voltage, the power amplifier circuit can mirror a precise DC current, effectively adjust the power consumption of the power amplifier circuit, and enable the same power amplifier circuit implemented by different chips to have similar performance.

The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

【Explanation of symbols】

100,200: Bias voltage generation circuit

110, 210: first circuit subunit

120, 220: Second circuit subunit

130,230: third circuit subunit

300: Power amplifier circuit

310: Amplifier circuit

320: Matching circuit

Bias_1, Bias_2: Bias input terminals

I1_dc, I1’_dc, I2_dc, I2’_dc, Idn, Idp: current

Iin: input signal

IN: Signal input terminal

Io: output signal

IS-1, IS-2: Current source

N11, N12, N13, N21, N22, N23: nodes

OP11,OP12,OP21,OP22:Amplifier circuit

T1, T11, T12, T13, T2, T21, T22, T23: Transistors

V1_dc, V1’_dc, V2_dc, V2’_dc: input voltage

Vdc, VGN, VGN-1, VGN-2, VGP, VGP-1, VGP-2: bias voltage.

Claims (10)

1. A bias generating circuit, comprising: a first circuit subunit, for generating a first bias voltage at a first node in response to a first current and a first input voltage; a second circuit sub-unit, coupled to the first circuit sub-unit, for receiving the first bias voltage and generating a second current flowing through a second node, wherein the second current is mirrored from the first current; and A third circuit subunit is coupled to the second node and is used to generate a second bias voltage at a third node in response to the second current and a second input voltage. 2 . The bias voltage generating circuit as claimed in claim 1 , wherein the first input voltage and the second input voltage are the same voltage. 3. The bias generating circuit as claimed in claim 1, wherein the first circuit subunit comprises: a first amplifier circuit, comprising a non-inverting input terminal, an inverting input terminal and an output terminal, wherein the non-inverting input terminal receives the first input voltage; a first transistor including a first electrode coupled to the output terminal of the first amplifier circuit, a second electrode coupled to the inverting input terminal of the first amplifier circuit, and a third electrode coupled to a first voltage source; and a current source, coupled to the second electrode of the first transistor, for providing the first current, The first electrode of the first transistor is also coupled to the first node. 4 . The bias voltage generating circuit as claimed in claim 3 , wherein a voltage generated at the second electrode of the first transistor in response to the first current and the first input voltage is equal to or substantially equal to the first input voltage. 5. The bias generating circuit as claimed in claim 3, wherein the second circuit subunit comprises: A second transistor includes a first electrode coupled to the output terminal of the first amplifier circuit, a second electrode coupled to the second node, and a third electrode coupled to the first voltage source. 6. The bias voltage generating circuit as claimed in claim 5, wherein the third circuit subunit comprises: a second amplifier circuit comprising a non-inverting input terminal, an inverting input terminal and an output terminal, wherein the non-inverting input terminal receives the second input voltage; and A third transistor includes a first electrode coupled to the output terminal of the second amplifier circuit, a second electrode coupled to the inverting input terminal of the second amplifier circuit, and a third electrode coupled to a second voltage source, wherein the second electrode of the third transistor is coupled to the second node, and the first electrode of the third transistor is coupled to the third node. 7 . The bias generating circuit as claimed in claim 6 , wherein the second transistor and the third transistor group form a mirror circuit for mirroring the second current to a power amplifier circuit. 8. A bias generating circuit as described in claim 7, wherein the first node is also coupled to a first bias input terminal of the power amplifier circuit for supplying the first bias voltage to the power amplifier circuit, and the third node is also coupled to a second bias input terminal of the power amplifier circuit for supplying the second bias voltage to the power amplifier circuit. 9. The bias generating circuit of claim 8, wherein in response to the supply of the first bias voltage, a third current is generated in the power amplifier circuit, and in response to the supply of the second bias voltage, a fourth current is generated through the power amplifier circuit, wherein the third current and the fourth current are mirrored from the second current. 10. The bias generating circuit as claimed in claim 1, wherein a current magnitude of the first current is equal to or substantially equal to a current magnitude of the second current.