CN118584199B - A test device and test method for dynamic on-resistance of gallium nitride power device - Google Patents
A test device and test method for dynamic on-resistance of gallium nitride power device Download PDFInfo
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
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- G01R27/02—Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant
- G01R27/08—Measuring resistance by measuring both voltage and current
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- G—PHYSICS
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
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Abstract
The invention discloses a testing device and a testing method for dynamic on-resistance of a gallium nitride device, wherein the testing device comprises a direct current power supply, a first driving switch, a second driving switch, a third driving switch, a tested device, a first diode, a second diode, a load inductance, a first capacitor and a second capacitor; the device comprises a drive switch, a device to be tested, a DUT voltage detection unit, an inductance current detection unit, a voltage detection unit and a voltage detection unit. The testing method comprises the steps of determining testing requirements and testing modes, setting a switching time sequence of a driving switch in each testing stage, continuously sampling by using a voltage detection unit and a current detection unit, and determining the dynamic on-resistance of the tested device according to sampling current and voltage. The method solves the problem that the prior art cannot effectively evaluate the influence of high-voltage stress time on the dynamic on-resistance of the gallium nitride device in the state of resetting the prepositive charge, and can perform related tests in a single pulse mode and a continuous pulse mode according to test requirements.
Description
Technical Field
The invention belongs to the technical field of semiconductor device measurement, and particularly relates to a device and a method for testing dynamic on-resistance of a gallium nitride power device.
Background
With the continuous increase of the energy density requirements of the switching power supply market on equipment, gallium nitride semiconductor devices are beginning to be widely applied in the fields of consumer products, automobiles, industry and the like. Meanwhile, related testing methods and standards of gallium nitride devices are standardized, and it is important for semiconductor manufacturers to improve the product quality and reliability. Among them, the dynamic on-resistance evaluation of gallium nitride is one of the key points of the requirement of the specification, and there are mainly the following three reasons:
1. Dynamic on-resistance is a unique characteristic of gallium nitride devices, and is expressed as a phenomenon that the transient recoverable on-resistance of the devices is increased after the devices are subjected to high-pressure stress, and the related standardized test standard is still lacking at present. Because of the specificity of the test conditions required by the characteristics, the conventional test device and method for the silicon-based switching tube are not suitable for gallium nitride switching devices at present;
2. because the gallium nitride device production process is still in an immature stage compared with a silicon-based device at present, most manufacturers can use a GaN-on-Si process for cost consideration, so that defects, cracks and dislocation are generated in the epitaxial growth of a chip, and the defects, the cracks and the dislocation can cause the aggravation of the dynamic on-resistance of gallium nitride;
3. in switching power supply equipment applications, engineering personnel are required to provide accurate relevant specification parameters for design references according to semiconductor manufacturers. The accurate dynamic on-resistance parameter is known, and the method has great significance in the aspects of selecting device specifications, evaluating system loss, selecting switching frequency, determining equipment heat dissipation system requirements and the like.
Currently, a testing method based on a half-bridge type double-pulse structure is generally adopted in the industry to detect the dynamic on-resistance of a gallium nitride power device. Such a structure is described in patent publication No. CN115575713A, CN218099379U, et al. The detection method mainly has the following defects:
1. The high-voltage stress time of the tested device in the device is controlled by the interval time between the double pulses, however, due to the natural failure of the inductance current between the double pulses, the double pulse detection method cannot evaluate the dynamic on-resistance change of the tested device under the rated test current after long-time (more than millisecond) stress voltage;
2. The double pulse testing device causes the tested device to generate a charge trapping phenomenon under the action of high voltage stress before the beginning of a testing period, and the trapped charge is not reset and cleared before the testing, which can seriously affect the control variable in the dynamic on-resistance characteristic evaluation and further affect the reliability of the testing result. The charge reset can be realized by switching on the tested device after the power supply is connected and before the test period starts so that the trapped charge is released in the conduction channel;
3. The double pulse detection device cannot evaluate the performance of the tested device after continuous pulse break, and the performance is exactly where the tested device is mainly used. This is solved in patent CN116223916a, but the device requires multiple test power supplies, circuit elements and more complex control schemes.
Limitations of the existing testing device and testing method can lead to inaccurate characteristic evaluation of the dynamic on-resistance of the gallium nitride device, thereby affecting the reliability of the gallium nitride device in the switching power supply equipment.
Disclosure of Invention
The invention aims to overcome the defects of the prior art, and provides a testing device and a testing method for the dynamic on-resistance of a gallium nitride power device, which can more accurately evaluate the change of the dynamic on-resistance of gallium nitride caused by long-time high-voltage stress under the condition of clearing front charge, and can be used for evaluating and testing the characteristics of a single pulse mode and a continuous pulse mode.
The invention provides a testing device for dynamic on-resistance of a gallium nitride power device, which comprises a direct-current power supply, a first driving switch, a second driving switch, a third driving switch, a tested device, a first diode, a second diode, a load inductor, a first capacitor and a second capacitor;
The first driving switch is connected with the first diode in series to form a first bridge arm, the third driving switch is connected with the tested device in series to form a second bridge arm, the first bridge arm and the second bridge arm are connected in parallel to form a full-bridge circuit, and the positive pole and the negative pole of the direct current power supply are respectively connected with a high-side switch and a low-side switch of the full-bridge circuit;
And two ends of the second driving switch are respectively connected with the negative end of the load inductor and the negative electrode of the direct current power supply and are used for providing an additional charging bypass for inductor current initialization. And two ends of the second diode are respectively connected with the negative end of the load inductor and the neutral point of the second bridge arm and are used for decoupling the inductor voltage and the stress voltage of the tested device.
Preferably, the first capacitor and the second capacitor are connected in parallel with the direct current power supply and are used for filtering and providing the function of high-frequency switching current.
Preferably, the first driving switch, the second driving switch, the third driving switch and the tested device are all provided with an isolation type driving control module, and the isolation type driving control module is used for controlling the on-off of the driving switch or the tested device.
Preferably, the device further comprises DUT voltage detection units which are arranged at two ends of the tested device in parallel;
The DUT voltage detection unit comprises a voltage probe with a clamping function and a high-voltage probe, wherein the clamping voltage probe and the high-voltage probe are respectively used for detecting dynamic voltage of a device to be detected in an on state and high-voltage stress of the device to be detected in an off state in real time.
Preferably, the apparatus further comprises an inductor current detection unit disposed in series between the load inductor and the second diode;
The inductance current detection unit is used for detecting load inductance current and detected device current in a state of being connected with the load inductance in series in real time.
The second object of the present invention is to provide a testing method of the testing device for dynamic on-resistance of gallium nitride power device, comprising the following steps:
S1, determining a test requirement and a test mode;
S2, setting a first driving switch, a second driving switch, a third driving switch and a switching time sequence of the tested device in each test stage according to the test requirement and the test mode determined in the step S1;
S3, according to the switching time sequence of each test stage set in the step S2, respectively and sequentially operating the DUT charge reset period, the DUT charge capturing period and the DUT charge escape period, and when the DUT charge escape period is entered, respectively and continuously sampling the dynamic voltage and the current of the tested device by using the DUT voltage detection unit and the inductance current detection unit to obtain the conducting voltage and the conducting current of the tested device;
S4, determining the dynamic on-resistance of the tested device according to the on-voltage and the on-current obtained in the step S3.
Preferably, in step S1, the test requirements include a high voltage stress magnitude, a high voltage stress time, a test current amplitude and a test switching frequency, and the test modes include a single pulse mode and a continuous pulse mode.
Preferably, in step S2, the test phase includes a DUT charge reset period, a DUT charge trapping period, and a DUT charge escape period.
Preferably, in step S2, when the test mode determined in step S1 is a single pulse mode, the switching timings of the first driving switch, the second driving switch, the third driving switch, and the device under test in each test stage are set as follows:
the DUT charge resetting period is to turn on the tested device and turn off the first driving switch, the second driving switch and the third driving switch;
The DUT charge capturing period is to turn on the third driving switch and turn off the tested device, and the first driving switch and the second driving switch are still kept off;
turning on the first drive switch and the second drive switch, and keeping the third drive switch on and the device to be tested off;
DUT charge escape period, namely, a device to be tested is turned on, and the first driving switch, the second driving switch and the third driving switch are turned off.
Preferably, in step S2, when the test mode determined in step S1 is a continuous pulse mode, the switching timings of the first driving switch, the second driving switch, the third driving switch, and the device under test in each test stage are set as follows:
the DUT charge resetting period is to turn on the tested device and turn off the first driving switch, the second driving switch and the third driving switch;
keeping the tested device on, and turning on the first drive switch, wherein the second drive switch and the third drive switch are still kept off;
Keeping the second drive switch off, and continuously switching on and off the first drive switch, the third drive switch and the tested device under test switching frequency, wherein the PWM switching signal of the tested device is identical to the first drive switch, is complementary to the third drive switch, and leaves proper dead time according to the specification of the device, the dead time is determined by the switching characteristic of the tested device, and the PWM duty ratio is set to 0.5;
DUT charge escape period, namely, a device to be tested is turned on, and the first driving switch, the second driving switch and the third driving switch are turned off.
Compared with the prior art, the invention has the beneficial effects that:
(1) According to the invention, by controlling the first driving switch and the second driving switch, an additional current bypass is provided for inductor charge and discharge, the problem that the high-voltage stress evaluation time is limited due to natural attenuation of inductor current between double pulses in a double-pulse test method is solved, so that the dynamic on-resistance can be tested under long-time high-voltage stress, and the method has great significance for understanding the maximum dynamic on-resistance increment, saturated charge trapping and device defect degree of a device.
(2) The invention ensures that the tested device can be turned on in the induction current initialization period by applying the full bridge structure, resets the trapped charge by the device conduction channel, ensures that the tested device carries out the dynamic conduction resistance test under the single pulse and continuous pulse modes in the state of resetting the preposed charge, and ensures the accuracy of the initial test condition and the control variable.
(3) According to the invention, the full-bridge structure is adopted to continuously turn on and off the tested device under the preset switching frequency and time, so that the change condition of the dynamic on-resistance of the tested device after continuous operation under different switching voltages, switching currents and switching frequencies can be observed. And simultaneously, a single energy supply power supply and a simpler control method are used for evaluating the characteristics under the two modes of single pulse and continuous pulse, the method has the advantages of low cost and convenient use, and the result has positive reference significance for both semiconductor manufacturers and switch power supply equipment manufacturers.
Drawings
Fig. 1 is a schematic structural diagram of a testing device for dynamic on-resistance of a gallium nitride power device according to an embodiment of the present invention;
FIG. 2 is a timing waveform diagram of related signals of the test method in the single pulse mode according to the embodiment of the present invention;
FIG. 3 is a timing waveform diagram of related signals of the test method in the continuous pulse mode according to the embodiment of the present invention;
FIG. 4 is a graph showing an example of a waveform of a test current of 10A, a high-voltage stress of 400V, and a high-voltage stress time of 10 μs in a single pulse mode according to the test method of the present invention;
fig. 5 is a graph of evaluation results of the test method provided by the embodiment of the invention under different high-voltage stress time for the dynamic on-resistance of the tested device GS66516T in the single-pulse mode;
FIG. 6 is a graph showing an example of a waveform of a test method according to an embodiment of the present invention under a continuous pulse mode, wherein the high voltage stress is 400V, the test current is 10A, the switching frequency is 100kHz, and the high voltage stress time is 100 μs;
Fig. 7 is a graph showing the evaluation results of the test method provided by the embodiment of the invention under different continuous pulse times for the dynamic on-resistance of the tested device GS66516T under the continuous pulse mode.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Example 1
As shown in FIG. 1, the embodiment of the invention provides a device for testing dynamic on-resistance of a GaN power device, which specifically comprises a DC power supply, a first driving switch S 1, a second driving switch S 2, a third driving switch S 3, Tested device S 4, first diode D 1, second diode D 2, load inductance L, The first driving switch S 1 is connected with the first diode D 1 in series to form a first bridge arm, the third driving switch S 3 is connected with the tested device S 4 in series to form a second bridge arm, the first bridge arm and the second bridge arm are connected in parallel to form a full-bridge circuit, and the positive pole and the negative pole of the direct current power supply are respectively connected with a high-side switch and a low-side switch of the full-bridge circuit. And the positive end of the load inductor is connected with the neutral point of the first bridge arm. The testing device additionally incorporates a second drive switch S 2 and a second diode D 2 on the basis of a full bridge circuit. And two ends of the second driving switch S 2 are respectively connected with the negative end of the load inductor L and the negative electrode of the direct-current power supply, so as to provide an additional current bypass for initializing the inductor current. And two ends of the second diode D 2 are respectively connected with the negative end of the load inductor L and the neutral point of the second bridge arm, so that the effect of decoupling the inductor voltage and the stress voltage of the tested device is achieved. The first capacitor C 1 and the second capacitor C 2 are connected with the direct-current power supply in parallel, and function in filtering and providing high-frequency switching current.
The first driving switch S 1, the second driving switch S 2, the third driving switch S 3 and the tested device S 4 are respectively provided with an isolated driving control module, the first driving switch S 1, the second driving switch S 2, the third driving switch S 3 and the tested device S 4 respectively correspond to the isolated driving control module 1, the isolated driving control module 2, the isolated driving control module 3 and the isolated driving control module 4, and the isolated driving control module 1, the isolated driving control module 2, the isolated driving control module 3 and the isolated driving control module 4 are respectively used for controlling the on-off of the first driving switch S 1, the second driving switch S 2, the third driving switch S 3 and the tested device S 4.
The device also comprises DUT voltage detection units which are arranged at two ends of the tested device S 4 in parallel and an inductive current detection unit which is arranged between the load inductor L and the second diode D 2 in series;
The DUT voltage detection unit comprises a voltage probe with a clamping function and a high-voltage probe, wherein the clamping voltage probe and the high-voltage probe are respectively used for detecting dynamic voltage of a device to be detected in an on state and high-voltage stress of the device to be detected in an off state in real time. The purpose of using the clamp voltage probe to test the turn-on voltage is to reduce sampling quantization errors caused by overlarge voltage peak value of the tested device in the switching process.
The inductance current detection unit is used for detecting load inductance current and detected device current in a state of being connected with the load inductance in series in real time.
The direct current power supply is a voltage-stabilized power supply with rated value capable of meeting the high-voltage stress and test current amplitude requirements of the tested device.
In the embodiment of the invention, the first driving switch S 1 and the second driving switch S 2 can be silicon-based MOSFET switch tubes, so that the control of inductance current is realized, and the third driving switch S 3 uses gallium nitride devices which are the same as the tested device S 4, so that the uniformity of bridge arm switch energy is ensured. The first diode D 1 and the second diode D 2 preferably use patch-type silicon carbide schottky diodes, which minimize parasitic capacitance and stray inductance in the circuit, reduce current and voltage oscillations during switching, and increase the effective area for dynamic on-resistance sampling.
Example 2
The embodiment of the invention provides a testing method for dynamic on-resistance of a gallium nitride power device based on a testing device provided in embodiment 1, which specifically comprises the following steps:
S1, determining a test requirement and a test mode, wherein the test requirement comprises high-voltage stress magnitude, high-voltage stress time, test current amplitude and test switching frequency, and the test mode comprises a single pulse mode and a continuous pulse mode;
S2, according to the test requirements and the test modes determined in the step S1, the switch time sequences of the first driving switch S 1, the second driving switch S 2, the third driving switch S 3 and the tested device S 4 in each test stage are set. The test phase includes a DUT charge reset period, a DUT charge trapping period, and a DUT charge escape period;
As shown in fig. 2, when the test mode determined in step S1 is a single pulse mode, the switching timings of the first driving switch S 1, the second driving switch S 2, the third driving switch S 3, and the device under test S 4 in each test stage are set as follows:
DUT charge reset period, namely, a device under test S 4 is turned on, a first driving switch S 1, a second driving switch S 2 and a third driving switch S 3 are turned off, at the moment, the device under test enters the charge reset period, and charges captured in device defects are released and cleared through a conduction channel. This stage suggests leaving a long enough charge initialization time to guarantee test accuracy according to device specifications;
The DUT charge trapping period is that the third driving switch S 3 is turned on, the tested device S 4 is turned off, the first driving switch S 1 and the second driving switch S 2 are still turned off, at the moment, the tested device enters the charge trapping period, and charges which do not realize energy level transition in the period are trapped in device defects and accumulated and increased continuously by time. The time of the high-pressure stress period is determined by the test requirement;
the first driving switch S 1 and the second driving switch S 2 are turned on, the third driving switch S 3 is kept on, the tested device S 4 is turned off, the measuring circuit enters a current initialization stage, the direct current power supply charges the load inductance, and the load current is increased linearly. During this time, the current initialization phase still belongs to the charge trapping phase, since the device under test is still under high voltage stress.
DUT charge escape period: turn on device under test S 4, turn off first drive switch S 1, second drive switch S 2, and third drive switch S 3. The load current freewheels through the closed loop of the first diode D 1, the second diode D 2 and the device under test S 4. At this point, the device under test S 4 is in the charge escape period, and the charge trapped during the DUT charge trapping period is released through the conduction channel. And in the period, the voltage detection unit and the current detection unit are used for sampling the conducting voltage and the conducting current of the tested device.
As shown in fig. 3, when the test mode determined in step S1 is a continuous pulse mode, the switching timings of the first driving switch S 1, the second driving switch S 2, the third driving switch S 3, and the device under test S 4 in each test stage are set as follows:
DUT charge reset period, namely, a device under test S 4 is turned on, a first driving switch S 1, a second driving switch S 2 and a third driving switch S 3 are turned off, at the moment, the device under test enters the charge reset period, and charges captured in device defects are released and cleared through a conduction channel. This stage suggests leaving a long enough charge initialization time to guarantee test accuracy according to device specifications;
The measured device S 4 is kept on, the first driving switch S 1 is turned on, the second driving switch S 2 and the third driving switch S 3 are still kept off, the measuring circuit enters a current initialization stage, the direct current power supply charges a load inductance, and the load current is increased linearly. The duration of the current initialization phase is determined by the inductance size and the test requirements. And after the load current reaches the required amplitude, the initialization is finished. During the period, the conduction channel of the device to be tested is in an open state, so that no charge is captured;
The DUT charge trapping period comprises the steps of keeping a second driving switch S 2 to be turned off and continuously turning on and off a first driving switch S 1, a third driving switch S 3 and a tested device S 4 at a test switching frequency, wherein a PWM switching signal of the tested device S 4 is identical to a PWM switching signal of the first driving switch S 1, is complementary to the third driving switch S 3, leaves proper dead time according to device specifications, and has a duty ratio set to be 0.5, and the time length of the tested device is determined by the test requirement.
DUT charge escape period, namely a device to be tested S 4 is turned on, a first driving switch S 1, a second driving switch S 2 and a third driving switch S 3 are turned off, the device to be tested S 4 enters the charge escape period, and the on-voltage and current sampling method of the device to be tested in the charge escape period is the same as that of a single pulse mode.
The on-voltage sampling of the device under test S 4 in the DUT charge escape period in the single pulse mode and the continuous pulse mode should use a voltage probe with a clamping function in the DUT voltage detection unit to reduce the sampling quantization error caused by the overlarge voltage peak value of the device under test S 4 in the switching process. Since the load inductance L and the device under test S 4 are in a series state, the inductance current is the same as the conduction current of the device under test S 4, and the current sampling of the device under test S 4 can be performed by the inductance current detecting unit. Because most gallium nitride devices are packaged by adopting a patch type, the current sampling method can reduce switch current and voltage oscillation caused by stray inductance introduced by setting a device current detection link, thereby improving the accuracy of sampling and dynamic on-resistance evaluation and reducing the design difficulty of a PCB and the use cost of the device.
S3, according to the switching time sequence of each test stage set in the step S2, respectively and sequentially operating the DUT charge reset period, the DUT charge capturing period and the DUT charge escape period, and when the DUT charge escape period is entered, continuously sampling the dynamic voltage and current of the tested device S 4 by using the DUT voltage detection unit and the inductance current detection unit respectively to obtain the conducting voltage and the conducting current of the tested device S 4. The length of the continuous sampling time can refer to the switching period of the tested device in practical application;
S4, determining the dynamic on-resistance of the tested device S 4 according to the on-voltage and the on-current obtained in the step S3. To evaluate the dynamic on-resistance of a device under test over a charge escape period, it is necessary to map the dynamic change in resistance value over the period from the ratio of current to voltage sampled continuously.
The test performance of the test device and the test method provided by the embodiment of the invention is verified.
In practical circuit testing, the first driving switch S 1 and the second driving switch S 2 are MOSFET (IPB 65R110CFD7 650V/22A) from Infraria, and the third driving switch unit S 3 and the tested device S 4 are GaN (GS 66516T 650V/60A) from GAN SYSTEMS. The first diode D 1 and the second diode D 2 are silicon carbide diodes from Cree (C4D10120E1.2kV/33A). The isolation type drive control module selects Si8271 isolation grid type drive IC from Silicon Labs as a control chip. The clamp voltage probe of the DUT voltage detection unit employs a clamp voltage probe (CLP 1500V15A 1) from Springburo.
The test method provided by the invention has the advantages that under the single pulse mode, the test current is 10A, the high-voltage stress is 400V, An example of the measured waveform at a high voltage stress time of 10 μs is shown in fig. 4, V gs1 refers to the gate voltage of the first driving switch S 1, V gs4 refers to the gate voltage of the device under test S 4, V ds4 refers to the voltage across the device under test S 4 observed by the high voltage probe, and V ds4_Clamp refers to the voltage across the device under test S 4 observed by the clamp voltage probe. as can be seen from fig. 4, prior to t 1, the test is in DUT charge reset phase, gate voltage V gs4 of device under test S 4 is 6V, device under test S 4 is on, and the front charge is cleared. By t 1, the test enters the DUT charge trapping period, the gate voltage V gs4 of the tested device S 4 is 0V, the tested device S 4 is turned off, the third driving switch S 3 is turned on, the voltage V ds4 at two ends of the tested device S 4 is 400V of the direct current power supply voltage, and the clamp voltage V ds4_Clamp is 2.5V of the preset value. By t 2, the test enters the inductor current initialization time, the first drive switch S 1 and the second drive switch S 2 are turned on, the inductor starts to charge, and the inductor current I L reaches 10A at t 3. At t 3, the charge trapping period of the device under test S 4 reaches the preset time of 10 microseconds, the test current reaches the preset value of 10A, the device under test S 4 is turned on, the test enters the DUT charge escape period, the conduction voltage V ds4_Clamp and the inductance current I L of the device under test S 4 are sampled, the dynamic conduction resistance ratio is calculated, at the moment, the device under test S 4 is connected in series with the load inductance L, and the inductance current I L is equal to the conduction current of the device under test.
Fig. 5 is a graph of evaluation results of the test method provided by the invention under different high-voltage stress times for the dynamic on-resistance of the tested device GS66516T in the single-pulse mode. The test requirement for this embodiment is a high stress time of 100 microseconds to 100 milliseconds, a test current of 10A, and a high stress of 100V to 400V. Fig. 5 shows the ratio of the dynamic on-resistance R ds (1 μs) of the device under test S 4 to the rated resistance R dc at a charge escape period of 1 μs. As can be seen from the results of fig. 5, the dynamic on-resistance does not increase more than 5% compared to the rated resistance when the high-voltage stress time is from 100 microseconds to 1 millisecond and the stress voltage is 400V, the dynamic on-resistance increases by about 24% when the stress time is from 1 millisecond to 10 milliseconds and the stress voltage is 400V, and the proportion of the dynamic on-resistance increases compared to the rated resistance gradually decreases when the stress time is from 40 milliseconds to 100 milliseconds and the stress voltage is 400V, which indicates that the amount of trapped charges may have approached the saturation level. In addition, the dynamic on-resistance of the tested device also shows similar trend for stress voltages of 200V and 300V, and the dynamic on-resistance is slower compared with the increase rate under the high-voltage stress time when the stress voltage is 100V. Semiconductor manufacturers may refer to such embodiment test results to improve the epitaxial process, product quality and reliability.
FIG. 6 shows a test method according to an embodiment of the present invention, in a continuous pulse mode, having a high voltage stress of 400V, a test current of 10A, a switching frequency of 250kHz, In fig. 6, V gs1 refers to the gate voltage of the first driving switch S 1, V gs4 refers to the gate voltage of the device under test S 4, V ds4 refers to the voltage across the device under test S 4 observed by the high voltage probe, and V ds4_Clamp refers to the voltage across the device under test S 4 observed by the clamp voltage probe. As can be seen from fig. 6, before t 1, the test is in DUT charge reset phase, the gate voltage V gs4 of the device under test S 4 is 6V, the device under test S 4 is turned on, and the front charge is cleared. In the interval t 0～t1, the test enters the current initialization stage, the first driving switch S 1 is turned on, the gate voltage V gs1 is 6V, the inductor is charged, and the current increases to 10A. In the interval t 1～t2, the test enters the DUT charge trapping period, the circuit works in a full-bridge constant current source mode, the switching frequency is 250kHz, the peak-to-peak value of the switching voltage V ds4 of the tested device S 4 is 400V of the direct current power supply voltage, and the average value of the inductance current I L is 10A. At t 3, the charge trapping period of the device under test S 4 reaches a preset time of 100 microseconds, the device under test S 4 is turned on, the DUT charge escape period is tested, the turn-on voltage V ds4_Clamp and the inductor current I L of the device under test S 4 are sampled, the dynamic turn-on resistance ratio is calculated, at this time, the device under test S 4 is connected in series with the load inductor, and the inductor current I L is equal to the turn-on current of the device under test S 4.
Fig. 7 is a graph showing the evaluation results of the test method according to the present invention for the dynamic on-resistance of the tested device GS66516T under the continuous pulse mode under different continuous switching times. The test requirement of this embodiment is a high stress time of 100 microseconds to 100 milliseconds, a test current of 10A, a high voltage stress of 100V to 400V, and a switching frequency of 250kHz. Fig. 7 shows the ratio of the measured device dynamic on-resistance R ds (1 μs) to the rated resistance R dc at a charge escape period of 1 μs. As can be seen from a comparison of the results of fig. 5, the dynamic on-resistance of the device under test S 4 increases more significantly at the same charge trapping time after continuous operation, which suggests that the switching process results in a more pronounced charge trapping phenomenon than normal high-voltage stress, which becomes more pronounced on a time scale of 10 ms to 100 ms. The switching power supply equipment manufacturer can select proper device specifications, estimate system loss, define the heat dissipation system requirements of the equipment, and the like with reference to the test results of such embodiments.
Although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made therein without departing from the spirit and scope of the invention as defined by the appended claims and their equivalents.
Claims (5)
1. The testing method is characterized by being realized by a testing device of the dynamic on-resistance of the gallium nitride power device, wherein the testing device of the dynamic on-resistance of the gallium nitride power device comprises a direct current power supply, a first driving switch, a second driving switch, a third driving switch, a tested device, a first diode, a second diode, a load inductor, a first capacitor and a second capacitor;
The first driving switch and the first diode are connected in series to form a first bridge arm, the third driving switch and the tested device are connected in series to form a second bridge arm, the first bridge arm and the second bridge arm are connected in parallel to form a full-bridge circuit, and the positive pole and the negative pole of the direct current power supply are respectively connected with a high-side switch and a low-side switch of the full-bridge circuit;
one end of the load inductor is connected with the neutral point of the first bridge arm;
two ends of the second driving switch are respectively connected with the other end of the load inductor and the negative electrode of the direct current power supply and are used for providing an additional charging bypass for inductor current initialization;
Two ends of the second diode are respectively connected with the other end of the load inductor and a second bridge arm neutral point and are used for decoupling the inductor voltage and the stress voltage of the tested device;
The first capacitor and the second capacitor are connected in parallel with the direct current power supply and are used for filtering and providing high-frequency switching current;
the method for testing the dynamic on-resistance of the gallium nitride power device comprises the following steps:
S1, determining a test requirement and a test mode;
the test requirement comprises high-voltage stress magnitude, high-voltage stress time, test current amplitude and test switching frequency, and the test mode comprises a single pulse mode and a continuous pulse mode;
S2, setting a first driving switch, a second driving switch, a third driving switch and a switching time sequence of the tested device in each test stage according to the test requirement and the test mode determined in the step S1;
the test phase includes a DUT charge reset period, a DUT charge trapping period, and a DUT charge escape period;
When the test mode determined in step S1 is a single pulse mode, the switching sequences of the first driving switch, the second driving switch, the third driving switch and the device under test in each test stage are set as follows:
the DUT charge resetting period is to turn on the tested device and turn off the first driving switch, the second driving switch and the third driving switch;
The DUT charge capturing period is to turn on the third driving switch and turn off the tested device, and the first driving switch and the second driving switch are still kept off;
turning on the first drive switch and the second drive switch, and keeping the third drive switch on and the device to be tested off;
The DUT charge escape period is that a device to be tested is turned on, and the first driving switch, the second driving switch and the third driving switch are turned off;
S3, according to the switching time sequence of each test stage set in the step S2, respectively and sequentially operating the DUT charge reset period, the DUT charge capturing period and the DUT charge escape period, and when the DUT charge escape period is entered, respectively and continuously sampling the dynamic voltage and the current of the tested device by using the DUT voltage detection unit and the inductance current detection unit to obtain the conducting voltage and the conducting current of the tested device;
S4, determining the dynamic on-resistance of the tested device according to the on-voltage and the on-current obtained in the step S3.
2. The method for testing the dynamic on-resistance of the gallium nitride power device according to claim 1, wherein the first driving switch, the second driving switch, the third driving switch and the device to be tested are all provided with an isolated driving control module, and the isolated driving control module is used for controlling the on-off of the driving switch or the device to be tested.
3. The method for testing the dynamic on-resistance of the gallium nitride power device according to claim 1, wherein the device further comprises DUT voltage detection units arranged in parallel at two ends of the device under test;
the DUT voltage detection unit comprises a clamping voltage probe with a clamping function and a high-voltage probe, wherein the clamping voltage probe and the high-voltage probe are respectively used for detecting dynamic voltage of a device to be detected in an on state and high-voltage stress of the device to be detected in an off state in real time.
4. The method for testing the dynamic on-resistance of the gallium nitride power device according to claim 1, wherein the device further comprises an inductor current detection unit arranged in series between the load inductor and the second diode;
the inductive current detection unit is used for detecting load inductive current and detected device current in real time.
5. The method for testing the dynamic on-resistance of the gallium nitride power device according to claim 1, wherein in step S2, when the test mode determined in step S1 is a continuous pulse mode, the switching timings of the first driving switch, the second driving switch, the third driving switch and the device under test in each test stage are set as follows:
the DUT charge resetting period is to turn on the tested device and turn off the first driving switch, the second driving switch and the third driving switch;
Keeping the tested device on, and turning on the first drive switch, wherein the second drive switch and the third drive switch are still kept off;
Keeping the second drive switch off, and continuously switching on and off the first drive switch, the third drive switch and the tested device under test switching frequency, wherein the PWM switching signal of the tested device is the same as that of the first drive switch, is complementary with the third drive switch, and leaves proper dead time according to the specification of the device, and the duty ratio is set to be 0.5;
DUT charge escape period, namely, a device to be tested is turned on, and the first driving switch, the second driving switch and the third driving switch are turned off.
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| CN116184149A (en) * | 2023-01-30 | 2023-05-30 | 北京华峰测控技术股份有限公司 | Power device electric stress impact circuit, control method and multi-station circuit |
| CN116224002A (en) * | 2022-12-19 | 2023-06-06 | 润新微电子(大连)有限公司 | A GaN transistor drain-source transient voltage test circuit and method |
| CN117310434A (en) * | 2023-11-28 | 2023-12-29 | 浙江大学杭州国际科创中心 | Dynamic on-resistance test circuit for gallium nitride high electron mobility transistor |
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| KR20160105020A (en) * | 2015-02-27 | 2016-09-06 | 한양대학교 에리카산학협력단 | Semiconductor Device, Method and System for Testing the Semiconductor Device |
| US11448686B2 (en) * | 2019-09-18 | 2022-09-20 | Texas Instruments Incorporated | RDSON/dRON measurement method and circuit for high voltage HEMTs |
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| CN116184149A (en) * | 2023-01-30 | 2023-05-30 | 北京华峰测控技术股份有限公司 | Power device electric stress impact circuit, control method and multi-station circuit |
| CN117310434A (en) * | 2023-11-28 | 2023-12-29 | 浙江大学杭州国际科创中心 | Dynamic on-resistance test circuit for gallium nitride high electron mobility transistor |
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