CN118572003B - Light-emitting diode epitaxial wafer and preparation method thereof, and light-emitting diode - Google Patents

Abstract

The invention discloses a light-emitting diode epitaxial wafer, a preparation method thereof and a light-emitting diode, and relates to the field of semiconductor photoelectric devices. The light-emitting diode epitaxial wafer sequentially comprises a substrate, a buffer layer, an undoped GaN layer, an N-type GaN layer, a multiple quantum well layer, an electron blocking layer and a P-type GaN layer; the multi-quantum well layer sequentially comprises a first multi-quantum well layer, a last well layer and a last barrier layer, wherein the first multi-quantum well layer comprises a quantum well layer and a quantum barrier layer, the quantum well layer and the last well layer are InGaN quantum well layers, and the quantum barrier layer is a GaN quantum barrier layer; the final barrier layer comprises an Al _xGa_1‑x N layer, an In _yGa_1‑y N layer, an In _zGa_1‑z N layer and a GaN layer which are sequentially stacked; x is 0.05-0.3, y is 0.01-0.1, z is 0.01-0.1, and z > y; the electron blocking layer is a beta-Ta ₂O₅ layer; the P-type GaN layer comprises a first P-type GaN layer, a P-type In _αGa_1‑α N layer and a second P-type GaN layer which are sequentially stacked, and alpha is 0.08-0.15. By implementing the invention, the luminous efficiency of the light-emitting diode under each current density can be improved.

Description

Light-emitting diode epitaxial wafer and preparation method thereof, and light-emitting diode

Technical Field

The invention relates to the field of semiconductor optoelectronic devices, and in particular to a light emitting diode epitaxial wafer and a preparation method thereof, and a light emitting diode.

Background Art

GaN-based light-emitting diodes generally use InGaN-GaN heterojunction as the quantum well region. It has advantages such as high luminous efficiency and is currently the most widely used LED. However, there are still some phenomena that limit its performance improvement. One of them is the phenomenon that the luminous efficiency decreases with the increase of the injected current, which is generally called the problem of Efficiency Droop. Studies have shown that Efficiency Droop has a strong correlation with leakage electrons. Since P-type AlGaN is generally used as the electron blocking layer in GaN-based light-emitting diodes, the lattice mismatch between the barrier layer (GaN) and the electron blocking layer will form a polarization electric field, generate positive charges, and then reduce the barrier of P-type AlGaN, resulting in electron leakage. The commonly used method is to replace the last barrier layer with a stacked structure of GaN and p-type InGaN, but this structure will cause Mg to diffuse into other quantum well layers, reducing the crystal quality of other quantum well layers. If there is too much In in p-type InGaN, it will cause the barrier to be too low, making it difficult to confine holes and electrons to the active area, which will also reduce the luminous efficiency.

Summary of the invention

The technical problem to be solved by the present invention is to provide a light emitting diode epitaxial wafer and a preparation method thereof, which can improve the light emitting efficiency of the light emitting diode under different light emitting currents.

In order to solve the above problems, the present invention discloses a light-emitting diode epitaxial wafer, which comprises a substrate, a buffer layer, a non-doped GaN layer, an N-type GaN layer, a multi-quantum well layer, an electron blocking layer and a P-type GaN layer sequentially stacked on the substrate;

The multi-quantum well layer comprises a first multi-quantum well layer, a final well layer and a final barrier layer sequentially stacked on the N-type GaN layer, the first multi-quantum well layer is a periodic structure formed by alternating stacking of quantum well layers and quantum barrier layers, the quantum well layer and the final well layer are both InGaN quantum well layers, and the quantum barrier layer is a GaN quantum barrier layer;

The final barrier layer comprises an _{AlxGa1 -xN} layer, an _{InyGa1 -yN} layer, an _{InzGa1 -zN} layer and a GaN layer sequentially stacked on the final well layer; wherein the value range of x is 0.05-0.3, the value range of y is 0.01-0.1, the value range of z is 0.01-0.1, and z>y;

The electron blocking layer is a β-Ta ₂ O ₅ layer;

The P-type GaN layer includes a first P-type GaN layer, a P-type In _α Ga _1-α N layer and a second P-type GaN layer which are sequentially stacked on the electron blocking layer, wherein the value range of α is 0.08-0.15.

As an improvement of the above technical solution, the thickness of the _{AlxGa1 -xN} layer is 3nm-8nm, and the value range of x is 0.1-0.2; and/or

The thickness of the In _y Ga _1-y N layer is 1 nm to 3 nm, and the value range of y is 0.02 to 0.04; and/or

The thickness of the In _z Ga _1-z N layer is 1 nm to 3 nm, and the value range of z is 0.05 to 0.1; and/or

The thickness of the GaN layer is 2nm~6nm.

As an improvement of the above technical solution, the thickness of the electron blocking layer is 20nm~50nm; and/or

The thickness of the first P-type GaN layer is 20 nm to 100 nm, and the P-type doping concentration is 1×10 ¹⁹ cm ^-3 to 1×10 ²⁰ cm ^-3 ; and/or

The thickness of the P-type In _α Ga _1-α N layer is 10 nm to 30 nm, and the P-type doping concentration is 1×10 ¹⁷ cm ^-3 to 1×10 ¹⁹ cm ^-3 ; and/or

The thickness of the second P-type GaN layer is 50 nm to 150 nm, and the P-type doping concentration is 1×10 ²⁰ cm ^-3 to 1×10 ²¹ cm ^-3 .

As an improvement of the above technical solution, the thickness of the _{AlxGa1 -xN} layer is 1.5 to 3 times the thickness of the _{InyGa1 -yN} layer.

As an improvement of the above technical solution, the thickness of the GaN layer is 1.2 to 2 times the thickness of the In _z Ga _1-z N layer.

As an improvement of the above technical solution, the In component ratio in the quantum well layer and the final well layer is 0.1-0.2, and the thickness thereof is 3nm-5nm;

The thickness of the quantum barrier layer is 5nm-15nm.

Correspondingly, the present invention also discloses a method for preparing a light-emitting diode epitaxial wafer, which is used to prepare the above-mentioned light-emitting diode epitaxial wafer, and comprises:

Providing a substrate, and sequentially growing a buffer layer, an N-type GaN layer, a multi-quantum well layer, an electron blocking layer, and a P-type GaN layer on the substrate;

The multi-quantum well layer comprises a first multi-quantum well layer, a final well layer and a final barrier layer sequentially stacked on the N-type GaN layer, the first multi-quantum well layer is a periodic structure formed by alternating stacking of quantum well layers and quantum barrier layers, the quantum well layer and the final well layer are both InGaN quantum well layers, and the quantum barrier layer is a GaN quantum barrier layer;

The final barrier layer comprises an _{AlxGa1 -xN} layer, an _{InyGa1 -yN} layer, an _{InzGa1 -zN} layer and a GaN layer sequentially stacked on the final well layer; wherein the value range of x is 0.05-0.3, the value range of y is 0.01-0.1, the value range of z is 0.01-0.1, and z>y;

The electron blocking layer is a β-Ta ₂ O ₅ layer;

The P-type GaN layer includes a first P-type GaN layer, a P-type In _α Ga _1-α N layer and a second P-type GaN layer which are sequentially stacked on the electron blocking layer, wherein the value range of α is 0.08-0.15.

As an improvement of the above technical solution, the growth temperature of the quantum well layer and the final well layer is 740° C. to 820° C., and the growth pressure is 100 torr to 300 torr; and/or

The growth temperature of the quantum barrier layer and the final barrier layer is 850° C. to 950° C., and the growth pressure is 100 torr to 300 torr; and/or

The growth temperature of the electron blocking layer is 800° C. to 900° C., and the growth pressure is 10 torr to 100 torr; and/or

The growth temperature of the first P-type GaN layer and the second P-type GaN layer is 900° C. to 1000° C., and the growth pressure is 100 torr to 500 torr; and/or

The growth temperature of the P-type In _α Ga _1-α N layer is 750° C. to 850° C., and the growth pressure is 100 torr to 500 torr.

As an improvement of the above technical solution, after the growth of the electron blocking layer is completed, annealing is performed at 900° C. to 950° C. in air or oxygen atmosphere for 10 min to 30 min.

Correspondingly, the present invention also discloses a light emitting diode, which includes the light emitting diode epitaxial wafer mentioned above.

The implementation of the present invention has the following beneficial effects:

In the light-emitting diode epitaxial wafer of the present invention, first, the _{AlxGa1 -xN} layer, _{InyGa1 -yN} layer, _{InzGa1 -zN} layer and GaN layer stacked in sequence are used as the last barrier layer, and the _{AlxGa1 -xN} layer- _{InyGa1 -yN} layer interface and the _{InzGa1 -zN} layer-GaN layer interface will generate polarization electric fields due to the polarization effect, thereby generating negative charges at the interface, which is convenient for consuming electrons and reduces the probability of electron escape. Furthermore, Mg doping is not introduced into the last barrier layer of the present invention, and the quantum well layer structure is not destroyed, thereby ensuring high luminous efficiency at a lower current density. Secondly, a β-Ta ₂ O ₅ layer is introduced on the GaN layer as an electron blocking layer, and the lattice mismatch between the GaN (0001) plane and the 010 crystal phase of β-Ta ₂ O ₅ is less than 3%, so the last barrier layer has a very weak effect on the electron blocking layer, and the band gap width of β-Ta ₂ O ₅ reaches about 4.4eV. The combination of the two makes the electron blocking layer have a good electron blocking effect. Thirdly, the P-type GaN layer of the present invention includes a first P-type GaN layer, a P-type In _α Ga _1-α N layer and a second P-type GaN layer stacked in sequence, and the P-type In _α Ga _1-α N layer with a lower barrier can play a role in storing holes, and the heterojunction formed by the first P-type GaN layer, the P-type In _α Ga _1-α N layer and the second P-type GaN layer can effectively accelerate holes and improve the efficiency of hole injection into the multi-quantum well layer. In summary, the light-emitting diode epitaxial wafer of the present invention can effectively improve the luminous efficiency under various current densities.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a schematic diagram of the structure of a light emitting diode epitaxial wafer according to an embodiment of the present invention;

FIG. 2 is a flow chart of a method for preparing a light emitting diode epitaxial wafer according to an embodiment of the present invention.

DETAILED DESCRIPTION

In order to make the purpose, technical solutions and advantages of the present invention more clear, the present invention is further described in detail below.

Referring to FIG1 , the present invention discloses a light emitting diode epitaxial wafer, which includes a substrate 100, a buffer layer 200, a non-doped GaN layer 300, an N-type GaN layer 400, a multi-quantum well layer 500, an electron blocking layer 600, and a P-type GaN layer 700, which are sequentially stacked on the substrate 100. The multi-quantum well layer 500 includes a first multi-quantum well layer 510, a final well layer 520, and a final barrier layer 530 sequentially stacked on the N-type GaN layer 400; the first multi-quantum well layer 510 is a periodic structure composed of quantum well layers 511 and quantum barrier layers 512 alternately stacked. The final barrier layer 530 includes an _{AlxGa1 -xN} layer 531, an _{InyGa1 -} yN layer 532, an _InzGa1 -zN layer 533 and a GaN layer 534 which are sequentially stacked on the final well layer 520. Based on the final barrier layer 530, firstly, the _{AlxGa1 -xN layer} 531 and the _{InyGa1 -yN} layer 532 with a higher lattice mismatch are introduced, and the concentration of the interface polarization charge is higher, which can more effectively prevent electron leakage. Secondly, the _{InzGa1 -zN} layer 533 and the GaN layer 534 are used as transitions to avoid a large lattice mismatch with the subsequent electron blocking layer 600 (β- _Ta2O5 layer). Thirdly, by introducing the _{AlxGa1 -xN layer} 531 with a higher barrier height, it is also prevented that the carriers overflow from the final well layer 520 and reduce the luminous efficiency.

The ratio of Al component (ie, x) in the _{AlxGa1 -xN} layer 531 is 0.05-0.3, exemplarily 0.08, 0.13, 0.18, 0.24, 0.25 or 0.29, but not limited thereto, and preferably 0.1-0.2.

The thickness of the _{AlxGa1 -xN} layer 531 is 3 nm to 10 nm, exemplarily 3.5 nm, 5 nm, 6.5 nm, 8 nm or 9.5 nm, but not limited thereto, preferably 3 nm to 8 nm.

The ratio of In component (i.e., y) in the In _y Ga _1-y N layer 532 is 0.01-0.1. If y<0.01, less negative charge is generated by polarization. If y>0.1, the overall barrier height of the last barrier layer 530 is too low, and it is difficult to effectively confine carriers in the last well layer 520 for recombination. Exemplarily, y is 0.02, 0.04, 0.06, or 0.08, but not limited thereto. Preferably, y is 0.02-0.04.

The thickness of the In _y Ga _1-y N layer 532 is 1 nm to 5 nm, and is exemplarily 1.2 nm, 1.5 nm, 1.8 nm, 2.2 nm, 2.6 nm, 3 nm, 3.7 nm or 4.4 nm, but is not limited thereto, and is preferably 1 nm to 3 nm.

The ratio of In component (i.e., z) in the In _z Ga _1-z N layer 533 is 0.01-0.1, and the present invention controls y＜z≤0.1 to prevent the barrier height of the last barrier layer 530 from being too low. Exemplarily, z is 0.02, 0.04, 0.06, or 0.08, but is not limited thereto. Preferably, z is 0.05-0.1.

The thickness of the In _z Ga _1-z N layer 533 is 1 nm to 5 nm, and is exemplarily 1.2 nm, 1.5 nm, 1.8 nm, 2.2 nm, 2.6 nm, 3 nm, 3.7 nm or 4.4 nm, but is not limited thereto, and is preferably 1 nm to 3 nm.

The thickness of the GaN layer 534 is 2 nm to 8 nm, exemplarily 3 nm, 5 nm, 7 nm or 8 nm, but not limited thereto, preferably 2 nm to 6 nm.

The electron blocking layer 600 is a β-Ta ₂ O ₅ layer, which has a high potential barrier and a small lattice mismatch with the GaN layer 534 , which greatly improves the blocking effect on electrons and improves the luminous efficiency of the light-emitting diode at various current densities.

The thickness of the electron blocking layer 600 is 20 nm to 80 nm, and is exemplarily 22 nm, 28 nm, 34 nm, 40 nm, 50 nm, 60 nm or 75 nm, but is not limited thereto, and is preferably 20 nm to 50 nm.

The P-type GaN layer 700 includes a first P-type GaN layer 710, a P-type In _α Ga _1-α N layer 720, and a second P-type GaN layer 730, which are sequentially stacked on the electron blocking layer 600. Based on the P-type GaN layer 700, the P-type In _α Ga _1-α N layer 720 with a lower barrier can play a role in storing holes, and the heterojunction formed by the P-type GaN layer 700 can effectively accelerate holes and improve the efficiency of hole injection into the multi-quantum well layer.

The thickness of the first P-type GaN layer 710 is 20 nm to 200 nm, and is exemplarily 30 nm, 50 nm, 70 nm, 90 nm, 120 nm or 180 nm, but is not limited thereto. Preferably, the thickness of the first P-type GaN layer 710 is 20 nm to 100 nm.

The P-type doping concentration of the first P-type GaN layer 710 is 1×10 ¹⁹ cm ⁻³ to 3×10 ²⁰ cm ⁻³ , preferably 1×10 ¹⁹ cm ⁻³ to 1×10 ²⁰ cm ⁻³ .

The ratio of the In component in the P-type In _α Ga _1-α N layer 720 (ie, α) is 0.08-0.15, and is 0.09, 0.11, 0.13 or 0.14, but not limited thereto, and is preferably 0.1-0.15.

The thickness of the P-type In _α Ga _1-α N layer 720 is 10 nm to 50 nm, exemplarily 12 nm, 20 nm, 28 nm, 36 nm or 44 nm, but not limited thereto, preferably 10 nm to 30 nm.

The P-type doping concentration in the P-type In _α Ga _1-α N layer 720 is 1×10 ¹⁷ cm ^-3 to 5×10 ¹⁹ cm ^-3 , preferably 1×10 ¹⁷ cm ^-3 to 1×10 ¹⁹ cm ^-3 .

The thickness of the second P-type GaN layer 730 is 50 nm to 200 nm, preferably 50 nm to 150 nm. The P-type doping concentration of the second P-type GaN layer 730 is 8×10 ¹⁹ cm ^-3 to 1×10 ²¹ cm ^-3 , preferably 1×10 ²⁰ cm ^-3 to 1×10 ²¹ cm ^-3 .

Preferably, in an embodiment of the present invention, the thickness of the _{AlxGa1 -xN} layer 531 is 1.5 to 3 times the thickness of the _{InyGa1 -yN} layer 532. Based on this thickness ratio, the probability of electron leakage can be further reduced.

Preferably, in one embodiment of the present invention, the thickness of the GaN layer 534 is 1.2 to 2 times the thickness of the In _z Ga _1-z N layer 533. Based on this thickness ratio, the probability of electron leakage can be further reduced.

The quantum well layer 511 and the final well layer 520 are the same, both are InGaN quantum well layers, and the In component ratio is 0.1-0.35, preferably 0.1-0.2. The thickness of the quantum well layer 511 and the final well layer 520 is 3nm-5nm.

The quantum barrier layer 512 is a GaN quantum barrier layer, and its thickness is 5 nm to 15 nm, preferably 8 nm to 15 nm.

The period number of the first multi-quantum well layer 510 is 3-15, preferably 5-15, and more preferably 8-15.

The substrate 100 is a sapphire substrate, a silicon substrate or a silicon carbide substrate, but is not limited thereto.

The buffer layer 200 is an AlN layer or an AlGaN layer, but is not limited thereto. The buffer layer 200 has a thickness of 20 nm to 80 nm.

The thickness of the non-doped GaN layer 300 is 1 μm-3 μm.

The N-type doping (Si) concentration in the N-type GaN layer 400 is 5×10 ¹⁸ cm ⁻³ to 5×10 ¹⁹ cm ⁻³ , and the thickness is 1 μm to 5 μm.

Correspondingly, referring to FIG. 2 , the present invention further provides a method for preparing a light emitting diode epitaxial wafer, which is used to prepare the light emitting diode epitaxial wafer, and specifically comprises the following steps:

S1: providing a substrate;

S2: sequentially growing a buffer layer, a non-doped GaN layer, an N-type GaN layer, a multi-quantum well layer, an electron blocking layer and a P-type GaN layer on the substrate;

Preferably, in some embodiments of the present invention, step S2 comprises:

S21: growing a buffer layer on the substrate;

The buffer layer may be grown by PVD, MOCVD, MBE or VPE, but is not limited thereto.

Preferably, in one embodiment of the present invention, an AlN layer is grown by PVD as a buffer layer.

S22: growing a non-doped GaN layer on the buffer layer;

The non-doped GaN layer may be grown by PVD, MOCVD, MBE or VPE, but is not limited thereto.

Preferably, in one embodiment of the present invention, the non-doped GaN layer is grown by MOCVD at a growth temperature of 1100° C. to 1150° C. and a growth pressure of 100 torr to 500 torr.

S23: growing an N-type GaN layer on the non-doped GaN layer;

The N-type GaN layer may be grown by MOCVD, MBE or VPE, but is not limited thereto.

Preferably, in one embodiment of the present invention, the N-type GaN layer is grown by MOCVD; the growth temperature is 1100° C. to 1150° C., and the growth pressure is 100 torr to 500 torr.

S24: growing a multi-quantum well layer on the N-type GaN layer;

Specifically, step S24 includes the following steps:

S241: growing a first multi-quantum well layer on the N-type GaN layer;

In one embodiment of the present invention, a quantum well layer and a quantum barrier layer are periodically grown on an N-type GaN layer by MOCVD until a multi-quantum well layer is obtained. The growth temperature of the quantum well layer is 740°C to 820°C, and the growth pressure is 100 torr to 300 torr. The growth temperature of the quantum barrier layer is 850°C to 950°C, and the growth pressure is 100 torr to 300 torr.

S242: growing a final well layer on the first multi-quantum well layer;

The InGaN quantum well layer may be grown by MOCVD, MBE or VPE as the final well layer, but is not limited thereto.

Preferably, in one embodiment of the present invention, an InGaN quantum well layer is grown by MOCVD as the final well layer; the growth temperature is 740° C. to 820° C., and the growth pressure is 100 torr to 300 torr.

S243: growing a final barrier layer on the final well layer to obtain a multi-quantum well layer;

Specifically, in one embodiment of the present invention, an _{AlxGa1 -xN} layer, an _{InyGa1 -yN} layer, an _{InzGa1 -zN} layer and a GaN layer are sequentially grown on the final well layer by MOCVD to obtain a final barrier layer;

Among them, the growth temperature of the last barrier layer is 850℃~950℃, and the growth pressure is 100torr~300torr.

S25: growing an electron blocking layer on the multi-quantum well layer;

The β-Ta ₂ O ₅ layer can be grown by PVD, MOCVD or PLD as an electron blocking layer, but is not limited thereto. Specifically, when MOCVD is used for growth, the Ta source used is Ta(C ₂ H ₅ O) ₅ , the O source is O ₂ , and N ₂ is used as a carrier gas.

Preferably, in one embodiment of the present invention, a β-Ta ₂ O ₅ layer is grown by MOCVD as the electron blocking layer, and the growth temperature is 800° C. to 900° C. and the growth pressure is 10 torr to 100 torr.

Preferably, in one embodiment, after the electron blocking layer is grown, annealing is performed at 900° C. to 950° C. for 10 min to 30 min in air or oxygen atmosphere. Based on the annealing treatment, the crystal quality of the β-Ta ₂ O ₅ layer can be further improved, and its blocking effect on electrons can be enhanced.

S26: growing a P-type GaN layer on the electron blocking layer;

Specifically, in one embodiment of the present invention, a first P-type GaN layer, a P-type In _α Ga _1-α N layer and a second P-type GaN layer are sequentially grown on the electron blocking layer to obtain a P-type GaN layer.

The growth temperature of the first P-type GaN layer and the second P-type GaN layer is 900° C. to 1000° C., and the growth pressure is 100 torr to 500 torr; the growth temperature of the P-type In _α Ga _1-α N layer is 750° C. to 850° C., and the growth pressure is 100 torr to 500 torr.

The present invention will be further described below with specific embodiments:

Example 1

The present embodiment provides a light emitting diode epitaxial wafer, which includes a substrate, a buffer layer, an undoped GaN layer, an N-type GaN layer, a multi-quantum well layer, an electron blocking layer and a P-type GaN layer sequentially stacked on the substrate.

The substrate is a sapphire substrate, the buffer layer is an AlN layer with a thickness of 45 nm, the thickness of the non-doped GaN layer is 1.5 μm, the doping element of the N-type GaN layer is Si with a doping concentration of 8×10 ¹⁸ cm ^-3 , and the thickness is 2.5 μm.

The multi-quantum well layer includes a first multi-quantum well layer, a final well layer and a final barrier layer stacked sequentially on the N-type GaN layer. The first multi-quantum well layer is a periodic structure with 9 periods, and each period includes a quantum well layer and a quantum barrier layer stacked sequentially. The quantum well layer is an In _0.2 Ga _0.8 N layer with a thickness of 3 nm; the quantum barrier layer is a GaN layer with a thickness of 10 nm. The final well layer is an In _0.2 Ga _0.8 N layer with a thickness of 3nm; the final barrier layer includes an Al _x Ga _1-x N layer (x=0.15), an In _y Ga _1-y N layer (y=0.03), an In _z Ga _1-z N layer (z=0.06) and a GaN layer stacked on the final well layer in sequence; among them, the thickness of the Al _x Ga _1-x N layer is 7nm, the thickness of the In _y Ga _1-y N layer is 1.5nm, the thickness of the In _z Ga _1-z N layer is 2nm, and the thickness of the GaN layer is 6nm. The electron blocking layer is a β-Ta ₂ O ₅ layer with a thickness of 50nm.

The P-type GaN layer includes a first P-type GaN layer, a P-type In _α Ga _1-α N layer (α=0.1) and a second P-type GaN layer which are sequentially stacked on the electron blocking layer, the Mg doping concentration in the first P-type GaN layer is 5×10 ¹⁹ cm ^-3 and the thickness thereof is 80 nm; the Mg doping concentration in the P-type In _α Ga _1-α N layer is 3×10 ¹⁸ cm ^-3 and the thickness thereof is 20 nm; the Mg doping concentration in the second P-type GaN layer is 5×10 ²⁰ cm ^-3 and the thickness thereof is 80 nm.

The method for preparing the light emitting diode epitaxial wafer in this embodiment comprises the following steps:

(1) Providing a substrate.

(2) growing a buffer layer on the substrate;

Among them, an AlN layer is grown by PVD as a buffer layer;

(3) growing a non-doped GaN layer on the buffer layer;

The non-doped GaN layer is grown by MOCVD at a growth temperature of 1120° C. and a growth pressure of 200 torr.

(4) growing an N-type GaN layer on the undoped GaN layer;

The N-type GaN layer is grown by MOCVD at a growth temperature of 1140° C. and a growth pressure of 300 torr.

(5) growing a first multi-quantum well layer on the N-type GaN layer;

Specifically, quantum well layers and quantum barrier layers are periodically grown on the N-type GaN layer by MOCVD until a first multi-quantum well layer is obtained, wherein the growth temperature of the quantum well layer is 750°C and the growth pressure is 200 torr; the growth temperature of the quantum barrier layer is 890°C and the growth pressure is 200 torr.

(6) growing a final well layer on the first multi-quantum well layer;

Specifically, the In _0.2 Ga _0.8 N layer is grown as the end well layer by MOCVD; the growth temperature is 750° C. and the growth pressure is 200 torr.

(7) growing a final barrier layer on the final well layer;

Specifically, an _{AlxGa1 -xN} layer, an _{InyGa1 -yN} layer, an _{InzGa1 -zN} layer and a GaN layer are grown in sequence by MOCVD; the growth temperature is 890°C and the growth pressure is 200 torr.

(8) growing an electron blocking layer on the final barrier layer;

Specifically, a β-Ta ₂ O ₅ layer is grown by MOCVD as an electron blocking layer, and the growth temperature is 840° C. and the growth pressure is 20 torr.

(9) Growing a P-type GaN layer on the electron blocking layer;

Specifically, in one embodiment of the present invention, a first P-type GaN layer, a P-type In _α Ga _1-α N layer and a second P-type GaN layer are sequentially grown on the electron blocking layer to obtain a P-type GaN layer; wherein the growth temperature of the first P-type GaN layer and the second P-type GaN layer is 920° C., and the growth pressure is 200 torr. The growth temperature of the P-type In _α Ga _1-α N layer is 750° C., and the growth pressure is 200 torr.

Example 2

This embodiment provides a light emitting diode epitaxial wafer, which is different from the first embodiment in that the thickness of the _{AlxGa1 -xN} layer is 6 nm, and the thickness of the _{InyGa1 -yN} layer is 2.5 nm.

The rest are the same as in Example 1.

Example 3

This embodiment provides a light emitting diode epitaxial wafer, which is different from the embodiment 2 in that:

The thickness of the _{InzGa1 -} zN layer is 2.5 nm, and the thickness of the GaN layer is 4.5 nm.

The rest is the same as Example 2.

Example 4

This embodiment provides a light emitting diode epitaxial wafer, which is different from the embodiment 3 in that:

After the electron blocking layer is grown, annealing is performed at 930°C in an oxygen atmosphere for 20 min.

The rest are the same as in Example 1.

Comparative Example 1

This comparative example provides a light emitting diode epitaxial wafer, which differs from Example 1 in that:

The last barrier layer is a GaN layer with a thickness of 10 nm; the electron blocking layer is an Al _0.4 Ga _0.6 N layer with a thickness of 30 nm; the P-type GaN layer is composed only of P-type GaN with a Mg doping concentration of 5×10 ²⁰ cm ^-3 and a thickness of 200 nm.

In this comparative example, the growth conditions of the final barrier layer are the same as the growth conditions of the quantum barrier layer in Example 1.

The growth temperature of the electron blocking layer is 1120° C. and the growth pressure is 300 torr. The growth conditions of the P-type GaN layer are the same as those of the first P-type GaN layer in Example 1.

The rest are the same as in Example 1.

Comparative Example 2

This comparative example provides a light-emitting diode epitaxial wafer, which differs from Example 1 in that:

The final barrier layer is a GaN layer with a thickness of 10 nm. Its growth conditions are the same as those of the quantum barrier layer in Example 1.

The rest are the same as in Example 1.

Comparative Example 3

This comparative example provides a light emitting diode epitaxial wafer, which differs from Example 1 in that:

The electron blocking layer is an Al _0.4 Ga _0.6 N layer with a thickness of 30 nm; its growth temperature is 1120° C. and the growth pressure is 300 torr.

The rest are the same as in Example 1.

Comparative Example 4

This comparative example provides a light emitting diode epitaxial wafer, which differs from Example 1 in that:

The electron blocking layer is a δ-Ta ₂ O ₅ layer; its growth temperature is 750° C. and the growth pressure is 20 torr.

The rest are the same as in Example 1.

Comparative Example 5

This comparative example provides a light emitting diode epitaxial wafer, which differs from Example 1 in that:

The P-type GaN layer consists only of P-type GaN, has a Mg doping concentration of 5×10 ²⁰ cm ⁻³ , and a thickness of 200 nm. The growth conditions of the P-type GaN layer are the same as those of the first P-type GaN layer in Example 1.

The rest are the same as in Example 1.

The light emitting diode epitaxial wafers obtained in Examples 1 to 4 and Comparative Examples 1 to 5 were tested, and the specific method is as follows:

(1) The epitaxial wafer was made into a 10 mil × 24 mil chip, and its luminous power was tested at 60 mA, 120 mA, and 1 A respectively. The luminous power improvement rate was calculated based on the data of comparative example 1.

Specifically, the luminous power improvement rate = (luminous power of each embodiment/comparative example-luminous power of comparative example 1)/luminous power of comparative example 1; when calculating, the test current used is the same.

(2) The internal quantum efficiency of each epitaxial wafer at 60 mA and 120 mA was measured using a PL tester, and the attenuation rate was calculated. Specifically, the attenuation rate = (internal quantum efficiency at 60 mA - internal quantum efficiency at 120 mA) / internal quantum efficiency at 60 mA.

The specific results are shown in the following table:

The above is a preferred embodiment of the invention. It should be pointed out that a person skilled in the art can make several improvements and modifications without departing from the principle of the invention. These improvements and modifications are also considered to be within the scope of protection of the invention.

Claims (10)

1. The light-emitting diode epitaxial wafer is characterized by comprising a substrate, and a buffer layer, an undoped GaN layer, an N-type GaN layer, a multiple quantum well layer, an electron blocking layer and a P-type GaN layer which are sequentially laminated on the substrate;

The multi-quantum well layer comprises a first multi-quantum well layer, a last well layer and a last barrier layer which are sequentially laminated on the N-type GaN layer, wherein the first multi-quantum well layer is a periodic structure formed by alternately laminating a quantum well layer and a quantum barrier layer, the quantum well layer and the last well layer are InGaN quantum well layers, and the quantum barrier layer is a GaN quantum barrier layer;

the final barrier layer comprises an Al _xGa_1-x N layer, an In _yGa_1-y N layer, an In _zGa_1-z N layer and a GaN layer which are sequentially laminated on the final well layer; wherein, the value range of x is 0.05-0.3, the value range of y is 0.01-0.1, the value range of z is 0.01-0.1, and z > y;

The electron blocking layer is a beta-Ta ₂O₅ layer;

The P-type GaN layer comprises a first P-type GaN layer, a P-type In _αGa_1-α N layer and a second P-type GaN layer which are sequentially laminated on the electron blocking layer, wherein the value range of alpha is 0.08-0.15.

2. The light-emitting diode epitaxial wafer of claim 1, wherein the thickness of the Al _xGa_1-x N layer is 3 nm-8 nm, and the value range of x is 0.1-0.2; and/or

The thickness of the In _yGa_1-y N layer is 1 nm-3 nm, and the value range of y is 0.02-0.04; and/or

The thickness of the In _zGa_1-z N layer is 1 nm-3 nm, and the value range of z is 0.05-0.1; and/or

The thickness of the GaN layer is 2 nm-6 nm.

3. The light-emitting diode epitaxial wafer of claim 1, wherein the electron blocking layer has a thickness of 20nm to 50nm; and/or

The thickness of the first P-type GaN layer is 20 nm-100 nm, and the P-type doping concentration is 1 multiplied by 10 ¹⁹cm^-3~1×10²⁰cm^-3; and/or

The thickness of the P-type In _αGa_1-α N layer is 10 nm-30 nm, and the P-type doping concentration is 1 multiplied by 10 ¹⁷cm^-3~1×10¹⁹cm^-3; and/or

The thickness of the second P-type GaN layer is 50-150 nm, and the P-type doping concentration is 1 multiplied by 10 ²⁰cm^-3~1×10²¹cm^-3.

4. A light emitting diode epitaxial wafer according to any one of claims 1 to 3, wherein the thickness of the Al _xGa_1-x N layer is 1.5 to 3 times the thickness of the In _yGa_1-y N layer.

5. A light emitting diode epitaxial wafer according to any one of claims 1 to 3, wherein the thickness of the GaN layer is 1.2 to 2 times the thickness of the In _zGa_1-z N layer.

6. The light-emitting diode epitaxial wafer according to claim 1, wherein the In component In the quantum well layer and the final well layer accounts for 0.1-0.2, and the thickness of the quantum well layer and the final well layer is 3-5 nm;

The thickness of the quantum barrier layer is 5 nm-15 nm.

7. A method for preparing a light-emitting diode epitaxial wafer, which is used for preparing the light-emitting diode epitaxial wafer according to any one of claims 1 to 6, and is characterized by comprising the following steps:

Providing a substrate, and sequentially growing a buffer layer, an N-type GaN layer, a multiple quantum well layer, an electron blocking layer and a P-type GaN layer on the substrate;

The multi-quantum well layer comprises a first multi-quantum well layer, a last well layer and a last barrier layer which are sequentially laminated on the N-type GaN layer, wherein the first multi-quantum well layer is a periodic structure formed by alternately laminating a quantum well layer and a quantum barrier layer, the quantum well layer and the last well layer are InGaN quantum well layers, and the quantum barrier layer is a GaN quantum barrier layer;

the final barrier layer comprises an Al _xGa_1-x N layer, an In _yGa_1-y N layer, an In _zGa_1-z N layer and a GaN layer which are sequentially laminated on the final well layer; wherein, the value range of x is 0.05-0.3, the value range of y is 0.01-0.1, the value range of z is 0.01-0.1, and z > y;

The electron blocking layer is a beta-Ta ₂O₅ layer;

The P-type GaN layer comprises a first P-type GaN layer, a P-type In _αGa_1-α N layer and a second P-type GaN layer which are sequentially laminated on the electron blocking layer, wherein the value range of alpha is 0.08-0.15.

8. The method for preparing a light-emitting diode epitaxial wafer according to claim 7, wherein the growth temperature of the quantum well layer and the final well layer is 740-820 ℃ and the growth pressure is 100-300 torr; and/or

The growth temperature of the quantum barrier layer and the final barrier layer is 850-950 ℃ and the growth pressure is 100-300 torr; and/or

The growth temperature of the electron blocking layer is 800-900 ℃, and the growth pressure is 10-100 torr; and/or

The growth temperature of the first P type GaN layer and the second P type GaN layer is 900-1000 ℃, and the growth pressure is 100-500 torr; and/or

The growth temperature of the P-type In _αGa_1-α N layer is 750-850 ℃, and the growth pressure is 100-500 torr.

9. The method for preparing a light-emitting diode epitaxial wafer according to claim 8, wherein after the electron blocking layer is grown, annealing is performed in an air or oxygen atmosphere at 900-950 ℃ for 10-30 min.

10. A light emitting diode comprising the light emitting diode epitaxial wafer according to any one of claims 1 to 6.