CN118571301B - A memory test and repair system and method, and integrated circuit - Google Patents
A memory test and repair system and method, and integrated circuit Download PDFInfo
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
- G11C29/56008—Error analysis, representation of errors
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/44—Indication or identification of errors, e.g. for repair
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
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Abstract
The application relates to the technical field of integrated circuits, in particular to a test repair system and method for a memory and an integrated circuit. The system comprises a memory array with redundant columns, a first controller, a second controller, a third controller, a fourth controller and a memory array, wherein the first controller receives a first test signal in a first test mode and outputs a first test control signal, the second controller receives a second test signal in a second test mode and outputs a second test control signal, the second controller receives the first/second test control signal and generates a third test control signal, the third controller traverses the memory array under the third test control signal and feeds back and outputs a first test result to the first controller, the third controller analyzes and outputs a second test result, the third controller analyzes the second test result to obtain fault information, the fourth controller analyzes the fault information and outputs a repair control signal to the memory array, and the memory array is repaired in an address reconstruction mode. The system saves hardware resources and test time.
Description
Technical Field
The application relates to the technical field of integrated circuits, in particular to a test repair system and method for a memory and an integrated circuit.
Background
Memory arrays in integrated circuits are the core components of data storage, whose reliability directly affects the performance of the overall system. To ensure reliability of memory arrays, two main repair strategies, hard repair and soft repair, are commonly employed in the industry.
Hard repair techniques hard repair typically involves testing a memory array using external automated test equipment to determine faulty cells and physically implement permanent repair. It has a number of disadvantages including requiring a large amount of hardware resources, long test time, etc.
In the soft repair technology, the existing soft repair technology does not use an APB system bus as a test means or channel, and the system cannot acquire and use test results and fault information, so that the test means is harder and has poor flexibility.
Disclosure of Invention
In order to solve the technical problems, the application provides a test repair system and method for a memory, and an integrated circuit, so that hardware resources and test time are saved.
The application provides a test repair system of a memory, which comprises a memory array with a redundant column, a first controller, a third controller, a fourth controller and a repair controller, wherein the first controller comprises a first control unit and a second control unit, the first control unit receives a first test signal in a first test mode and then outputs the first test control signal, the second control unit receives a second test signal in a second test mode and then outputs a second test control signal, the second controller receives the first/second test control signal and generates a third test control signal, the third test control signal comprises a test vector sequence and an address read-write control signal, after traversing the memory array under the third test control signal, the first controller feeds back and outputs a first test result, and compares and analyzes the second test result to obtain a current test address and a failure bitmap, the third controller receives and analyzes the second test result to obtain fault information, the fault information comprises a fault bad point type, a failure bit number and a bad point, the fourth controller receives and analyzes the fault information to obtain the fault information, and the fault point type can be repaired by the fault point type and the fault point type, and the fault point type can be repaired by the address read-write control signal, and the repair signal can be repaired by the address type of the memory array.
According to the test repair system of the memory, the corresponding controllers are controlled by the automatic tester control unit to complete the test of the memory array with the redundant columns, and the APB bus control unit can also be used for controlling the corresponding controllers to complete the test of the memory array with the redundant columns, so that the test means are more diversified and the operation is more flexible. Meanwhile, in the repair process of the memory array with the redundant columns, hard repair is not needed through laser or electronic fuses, and hardware resources and test time are saved.
In one implementation, the system further comprises a central processing unit connected with the first controller and used for sending the first test signal to the first controller, and the central processing unit is used for receiving the fault information output by the first controller.
According to the test repair system of the memory, the central processing unit reads the fault information from the first control unit, when the fault type is the repairable type, the generated repair information is written into the register unit, and the latch control unit is controlled to output the repair control signal to the memory array with the redundant columns for repair, so that the flexibility and the user experience of the system are further improved.
In one implementation, the fourth controller includes a latch control unit that analyzes the fault information, outputs the repair control signal to the memory array when the fault information is of a repairable type, and a register unit that latches the fault information when the fault information is of a repairable type.
In the test repair system of the memory, after the fourth controller receives the fault information sent by the third controller, the latch control unit judges whether the fault type in the fault information is a repairable type. If the fault type is a repairable type, the latch control unit outputs a repair control signal to the memory array with the redundant columns for repair, and the register unit latches fault information, and if the fault type is a non-repairable type, the latch control unit does not output the repair control signal, and the register unit does not latch the fault information. Therefore, the area overhead of the test repair system of the memory can be reduced, and the aim of balancing the repair efficiency is achieved.
In one implementation, the fourth controller further includes a test control unit that detects a repair result after the memory array completes repair.
According to the test repair system of the memory, whether the memory array with the redundant columns is repaired successfully is confirmed by comparing the previous test result with the secondary test result, so that the repair accuracy is improved, and the repair error is reduced.
In one implementation, the registering unit receives the repair information written by the central processing unit through the first control unit, the latch control unit receives the repair information and generates the repair control signal, and the central processing unit also reads the second test result from the registering unit through the first control unit.
In one implementation, the central processing unit is further configured to receive a first test result obtained by the test machine from the second control unit, generate the repair information, and send the second test control signal by the test machine.
According to the test repair system of the memory, the central processing unit can be linked with the automatic test machine to obtain the first test result obtained by the automatic test machine in the first test mode or the second test mode, and corresponding repair information is generated according to the first test result. And then writing the repair information into the register unit, controlling the latch control unit to output a repair control signal to repair the memory array with the redundant columns, and further improving the compatibility of the system.
In one implementation, the first controller further comprises a data synchronization unit, and when the first controller and the central processing unit interact data through a bus, the data synchronization unit performs synchronization processing on the data.
In one implementation, the second controller comprises a test vector generator and a comparator, wherein the test vector generator generates the third test control signal according to an algorithm model, the comparator compares and analyzes and outputs the second test result, the algorithm model is built in the third controller, whether a tested memory array has fault dead points and the number of dead points or not is analyzed, and when single dead points or single-column multiple dead points exist, the fault dead points are of a repairable type.
In a second aspect, the present application also provides an integrated circuit, including a test repair system for implementing a memory as described in any of the above.
The application further provides a test repair method of the memory, which is applied to the test repair system for realizing the memory, and comprises the steps of generating a first test control signal when the memory is in a first test mode by analysis, generating a second test control signal when the memory is in a second test mode by analysis, generating a third test control signal according to the first/second test control signals, wherein the third test control signal comprises a test vector sequence and an address read-write control signal, feeding back and outputting a first test result after traversing the memory array under the third test control signal, comparing and analyzing and outputting a second test result, wherein the second test result comprises a current test address and a failure bitmap, analyzing the second test result to obtain fault information, wherein the fault information comprises a fault dead point type, a failure bit number and a fault address, outputting a repair control signal to the memory array in a mode of address reconstruction when the fault dead point type is a repairable type, and repairing the memory array in a mode.
Compared with the prior art, the application has at least one of the following beneficial effects:
1. The corresponding controllers are controlled by the control unit of the automatic tester to finish the test of the memory array with the redundant columns, and the APB bus control unit can also be used for controlling the corresponding controllers to finish the test of the memory array with the redundant columns, so that the test means are more diversified and the operation is more flexible. Meanwhile, in the repair process of the memory array with the redundant columns, hard repair is not needed through laser or electronic fuses, and hardware resources and test time are saved.
2. The central processing unit reads fault information from the first control unit, when the fault type is a repairable type, the generated repair information is written into the register unit, and the latch control unit is controlled to output a repair control signal to the memory array with the redundant columns for repair, so that the flexibility and the user experience of the system are further improved.
3. After receiving the fault information sent by the third controller, the fourth controller latches the control unit to judge whether the fault type in the fault information is a repairable type. If the fault type is a repairable type, the latch control unit outputs a repair control signal to the memory array with the redundant columns for repair, and the register unit latches fault information, and if the fault type is a non-repairable type, the latch control unit does not output the repair control signal, and the register unit does not latch the fault information. Therefore, the area overhead of the test repair system of the memory can be reduced, and the aim of balancing the repair efficiency is achieved.
4. By comparing the previous test result with the secondary test result, whether the memory array with the redundant columns is successfully repaired is confirmed, the repair accuracy is improved, and the repair error is reduced.
5. The central processing unit can be linked with the automatic test machine to acquire a first test result obtained by the automatic test machine in the first test mode or the second test mode, and corresponding repair information is generated according to the first test result. And then writing the repair information into the register unit, controlling the latch control unit to output a repair control signal to repair the memory array with the redundant columns, and further improving the compatibility of the system.
Drawings
The above features, technical features, advantages and implementation of the present application will be further described in the following description of preferred embodiments with reference to the accompanying drawings in a clear and easily understood manner.
FIG. 1 is a schematic diagram of a hard repair architecture for a memory according to an embodiment of the present application;
FIG. 2 is a schematic diagram of a memory soft repair structure according to an embodiment of the present application;
FIG. 3 is a schematic diagram of a memory test repair system according to an embodiment of the present application;
FIG. 4 is a flow chart of a test repair of a memory according to an embodiment of the present application;
Fig. 5 shows a flowchart of a method for repairing a memory by testing according to an embodiment of the present application.
Reference numerals:
The test system comprises a first controller 100, a second controller 200, a third controller 300, a fourth controller 400, a storage array 500 with redundant columns, an automatic test machine 600, a central processing unit 700, a memory management unit 800, a first control unit 110, a second control unit 120, a data synchronization unit 130, a test vector generator 210, a state machine 220, a comparator 230, a register unit 410, a latch control unit 420 and a test control unit 430.
Detailed Description
In the following description, for purposes of explanation and not limitation, specific details are set forth such as the particular system architecture, techniques, etc., in order to provide a thorough understanding of the embodiments of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail.
It should be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
For simplicity of the drawing, only the parts relevant to the invention are schematically shown in each drawing, and they do not represent the actual structure thereof as a product. Additionally, in order to simplify the drawing for ease of understanding, components having the same structure or function in some of the drawings are shown schematically with only one of them, or only one of them is labeled. Herein, "a" means not only "only this one" but also "more than one" case.
It should be further understood that the term "and/or" as used in the present specification and the appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes such combinations.
In this context, unless explicitly stated or limited otherwise, the terms "mounted," "connected," "coupled," and "connected" are to be construed broadly, and may, for example, be fixedly connected, detachably connected, or integrally connected, mechanically connected, electrically connected, directly connected, indirectly connected via an intervening medium, or communicate between two elements. The specific meaning of the above terms in the present application will be understood in specific cases by those of ordinary skill in the art.
In particular implementations, the terminal devices described in embodiments of the present application include, but are not limited to, other portable devices such as mobile phones, laptop computers, home teaching machines, or tablet computers having touch-sensitive surfaces (e.g., touch screen displays and/or touchpads). It should also be appreciated that in some embodiments, the terminal device is not a portable communication device, but rather a desktop computer having a touch-sensitive surface (e.g., a touch screen display and/or a touch pad).
In addition, in the description of the present application, the terms "first," "second," and the like are used merely to distinguish between descriptions and are not to be construed as indicating or implying relative importance.
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following description will explain the specific embodiments of the present application with reference to the accompanying drawings. It is evident that the drawings in the following description are only examples of the application, from which other drawings and other embodiments can be obtained by a person skilled in the art without inventive effort.
Static Random-Access Memory (SRAM) is a widely used Memory technology in integrated circuits. It is mainly used in the occasion that needs frequent and quick read-write operation. Thus, the initial form of SRAM is a simple memory matrix, consisting of basic memory cells, each cell being responsible for storing one bit of data. SRAM designs at this stage focus on speed and efficiency, but are less tolerant of faults. In particular, the failure of a memory cell, once it has occurred, may lead to failure of the entire chip. To improve the reliability of SRAM, designers began to introduce the concept of redundancy. This is just like adding a "replacement team member" to the memory, and when a certain memory unit fails, the redundant unit can immediately take over its work, also called redundancy allocation. For this reason, on the basis of SRAM, designers have designed SRAM memory arrays with redundant columns.
The SRAM memory array with redundant columns is composed of a plurality of large-capacity memory array groups formed by a plurality of small-capacity single-port SRAM memories or double-port SRAM memories, and the number of the array groups can be dynamically configured according to the demands of a chip system. Redundant columns are additional memory cells in the array that normally do not participate in data storage, but are ready to replace those that fail. These redundant columns are physically adjacent to normal memory cells but logically independent.
When a cell or column in a memory array fails, the system can identify the location of the failure by built-in failure detection and repair logic and replace the failed cell with a redundant column, a process known as "fail-over". After replacing the failed unit with a redundant column, the system needs to adjust the address mapping of the memory to ensure that the logical to physical address mapping is still correct. This typically involves the logic of address reconstruction, which can automatically redirect accesses to failed cells to redundant columns.
There are a number of repair approaches to the repair of a memory array, described below in conjunction with the accompanying drawings:
Referring to fig. 1, a schematic diagram of a hard repair structure for a memory according to an embodiment of the present application is shown. As shown in fig. 1, the system includes a memory array 500 with redundant columns, an automatic test equipment 600, and electronic fuses 900. The automatic test equipment 600 is used for testing whether the storage array 500 with the redundant array has a fault, for example, the automatic test equipment sends a test vector sequence with a diagnostic function to the storage array 500 with the redundant array for testing. The redundant array 500 is used to feed back corresponding test responses to the automated test equipment 600. The electronic fuse 900 is used to repair a failure occurring in the memory array 500 with redundant columns. The automated test equipment 600 communicates with the storage array 500 with redundant columns. The communication means includes, for example, but is not limited to, I/O interfaces, JTAG interfaces, boundary scan, serial communication, parallel communication, dedicated test interfaces, control signals, data synchronization, status and command registers, network communication, test access ports, etc.
Taking the I/O interface as an example, the automatic test equipment 600 sends a test vector sequence with a diagnostic function to the storage array 500 with redundant columns through the I/O interface, so as to traverse the whole storage array. And testing whether each storage array can work normally. After the test is completed, the storage array 500 with redundant columns feeds back the corresponding test response to the automatic test machine 600. And the automatic test machine generates a bitmap according to the test response. Wherein the bitmap indicates which storage arrays are operating properly and which are malfunctioning. A failure bitmap is a type of bitmap on which only which storage arrays fail is marked. The automatic test equipment 600 performs redundancy allocation according to the failure bitmap and obtains corresponding reconfiguration repair information. The reconfiguration repair information is then downloaded to the electronic fuse 900. Address mapping between the failed column and the redundant column is achieved by laser or by blowing the electronic fuse 900, so that the redundant column replaces the failed column, and address reconstruction can be completed. I.e., the system attempts to access a failed column, the control logic will automatically redirect the access to the corresponding redundant column. Thus, the repair of the failure of the storage array 500 with redundant columns is completed.
Repair of a failed memory array may take the form of soft repair in addition to hard repair. For example, referring to fig. 2, a schematic structural diagram of a memory soft repair according to an embodiment of the present application is shown. As shown in fig. 2, includes a second controller 200, a third controller 300, a fourth controller 400, and a memory array 500 with redundant columns. The second controller 200 is configured to generate test control signals for performing fault detection on the memory array 500 with redundant columns, where the test control signals include a test vector sequence and address read/write signals, for example. The third controller 300 is configured to analyze the test results obtained by the second controller 200, for example, the test results including the current test address and the failure bitmap. The fourth controller 400 is configured to perform redundancy column allocation and address reconstruction according to the fault information analyzed by the third controller 300, where the fault information includes, for example, a fault dead pixel type, a fault bit number, and a dead pixel address. The controller or algorithm implementing the functions of the second controller 200 includes, for example, but is not limited to, a built-In Self-Test (BIST) controller, a travel Test algorithm, a scan path, and the like. The controller or algorithm implementing the functionality of the third controller 300 includes, for example, but is not limited to, a built-In Self-diagnostic (BISD) controller, fault isolation logic, diagnostic engine, and the like. The controller or algorithm implementing the functions of the fourth controller 400 includes, for example, but is not limited to, a built-In Self-Repair (BISR) controller, redundant logic, repair fuses, etc.
Taking the second controller 200 as a BIST controller, the third controller 300 as a BISD controller, and the fourth controller 400 as a BISR controller as an example, the second controller 200 is self-started after the system is powered on, and sends a test control signal to the storage array with redundant array 500 to detect whether the storage array with redundant array 500 fails. And sending the current test address and the failure bitmap in the test result to the third controller 300 for analysis, so as to obtain the fault dead pixel type, the failure bit number and the dead pixel address. The third controller 300 transmits the defective pixel type, the defective bit number, and the defective pixel address to the fourth controller 400, and the fourth controller 400 performs redundancy column allocation according to the received defective information to replace the detected defective memory array, and performs corresponding address reconstruction. The scheme realizes the built-in self-repair of the memory, shields the invalid memory, and improves the yield and reliability of the memory.
The embodiment of the application also provides a fault repairing method for the memory array, which enables the APB (ADVANCED PERIPHERAL Bus) Bus system to directly obtain the test result and the fault information by interacting the APB Bus system, the automatic test machine, the second controller 200, the third controller 300 and the fourth controller 400, and controls the fourth controller 400 to repair the memory array 500 with the redundant columns according to the test result and the fault information. The APB bus system may also obtain test results from the automatic test equipment so that the test results of the automatic test equipment may be used to write into the fourth controller 400 and repair the memory array 500 with redundant columns.
Referring to fig. 3, a schematic structural diagram of a test repair system for a memory according to an embodiment of the present application is shown. As shown in fig. 3, the system includes a first controller 100, a second controller 200, a third controller 300, a fourth controller 400, a storage array 500 with redundant columns, an automatic test equipment 600, a central processing unit 700, and a memory management unit 800. Wherein the first controller 100 includes a first control unit 110 and a second control unit 120. The first control unit 110 receives a first test signal in a first test mode and outputs a first test control signal, the second control unit 120 receives a second test signal in a second test mode and outputs a second test control signal, the second controller 200 receives the first/second test control signal and generates a third test control signal, the third test control signal comprises a test vector sequence and an address read-write control signal, after traversing the memory array 500 with redundancy columns under the third test control signal, the first controller 100 is fed back and outputs a first test result, and compares and analyzes the second test result, the second test result comprises a current test address and a failure bitmap, the third controller 300 receives and analyzes the second test result to obtain fault information, the fault information comprises a fault dead point type, a failure bit number and a dead point address, the fourth controller 400 receives and analyzes the fault information, when the fault dead point type is a repairable type, the memory array 500 with redundancy columns is output a repair control signal, the memory array 500 with redundancy columns is repaired in an address reconstruction mode, and the repair control signal comprises a repairing signal and a repairable address sequence.
In the embodiment of the application, the first test mode is a self-test and self-repair process, and the second test mode is an automatic test machine test process. The user can select a corresponding test mode to test according to the self requirement.
Taking the first test mode as an example, after the initialization of the power-on reset of the test repair system of the memory is completed, the self-test and the self-repair flow are completed in the starting process (wherein, the entering flow of the self-test is that the user sends a self-test starting instruction through the SWD port on the central processing unit 700 by using the software program, and the first control unit 110 starts the self-test flow according to the self-test starting instruction), and then enters the normal working mode one. Where normal operation mode one is that the memory array 500 with redundant columns has no failure or that the failure has been repaired. In the first test mode, the first control unit 110 receives the first test signal and generates a corresponding first test control signal (bist _clk, rst_l, test_h). The second controller 200 generates a third test control signal according to the first test control signal. The memory array 500 with redundant columns is tested by traversing the third test control signal, and after the test is completed, the second controller 200 feeds back the first test result to the first controller 100. Meanwhile, the second controller 200 also performs exclusive-or comparison analysis on the content to be tested in the memory array 500 with redundant columns and the expected value, and outputs a corresponding second test result to the third controller 300. The third controller 300 analyzes the second test result to obtain fault information, and transmits the fault information to the first controller 100 and the fourth controller 400, respectively. The fourth controller 400 receives and analyzes the fault information, and when judging that the fault bad point type in the fault information is a repairable type, outputs a repair enable signal (repairable_enable) and a bad point address sequence (repairable_data_auto) to the memory array 500 with the redundant columns, so that the redundant columns in the memory array 500 with the redundant columns replace the detected faulty memory array, and performs corresponding address reconstruction. Thereby completing the first test mode.
Taking the second test mode as an example, the automatic test equipment 600 sends a second test signal to the second control unit 120 in the first controller 100, where the second test signal includes an input clock (ate_clk), a reset (reset), an enable bit (test_debug_l), and an array selection (test_mb_sel). The enable bit is used to control the first controller 100 to enter the testing process of the automatic testing machine. In this flow, the second control unit 120 generates a corresponding second test control signal according to the second test signal. The second controller 200 generates a third test control signal according to the second test control signal. After the test is completed, the second controller 200 feeds back a first test result (fail_h/test_done) to the first controller 100 through the third test control signal traversing the memory array 500 with redundant columns, wherein fail_h indicates that a fault is found during the test, and test_done indicates that the test flow has ended. The second control unit 120 in the first controller 100 transmits the first test result and repair_info to the automatic test equipment 600, thereby completing the second test mode. It is contemplated that during the second test mode, the automated test equipment 600 obtains test results for all memory arrays because the redundant columns of memory arrays 500 are tested in parallel. To determine which column of memory is faulty, the automatic test equipment 600 may modify the value of the array selection (e.g., to test_mb_sel [2:0 ]), select the designated memory array for testing, or perform serial scan testing on each memory one by one. At this time, the test result of the memory to be tested is obtained by the automatic test machine 600.
In the embodiment of the present application, the first controller 100 is a system controller, the first control unit 110 is an APB bus control unit, and the second control unit 120 is an automatic tester control unit.
An APB bus control unit for controlling the first test mode, which includes a series of register sets mounted on the APB bus. Including, for example, but not limited to, a plurality of command register sets, a plurality of status register sets, etc. The command register set (BIST_CSR) is used for controlling the starting or suspending of the built-in self test/built-in self repair flow and reflecting whether the built-in self test/built-in self repair is completed or not. The set of STATUS registers (bist_status_xxx) records the first test result and fault information for each memory. The first test result of each memory will have an independent status bit record.
And an automatic test machine control unit for controlling the second test mode to communicate with the automatic test machine 600 through an external I/O interface. And receives the second test signal sent by the automatic test machine 600, and feeds back the first test result and the repair information to the automatic test machine 600.
The embodiment of the application can not only control the corresponding controller to complete the test of the memory array with the redundant columns through the control unit of the automatic testing machine, but also control the corresponding controller to complete the test of the memory array with the redundant columns through the APB bus control unit, so that the test means is more diversified and the operation is more flexible. Meanwhile, in the repairing process of the memory array with the redundant columns, hard repairing is not needed through laser or electronic fuses, and hardware resources and testing time are saved.
In one case, the Memory array 500 with redundant columns is generated by a Memory Compiler configuration to support redundant column repair. In order to balance the repair efficiency and the area overhead, the embodiment of the application can support the repair of the fault dead point of the single-column memory. A column may be repaired when one or more bits fail in that column, but the array memory cannot be repaired when two or more columns fail. Therefore, the fault type in the fault information can be divided into a repairable type and a non-repairable type, and the fault type information is characterized by two combined signals (repairable _h, repair_data_force).
In the first test mode, the fourth controller 400 needs to perform different operations according to the type of fault when receiving the fault information. For example, referring to fig. 3, an embodiment of the present application provides a test repair system for a memory, the fourth controller 400 includes a latch control unit 410 analyzing fault information, outputting a repair control signal to a memory array when the fault information is of a repairable type, and a register unit 420 latching the fault information when the fault information is of a repairable type. The latch control unit 410 may be a repairable fault latch unit, and the register unit 420 may be a repair information register unit.
After receiving the fault information sent by the third controller 300, the latch control unit 410 determines whether the fault type in the fault information is a repairable type. If the failure type is a repairable type, the latch control unit 410 outputs a repair control signal to the memory array 500 with the redundant columns for repair while the register unit 420 latches the failure information, and if the failure type is a non-repairable type, the latch control unit 410 does not output a repair control signal while the register unit 420 does not latch the failure information. Therefore, the area overhead of the test repair system of the memory can be reduced, and the aim of balancing the repair efficiency is fulfilled.
In one embodiment of the application, the repairable type of failure information may optionally be configured by software and written to the register unit 420 via the central processor 700 to facilitate user invocation to effect repair of the memory array 500 with redundant columns. For example, referring to fig. 3, an embodiment of the present application provides a test repair system for a memory, in which a central processor 700 is connected to a first controller 100 to send a first test signal to the first controller 100, the central processor 700 receives fault information output by the first controller 100, a register unit 420 receives repair information written by the central processor 700 through a first control unit 110, and a latch control unit 410 receives the repair information and generates a repair control signal.
The central processor 700 accesses the respective status register sets in the first control unit 110 through the APB bus, and reads the fault information therefrom. The central processor 700 determines whether the fault type in the fault information is a repairable type. If it is determined that the repairable type, it is further determined whether the memory array 500 with redundant columns is completed. If the repair is judged to be completed, the central processing unit 700 controls the test repair system of the memory to enter the first normal operation mode, and if the repair is judged to be completed, the central processing unit 700 generates corresponding repair information according to the fault information, writes the repair information into the register unit 420 through the first control unit 110, and controls the latch control unit 410 to output a repair control signal to the memory array 500 with the redundant columns for repair.
Further, if the cpu 700 determines that the fault type in the fault information is an unrepairable type, the test repair system of the memory is controlled to enter the second normal operation mode. In the second normal operation mode, the cpu 700 sends the fault information of the unrepairable type to the memory management unit 800. The memory management unit 800 replaces unrepairable failed memory columns with reserved redundant columns by means of software and hardware, writes data originally written to the failed memory columns into the replaced redundant columns, or avoids the failure memory columns from being used.
In the embodiment of the application, the central processing unit reads the fault information from the first control unit, writes the generated repair information into the register unit when the fault type is a repairable type, and controls the latch control unit to output the repair control signal to the memory array with the redundant columns for repair, thereby further improving the flexibility and user experience of the test flow.
In one embodiment of the present application, the central processor 700 may further receive the first test result sent by the automatic test equipment 600, and generate corresponding repair information according to the first test result, so as to repair the memory array 500 with redundant columns. For example, referring to fig. 3, an embodiment of the present application provides a test repair system for a memory, where the central processor 700 is further configured to receive a first test result obtained by a test machine from the second control unit 120, generate repair information, and send a second test control signal to the test machine.
In the embodiment of the present application, the central processing unit 700 receives the first test result obtained from the second control unit 120 by the automatic test machine (the test machine is an automatic test machine) 600, and generates repair information. Meanwhile, the central processor 700 writes the generated repair information to the register unit 420 in the fourth controller 400 through the first control unit 110, and the register unit 420 also transmits the repair information to the latch control unit 410. The latch control unit 410 generates a repair control signal according to the repair information and transmits the repair control signal to the memory array 500 with the redundant columns for repair.
In the embodiment of the application, the central processing unit can be linked with the automatic test machine to acquire the first test result of the automatic test machine in the first test mode or the second test mode, and generate corresponding repair information according to the first test result. And then writing the repair information into the register unit, and controlling the latch control unit to output a repair control signal to repair the memory array with the redundant columns, so that the compatibility of the test flow is further improved.
In one embodiment of the present application, referring to fig. 3, the registering unit 420 may further store a second test result, and the central processor 700 reads the second test result to the registering unit 420 through the first control unit 110 and generates repair information according to the read second test result. Meanwhile, the cpu 700 writes the generated repair information into the register unit 420 of the fourth controller 400, and the register unit 420 also transmits the repair information to the latch control unit 410. The latch control unit 410 generates a repair control signal according to the repair information and transmits the repair control signal to the memory array 500 with the redundant columns for repair.
In one embodiment of the present application, after the whole process of the first test mode is completed, or after the central processing unit receives the repair information sent by the automatic test machine and repairs the memory array with the redundant columns according to the repair information, or after the central processing unit reads the fault information through the status register set in the first control unit and repairs the memory array with the redundant columns according to the fault information, the repaired result can be detected secondarily. For example, referring to FIG. 3, an embodiment of the present application provides a test repair system for a memory, and the fourth controller 400 further includes a test control unit 430 for detecting a repair result after the repair of the memory array is completed.
During the start-up secondary test, the test control unit 430 locks the fault information of the previous repair or the information written from the central processor 700 by a control signal (se_enable) so that the tested memory is in the repaired state. After the secondary test is completed, comparing the results of the previous test and the secondary test to confirm whether the repair is successful. If the repair is confirmed to be successful, the test repair system of the memory is controlled to enter a first normal working mode. The test repair system of the memory confirms whether the memory array with the redundant columns is repaired successfully or not by comparing the previous test result with the secondary test result, thereby improving the repair accuracy and reducing the repair error.
In one embodiment of the present application, referring to fig. 3, the first controller 100 further includes a data synchronization unit 130, and when the first controller 100 and the central processor 700 perform data interaction through a bus, the data synchronization unit 130 performs synchronization processing on the data.
In the embodiment of the present application, the data synchronization unit 130 is a data synchronization processing unit, where in the first test mode, the test clock of the second controller 200 is derived from an external passive crystal oscillator clock (24 MHz), the first control unit 110 uses a high-speed PLL clock (192 MHz), and when the second controller 200 interacts with the first control unit 110, it is necessary to process data in a clock domain crossing synchronization manner, and add a delay unit. In the second test mode, the APB bus does not operate, and the test clock of the second controller 200 uses the specific frequency clock (10 MHz) output from the automatic test equipment 600, and the data does not need to be synchronized.
In one embodiment of the present application, referring to fig. 3, the second controller 200 includes a test vector generator 210, a state machine 220 and a comparator 230, the test vector generator 210 generates a third test control signal according to an algorithm model, the comparator 230 compares and analyzes and outputs a second test result, the state machine 220 is used for controlling the test vector generator 210 to generate the third control signal and to traverse the memory array 500 with redundant columns in parallel through the third control signal, the third controller 300 is built with the algorithm model to analyze whether the tested memory array has a fault dead pixel and the number of dead pixels, and when the tested memory array has a single dead pixel or a single column multiple dead pixel, the fault dead pixel type is a repairable type.
In the embodiment of the present application, the state machine 220 is a self-test finite state machine, and the comparator 230 is a fault address comparator. The state machine 220 is configured to control the test vector generator 210 to generate a third test control signal according to the first/second test control signal and send the third test control signal to the memory array 500 with redundancy columns for parallel traversal according to the algorithm model SMARCHCHKBvcd, and meanwhile, the comparator 230 performs an exclusive-or comparison analysis on the contents to be tested in the memory array 500 with redundancy columns to generate a corresponding second test result and send the second test result to the third controller 300. The third controller 300 is built with an algorithm model for analyzing and diagnosing whether there are defective pixels and the number of defective pixels in the currently tested memory array, and the type information of the fault represented by the two combined signals (repairable _h, repair_data_force) is output to the first controller 100. If the single bad point or the single-row multi-bad point is detected, outputting a repairable mark, otherwise outputting unrepairable mark information.
The complementation of the above dual test modes is that the second test mode flow is performed by the automatic test machine 600 to obtain the corresponding first test result, and then the central processor 700 receives the first test result sent by the automatic test machine 600 and generates the repair information when in use. This information is configured into the fourth controller 400 by the first control unit 110. For the selection of repair information, the test repair system of the memory automatically monitors the current flow of which test mode is in, and outputs the selected repair information to the memory array 500 with redundant columns. When the cpu 700 writes the repair information into the fourth controller 400, the repair information written by the cpu 700 is selected to be output to the memory array with redundant columns 500, and when the first test mode flow is started, the repair information generated after the end of the first test mode is output to the memory array with redundant columns 500.
Referring to fig. 4, a flowchart of test repair of a memory according to an embodiment of the present application is shown in fig. 4, where after a system power-on reset is initialized, it is determined whether to enter a second test mode. If the second test mode is entered, the second controller 200 traverses the memory array 500 with redundant columns through the third test control signal, and after the test is completed, the second controller 200 feeds back the first test result to the automatic test machine 600 through the first controller 100.
If the second test mode is not entered, continuing to judge whether to enter the first test mode. If the first test mode is not entered, the first normal working mode is directly entered. If the first test mode is entered, the fault information obtained by the test is sent to the register unit 420 for latching and the status register set in the first control unit 110. After the first test mode is completed, the central processor 700 accesses each status register set in the first control unit 110 through the APB bus, and reads the fault information therefrom. It is determined whether the memory array 500 with redundant columns is faulty or after repair is faulty. If the fault is judged to exist, the normal working mode II is entered. If no fault exists or no fault exists after repair, judging whether the repair result is subjected to secondary detection. If the secondary detection is not performed, the normal working mode I is directly entered. If the secondary detection is performed, judging whether to use the test result of the second test mode. If the test result of the second test mode is used, the central processor 700 writes the first test result into the fourth controller 400, and the test control unit 430 controls the latch control unit 410 to perform the second test, compares the result of the second test with the result of the second test mode to confirm whether the repair is successful, and enters the normal operation mode one if the repair is successful, and if the test result of the second test mode is not used, the test control unit 430 controls the latch control unit 410 to perform the second test, compares the result of the second test with the result of the first test mode to confirm whether the repair is successful, and enters the normal operation mode one if the repair is successful.
Referring to fig. 5, a flowchart of a method for testing and repairing a memory according to an embodiment of the present application is shown, which is applied to the system for testing and repairing a memory according to the foregoing embodiment, and as shown in fig. 5, includes:
s500, when the memory is in the first test mode, a first test control signal is generated, and when the memory is in the second test mode, a second test control signal is generated.
S510, generating a third test control signal according to the first/second test control signals, wherein the third test control signal comprises a test vector sequence and an address read-write control signal.
S520, after traversing the test memory array under the third test control signal, feeding back and outputting the first test result, and comparing and analyzing and outputting the second test result, wherein the second test result comprises the current test address and the failure bitmap.
S530, analyzing the second test result to obtain fault information, wherein the fault information comprises fault dead point types, fault bit numbers and dead point addresses.
S540, when the fault dead pixel type is repairable, a repair control signal is output to the memory array, the memory array is repaired in an address reconstruction mode, and the repair control signal comprises a repair enabling signal and a dead pixel address sequence.
The details of the embodiments of the present application are described in the test repair system of the memory in the foregoing embodiments, and will not be described herein.
The embodiment of the application also provides an integrated circuit, which comprises the test repair system of the memory according to any of the previous embodiments.
In the foregoing embodiments, the descriptions of the embodiments are focused on, and the parts of a certain embodiment that are not described or depicted in detail may be referred to in the related descriptions of other embodiments.
Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other manners. The above-described embodiments of the apparatus are exemplary only, and exemplary, the division of the modules or units is merely a logical function division, and there may be additional divisions in actual implementation, exemplary, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection via interfaces, devices or units, which may be in electrical, mechanical or other forms.
The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed over a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional unit in the embodiments of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.
While preferred embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the application.
It will be apparent to those skilled in the art that various modifications and variations can be made to the present application without departing from the spirit or scope of the application. Thus, it is intended that the present application also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.
Claims (10)
1. A test repair system for a memory, comprising:
a memory array with redundant columns;
The first controller comprises a first control unit and a second control unit, wherein the first control unit outputs a first test control signal after receiving a first test signal in a first test mode;
The second controller receives the first/second test control signals and generates a third test control signal, wherein the third test control signal comprises a test vector sequence and an address read-write control signal;
After traversing and testing the memory array under the third test control signal, feeding back and outputting a first test result to the first controller through the second controller, and performing exclusive-or comparison analysis on the content to be tested in the memory array with the redundant columns and the expected value through the second controller to output a second test result, wherein the second test result comprises a current test address and a failure bitmap;
The third controller receives and analyzes the second test result to obtain fault information, and the third controller respectively sends the fault information to the first controller and the fourth controller, wherein the fault information comprises a fault dead point type, a fault bit number and a dead point address;
and the fourth controller is used for receiving and analyzing the fault information, outputting a repair control signal to the memory array when the fault dead pixel type is a repairable type, and repairing the memory array in an address reconstruction mode, wherein the repair control signal comprises a repair enabling signal and a dead pixel address sequence.
2. The test repair system of a memory of claim 1, further comprising:
the central processing unit is connected with the first controller and used for sending the first test signal to the first controller;
the central processing unit receives the fault information output by the first controller.
3. A test repair system for a memory according to claim 2, characterized in that the fourth controller comprises:
the latch control unit is used for analyzing the fault information and outputting the repair control signal to the memory array when the fault information is of a repairable type;
And the registering unit is used for latching the fault information when the fault information is of a repairable type.
4. The test repair system of a memory of claim 3 wherein the fourth controller further comprises:
And the test control unit detects a repair result after the memory array is repaired.
5. A test repair system for a memory as in claim 3, wherein:
the register unit receives the repair information written by the central processing unit through the first control unit, and the latch control unit receives the repair information and generates the repair control signal;
the central processing unit also reads the second test result from the register unit through the first control unit.
6. A memory test repair system according to any one of claims 1-5, wherein:
the central processing unit is also used for receiving a first test result obtained by the test machine from the second control unit and generating the repair information, and the second test control signal is sent by the test machine.
7. The test repair system of claim 2 wherein the first controller further comprises:
And the data synchronization unit is used for performing synchronization processing on data when the first controller and the central processing unit perform data interaction through a bus.
8. A memory test repair system according to any one of claims 1-5, wherein:
the second controller comprises a test vector generator and a comparator, wherein the test vector generator generates the third test control signal according to an algorithm model, and the comparator compares and analyzes the second test result;
And the third controller is internally provided with the algorithm model and is used for analyzing whether the tested memory array has fault dead points and the number of the dead points, and if the tested memory array has single dead points or single-column multi-dead points, the fault dead points are of a repairable type.
9. An integrated circuit comprising a test repair system for a memory according to claims 1-8.
10. A method for testing and repairing a memory, which is applied to the system for testing and repairing a memory according to claims 1-8, comprising the steps of:
when the memory is in a first test mode through analysis, a first test control signal is generated; generating a second test control signal when the memory is in a second test mode through analysis;
Generating a third test control signal according to the first/second test control signals, wherein the third test control signal comprises a test vector sequence and an address read-write control signal;
After traversing and testing the memory array under the third test control signal, feeding back and outputting a first test result to a first controller through a second controller, and performing exclusive-or comparison analysis on the content to be tested in the memory array with the redundant array and an expected value through the second controller to output a second test result, wherein the second test result comprises a current test address and a failure bitmap;
Analyzing the second test result to obtain fault information, and respectively sending the fault information to the first controller and the fourth controller through a third controller, wherein the fault information comprises a fault dead point type, a fault bit number and a dead point address;
When the fault dead pixel type is a repairable type, a repair control signal is output to the memory array, the memory array is repaired in an address reconstruction mode, and the repair control signal comprises a repair enabling signal and a dead pixel address sequence.
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| KR20220084994A (en) * | 2020-12-14 | 2022-06-21 | 에스케이하이닉스 주식회사 | Memory system including memory device performing target refresh |
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| KR100331281B1 (en) * | 1999-10-20 | 2002-04-06 | 박종섭 | Redundant memory cell reparing circuit of a memory device |
| KR20160148347A (en) * | 2015-06-16 | 2016-12-26 | 에스케이하이닉스 주식회사 | Self repair device and method |
| KR20170048892A (en) * | 2015-10-27 | 2017-05-10 | 에스케이하이닉스 주식회사 | Compensation circuit and method for compensating |
| CN109390029B (en) * | 2017-08-10 | 2021-07-27 | 北京兆易创新科技股份有限公司 | Method and device for automatically repairing word line fault of NOR type memory array |
| KR102697631B1 (en) * | 2019-10-28 | 2024-08-23 | 삼성전자주식회사 | Memory device varying repair unit and repair method thereof |
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| KR20220084994A (en) * | 2020-12-14 | 2022-06-21 | 에스케이하이닉스 주식회사 | Memory system including memory device performing target refresh |
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