CN118567703B

CN118567703B - SPI interface chip configuration system and method

Info

Publication number: CN118567703B
Application number: CN202410662103.8A
Authority: CN
Inventors: 刘迪; 王竹刚; 韩霜雪; 饶家宁; 王静
Original assignee: National Space Science Center of CAS
Current assignee: National Space Science Center of CAS
Priority date: 2024-05-27
Filing date: 2024-05-27
Publication date: 2025-02-28
Anticipated expiration: 2044-05-27
Also published as: CN118567703A

Abstract

The present invention discloses a SPI interface chip configuration system and method, which is implemented based on a field programmable gate array (FPGA), and includes: a command execution module for detecting and reading the output of an instruction code table using a state machine, performing command recognition on the output instruction code according to the agreed format in the instruction code table, jumping to the corresponding state, and extracting the corresponding operand, interacting with an SPI timing control module based on the recognized instruction code and the extracted operand, and completing the jump to the next state according to the jump condition in the current state; and an SPI timing control module for configuring the SPI interface chip according to the instruction code and the operand. For different chips with a standard SPI serial universal interface, the present invention only needs to maintain a ROM instruction code table and some macro definition parameters. The design difficulty and time cost of developers are greatly reduced.

Description

SPI interface chip configuration system and method

Technical Field

The present invention relates to the field of interface configuration technologies, and in particular, to a system and a method for configuring an SPI interface chip.

Background

With the rapid development of the electronic industry, the integration level of electronic chips is higher and higher, and the functions are stronger and stronger. Typically, such AD/DA chips have a four-wire or three-wire serial SPI (SERIAL PERIPHERAL INTERFACE ) interface, allowing for programming and readback of the chip internal register parameters. However, the number of registers in the chip is large (tens or hundreds), and the control is complicated. The existing configuration method aims at different chips, needs to modify a large amount of design codes every time, has poor portability, inflexible configuration and single function, and needs to design a flexible and universal configuration method.

Disclosure of Invention

The invention aims to overcome the defects of the prior art, and provides an SPI interface chip configuration system and an SPI interface chip configuration method so as to realize the flexibility and the universality of SPI interface chip configuration.

In order to achieve the aim, the invention provides an SPI interface chip configuration system which is realized based on a Field Programmable Gate Array (FPGA), and comprises a command execution module and an SPI time sequence control module, wherein,

The command execution module is used for detecting and reading the output of the command code table by using a state machine, carrying out command identification on the output command code according to a contracted format in the command code table, jumping to a corresponding state, extracting a corresponding operand, interacting with the SPI time sequence control module based on the identified command code and the extracted operand, and completing the jumping of the next state according to the jumping condition in the current state, wherein the command code table is pre-stored in a ROM, and the bit widths of the command code and the operand and the depth of the command code table are defined according to the type and the project requirement of an SPI interface chip;

the SPI time sequence control module is used for interacting with the command execution module and configuring the SPI interface chip according to the instruction codes and the operands.

As an improvement of the system, the instruction codes in the instruction code table comprise part or all of a write register command, a waiting command, a read-back monitoring command, a read-back checking command and a jump command.

As an improvement of the above system, the command execution module is specifically configured to initiate an SPI configuration request to the SPI timing control module when the instruction code is a write register command, a read-back check command, or a read-back monitor command, and perform ROM addressing after receiving a notification that the current register configuration is completed;

The SPI timing control module is particularly used for interacting with the SPI interface chip when the SPI configuration request is detected, completing the read-write operation of the current register, and notifying the command execution module when the current register configuration is completed.

As an improvement of the system, the system also comprises a data selector and a serial port online debugging module, wherein,

The data selector is used for receiving a serial port online debugging enabling signal, and not enabling the serial port online debugging module when the configuration needs to be circularly refreshed;

the serial port online debugging module is used for completing the writing-in and the reading-back of the registers through the serial port and carrying out online modification on certain registers in real time;

the command execution module is also used for interacting with the SPI time sequence control module through the data selector, executing a waiting command after the last register is configured when the configuration is needed to be circularly refreshed, executing a jump command to jump to an address in the ROM where the required refreshing register is located after the waiting time reaches a preset value, completing the circular refreshing operation, and reading, detecting and executing an instruction code table in the ROM until the configuration of the last register of the SPI interface chip is completed when the configuration is needed to be modified online, and switching to a serial port online debugging mode.

As an improvement of the above system, the command execution module includes a plurality of ROMs, each ROM stores an instruction code table, and a transmission mode matches with an instruction code table;

The command execution module is further configured to detect a reconfiguration request and a current transmission mode, and when the reconfiguration request is detected, reset the state machine, and reset the instruction code table of other modes according to the instruction code table of which the current transmission mode enables matching, wherein the current transmission mode is a transmission mode to be switched.

The invention also provides an SPI interface chip configuration method, based on the SPI interface chip configuration system, comprising:

The state machine of the command execution module detects and reads the output of the ROM instruction code table, carries out command identification on the output instruction code according to the agreed format in the instruction code table, jumps to the corresponding state, and extracts the corresponding operand;

The command execution module interacts with the SPI time sequence control module based on the identified instruction codes and the extracted operands so as to facilitate the SPI time sequence control module to configure the SPI interface chip;

and the state machine of the command execution module completes the jump of the next state according to the jump condition in the current state.

As an improvement of the method, the instruction codes in the instruction code table comprise part or all of a write register command, a waiting command, a read-back monitoring command, a read-back checking command and a jump command.

As an improvement of the above method, the command execution module interacts with the SPI timing control module based on the identified instruction code and the extracted operand, comprising:

when the instruction code is a write register command, a read-back check command or a read-back monitoring command, the command execution module initiates an SPI configuration request to the SPI time sequence control module;

when the SPI timing control module detects an SPI configuration request, the SPI timing control module interacts with an SPI interface chip to finish read-write operation of a current register, and when the current register is configured, the command execution module is notified;

The command execution module performs ROM addressing.

As an improvement of the above method, the method further comprises:

When the cyclic refreshing configuration is needed, the data selector does not enable the serial port to debug the enabling signal on line, after the last register is configured, the state machine executes a waiting command, after the waiting time reaches a preset value, the execution of a jump command jumps to an address in the ROM where the required refreshing register is located, and the cyclic refreshing operation is completed;

When the configuration needs to be modified online, the command execution module reads, detects and executes the instruction code table in the ROM by using the state machine until the last register configuration of the SPI interface chip is completed, and the data selector receives the serial online debugging enabling signal and switches to the serial online debugging mode.

As an improvement of the method, the method further comprises the steps that the command execution module comprises a plurality of ROMs, each ROM stores an instruction code table, and a transmission mode is matched with the instruction code table, and the method further comprises the steps of:

the command execution module detects a reconfiguration request and a current transmission mode, wherein the current transmission mode is a transmission mode to be switched;

When the command execution module detects a reconfiguration request, the state machine is reset, and the matched command code table is enabled according to the current transmission mode, and the command code tables of other modes are reset.

Compared with the prior art, the invention has the advantages that:

1. The proposal of the embodiment of the invention provides a proposal that an instruction code table containing instruction codes and operands is stored in a ROM, then the instruction codes and the operands in the instruction code table are executed by a state machine, thus realizing SPI configuration, and because when different SPI interface chips are configured, only the format of the instruction code table is required to be appointed, based on the requirement of the project and the type of the SPI interface chip, an instruction code table is manufactured again and then is given to a state machine to complete the configuration of the SPI interface chip by using the instruction code table, so that the portability is high, the reusability is high, and the design difficulty and the time cost of a developer can be greatly reduced.

2. According to the scheme provided by the embodiment of the invention, the functions of circularly refreshing the register or carrying out online modification after the configuration is completed are selected according to the actual running environment requirements, and the different running environment requirements are considered.

3. The scheme of the embodiment of the invention completes the switching selection of the instruction code table according to different transmission modes so as to adapt to the defect that the analog devices are inconsistent in performance under different modes and meet the index requirements of projects.

Drawings

FIG. 1 is a schematic diagram of the SPI interface chip configuration system of embodiment 1 of the present invention;

FIG. 2 is a flowchart of an SPI interface chip configuration method of embodiment 2 of the present invention;

fig. 3 is an SPI timing chart of AD9144 in embodiment 3 of the present invention;

fig. 4 is a diagram of an FPGA state machine in embodiment 3 of the present invention.

Detailed Description

The technical scheme of the invention is described in detail below with reference to the accompanying drawings and examples.

Example 1

As shown in fig. 1, the design schematic diagram of the configuration system of the SPI interface chip according to the embodiment of the application is implemented based on an FPGA (Filed Programmable GATE ARRAY, field programmable array), and the FPGA is connected to the SPI interface chip through an SPI bus, so as to complete complex configuration of internal registers of the SPI interface device in the FPGA. The system comprises a command execution module and an SPI time sequence control module.

The command execution module includes a ROM (Read-only Memory) and a state machine.

The ROM is used for storing a pre-agreed instruction code table, each row of the instruction code table comprises instruction codes and corresponding operands, the bit widths of the instruction codes and the operands and the depth of the instruction code table are defined according to the type of SPI interface chips and project requirements, the instruction code table can be stored in coe files of the ROM, and control logic such as a state machine can be described by HDL (Hardware Description Language ) instruction type conditional circulating sentences.

The command execution module is used for detecting and reading the output of the command code table by using the state machine, carrying out command identification on the output command code according to the agreed format in the command code table, jumping to the corresponding state, extracting the corresponding operand, interacting with the SPI time sequence control module based on the identified command code and the extracted operand, and completing the jumping of the next state according to the jumping condition in the current state.

And the SPI time sequence control module is used for interacting with the command execution module and configuring the SPI interface chip according to the instruction codes and the operands.

Specifically, the SPI time sequence control module is used for receiving the read-write command and the configuration content of the command execution module or the serial port online debugging module, completing writing of the SPI interface chip according to the SPI interface chip manual time sequence, and reading back the register content returned by the SPI and sending the register content to the command execution module or the serial port online debugging module.

The state machine can continuously read, analyze and execute the instruction code table, and is used for carrying out command identification, state jump and operation execution according to the appointed format in the instruction code table, so as to complete the functions of writing programming, readback verification, real-time monitoring and the like of the internal register parameters of the SPI interface chip.

Preferably, the instruction codes in the instruction code table comprise part or all of a write register command, a waiting command, a read-back monitoring command, a read-back checking command and a jump command.

Specifically, the command execution module is specifically configured to initiate an SPI configuration request to the SPI timing control module when the instruction code is a write register command, a read-back check command, or a read-back monitor command, and perform ROM addressing after receiving a notification that the current register configuration is completed;

Preferably, when the need of debugging and the like exists, the SPI interface chip configuration system also comprises a serial port online debugging module and a data selector MUX;

the data selector is used for receiving a serial port online debugging enabling signal, and does not enable the serial port online debugging module when the configuration needs to be circularly refreshed;

the command execution module is also used for interacting with the SPI time sequence control module through the data selector, executing a waiting command after the last register is configured when the configuration is needed to be circularly refreshed, and executing a jump command to jump to an address in the ROM where the register is required to be refreshed after the waiting time reaches a preset value to finish the circular refresh operation;

and the serial port online debugging module is used for completing the writing-in and the reading-back of the registers through the serial port and carrying out online modification on certain registers in real time.

Specifically, the serial port online debugging module comprises serial port receiving, serial port analyzing and serial port sending;

The serial port receiving is used for receiving serial port instruction frames sent by the serial port debugging assistant;

the serial port analysis is used for analyzing the serial port instruction frame and extracting the read-write instruction and the configuration content;

and the serial port is used for sending the content read back by the SPI to a serial port debugging assistant for displaying.

Preferably, the command execution module comprises one or more ROM, when the command execution module comprises a plurality of ROM, each ROM can store an instruction code table, and a transmission mode is matched with the instruction code table;

In the scheme of the embodiment 1 of the invention, aiming at different chips with standard SPI serial universal interfaces, only one instruction code table and some macro definition parameters are required to be maintained, and the state machine performs the functions of command identification, state jump and operation execution according to the agreed format in the instruction code table, so that the functions of writing programming, readback verification, real-time monitoring and the like of internal register parameters are completed, and the design difficulty and time cost of developers are greatly reduced. According to the actual running environment requirements, the functions of carrying out cyclic refreshing configuration on the register or carrying out online modification after the configuration is completed are selected, and the different running environment requirements are considered. Switching selection of the instruction code table is completed according to different transmission modes so as to adapt to the defect that the analog devices are inconsistent in performance under different modes and meet the index requirements of projects.

Example 2

Based on the SPI interface chip configuration system described in embodiment 1, this embodiment 2 describes an SPI interface chip configuration method. The method is as shown in fig. 2, and comprises the following steps:

step 201, a state machine of the command execution module detects and reads the output of the ROM instruction code table, carries out command identification on the output instruction code according to the agreed format in the instruction code table, jumps to the corresponding state, and extracts the corresponding operand.

Step 202, the command execution module interacts with the SPI timing control module based on the identified instruction codes and the extracted operands.

And 203, configuring the SPI interface chip by the SPI time sequence control module according to the instruction codes and the operands.

Specifically, when the instruction code relates to a read/write command, the SPI timing control module configures the SPI interface chip according to the content of the operand, namely the register address and the register content.

The instruction codes in the instruction code table comprise a part or all of a register writing command, a waiting command, a read-back monitoring command, a read-back checking command and a jump command, and can be used based on actual needs.

Step 204, the state machine completes the jump of the next state according to the jump condition in the current state.

The following describes the above instruction codes, respectively:

And (3) a register writing command, namely configuring corresponding addresses and contents to the SPI register, and returning the state machine to an initial state after the configuration is completed.

Wait command-wait period, do not make any SPI register configuration. Until the waiting period reaches a preset value (e.g., N ms), the system returns to the initial state and prepares to execute the next instruction. The wait command is effective in that some registers in the device cannot respond immediately after being written, and thus it is necessary to wait for a certain period of time to execute the configuration of the next register. At the same time, the time interval of cyclic refreshing of the on-board registers is also completed by the wait command. The preset value N here may be defined using macro definition parameters;

And (3) reading back the monitoring command, namely writing a corresponding address into the SPI register, and returning to an initial state after the configuration is completed by content DNC (Do not Care). The read-back monitoring command has the function that certain registers can reflect whether the working state of the device is normal or not, and the registers can be written into the dual-port RAM for real-time monitoring by an upper computer.

And (3) reading the check command, namely writing a corresponding address into the SPI register, and bit-ANDed the mask and the read-back content. If the result of the bit AND is different from the expected value, a check needs to be performed again until the check is successful or the check number reaches the upper limit of the set check number (for example M times), the state machine returns to the initial state to prepare to execute the next instruction, wherein M times can be defined by using macro definition parameters.

Jump command, when the jump command is detected, the ROM address is set as the jump address, the state machine returns to the initial state, and the command where the jump address is ready to be executed.

It should be noted that, the above instruction codes are the key points of the present invention, and the configuration of the SPI interface chip is implemented by using these instruction codes singly or in combination, which shows the versatility and reliability of the configuration method of the present invention.

The prior configuration method only gives a register writing command and a register reading command, but after writing of certain registers is finished, the SPI interface chip cannot immediately respond and needs to wait for a while, so the invention designs a waiting command and simultaneously the waiting command also ensures the refreshing requirement.

For some registers, such as register a, register a is written, register B should be equal to C0, but read-back register B is equal to 00, indicating that register B is not responding correctly, requiring a further write through of register a. The method and the device repeatedly generate the requirement of the read-back check command, so the read-back check command is designed.

The invention designs the readback monitoring command because some registers can monitor whether the whole chip or the link works normally or not and the readback content of the registers can be used as remote measurement to be sent to the CPU upper computer for real-time monitoring, namely the requirement of generating the readback monitoring command is met.

The existing configuration method generally finishes one pass, and for the on-board requirement, due to the influence of irradiation environment, some registers need to be continuously refreshed, and some registers cannot be refreshed, and the requirements of waiting commands and jump commands are generated, so the invention designs the requirements of the waiting commands and the jump commands to finish refreshing together. For example, registers share ABCDEF, requiring 5s of a refresh of register CD. 5s is controlled by a wait command, and how to refresh the CD after F is configured is controlled by a jump command.

Specifically, in step 202, the command execution module interacts with the SPI timing control module based on the identified instruction code and the extracted operand, and specifically includes that when the instruction code is a write register command, a read-back check command or a read-back monitor command, the command execution module initiates an SPI configuration request to the SPI timing control module, when the SPI timing control module detects the SPI configuration request, interacts with the SPI interface chip, completes the read-write operation on the current register, and notifies the command execution module when the current register configuration is completed, and the command execution module performs ROM addressing.

Preferably, the configuration modes can be divided into a cyclic refresh configuration mode and an online modification configuration mode according to the operation environment. The former is suitable for on-board on-orbit operation stage, and the latter is suitable for ground test and debugging stage.

When the configuration needs to be modified online, the state machine reads, detects and executes the instruction code table in the ROM until the last register configuration of the SPI interface chip is completed, and the MUX receives the serial port online debugging enabling signal and switches to the serial port online debugging mode.

In actual operation, in the configuration of the ground test stage, the writing and reading of the registers can be completed through a serial port or a VIO debugging IP core of a compiling tool in the initial debugging stage, namely, on-line modification is performed on certain registers in real time, and in the later debugging stage, only fine adjustment is performed on certain registers after ROM configuration is completed once.

By using the scheme of the embodiment of the invention, the functions of circulating refreshing configuration and the like of the register can be realized in the on-board on-orbit running stage, and the functions of one-time ROM configuration, on-line modification and the like can be realized in the ground test and debugging stage.

In some projects, the invention has a plurality of transmission modes, different transmission mode modulation modes and transmission rates are different, and analog devices (such as a transformer, a filter, a modulator and the like) can only perform well for high speed or low speed, and cannot simultaneously consider all transmission modes, so that EVM (vector magnitude error) and power cannot meet project index requirements under single configuration.

After the command code table is matched, step 201 to step 204 are executed to complete the configuration of the SPI interface chip.

In the scheme, the switching selection of the instruction code table is completed according to different transmission modes, when the switching of the transmission modes is detected, the state machine is reset, corresponding ROM configuration parameters are selected according to the current mode, and the reconfiguration of the SPI register is completed, so that the configuration device is suitable for the characteristics of analog devices such as a modulator and meets the index requirements of projects.

The scheme of embodiment 2 of the present invention will be described in detail below by way of a specific example in embodiment 3.

Example 3

In this embodiment 3, a method of configuring the SPI interface chip in embodiment 1 will be described by taking one item as an example. The transmission modes in the project are respectively 8PSK modulation, two-channel rate 2 x 900Mbps, QPSK modulation, single-channel rate 300Mbps, QPSK modulation and single-channel rate 30Mbps. The chip used is AD9144, and the SPI timing of AD9144 is shown in fig. 3.

The communication period of AD9144 can be divided into two phases. In fig. 3, the first phase is an instruction cycle, writing a register address to the device, in synchronization with the rising edges of the first 16 serial clocks SCLK. Whether the operation explicitly occurring at this stage is a read operation (logic 1) or a write operation (logic 0), and register address A [14:0]. The second phase is a data transfer cycle, the instruction word providing information about the register contents to the serial port controller. The serial port supports a three-wire or four-wire interface, the present invention selects a four-wire interface by configuring registers, where SDIO is the input of AD9144, SDO is the output of AD9144,Indicating that the chip select is enabled, active low.

Because the project has three modes, in order to keep good consistency of output power of data transmission in various modes and meet EVM indexes, a state machine and certain key registers need to be reset and reconfigured when different transmission modes are started each time.

The format of coe instruction code tables in ROM can be agreed upon according to the definition of the AD9144 configuration registers as shown in table 1, of course, different chips can agree upon different instruction code tables.

Table 1 format of instruction code table

When the reconfiguration cfg_start is detected to be valid, the ROM instruction code table in the current mode is enabled, and the ROM instruction code tables in the other modes are reset.

Assume that the matching instruction code table in the ROM in the current mode is as follows:

0x01 spi_rw+spi_addr[14:0]spi_wr_data[7:0]

0x02 spi_rw+spi_addr[14:0]chk_pos[7:0]exp_val[7:0]jump_addr[11:0]

The AD9144 chip is configured as in steps 201 to 204 in embodiment 2 using the above instruction code table as follows:

Reading 0x01 by a state machine, recognizing that 0x01 is a WRITE register command according to the format in the table 1, jumping to a REG_WRITE WRITE state, and extracting an operand spi_rw+spi_addr [14:0] spi_wr_data [7:0];

The command execution module sends a configuration request signal to the SPI time sequence control module, and the configuration request signal is sent to the SPI time sequence control module by the spi_rw+spi_addr [14:0] spi_wr_data [7:0 ].

And thirdly, when the SPI timing control module detects that the SPI configuration request signal spi_req sent by the command execution module is valid, splicing the SPI read-write operation signal spi_rw, the SPI register address spi_addr [14:0] and the SPI register content spi_wr_data [7:0] into a 24-bit register, shifting left, and serially outputting to the SDIO. Enabling the spi_done signal when the current register writing is completed, indicating that the transmission is finished, and outputting the spi_done signal to the command executing module.

And fourthly, if the state machine detects that the jump condition spi_done is valid, the ROM address is added with 1 to prepare for addressing the next instruction code, and the state machine returns to the IDLE, otherwise, the state machine continues to be in the REG_WRITE state.

And fifthly, the command execution module continues the addressing of the ROM, the state machine judges that the current command type is a READ-back check command according to the output 0x02 of the ROM, jumps to a REG_READ_CHK state, and extracts an operand spi_rw+spi_addr [14:0], wherein spi_wr_data [7:0] is DNC.

And step six (the same as the step two), the command execution module sends a configuration request signal to the SPI time sequence control module, and the configuration request signal is sent to the SPI time sequence control module by the spi_rw+spi_addr [14:0] spi_wr_data [7:0 ].

And seventhly, when the SPI timing control module detects that the SPI configuration request signal spi_req sent by the command execution module is effective, splicing the SPI read-write operation signal spi_rw, the SPI register address spi_addr [14:0] and the SPI register content spi_wr_data [7:0] into a 24-bit register, shifting left, and serially outputting to the SDIO. When the chip select signal is valid and the chip select signal is currently in the second stage data transmission period, the SDO shift register is used for obtaining 8-bit read-back content spi_rd_data [7:0], and if the current spi_rw is a read operation, the read-back content spi_rd_data [7:0] and the read-back enabling spi_rd_dv are sent to the command execution module.

And eighth step, the state machine jumps to the value_check_pre state according to the valid jump condition READ back enabling spi_rd_dv in the REG_READ_CHK READ back CHECK state, the ROM address remains unchanged, and the state machine jumps to the value_check state unconditionally. In the value_check state, if the CHECK is passed, the ROM address is added with 1to prepare for addressing the next instruction code, the state machine returns to the IDLE, if the CHECK is not passed but the CHECK number reaches the upper limit of the CHECK number, the ROM address is added with 1to prepare for addressing the next instruction code, the state machine returns to the IDLE, and if the CHECK is not passed but the CHECK number does not meet the upper limit of the CHECK number, the ROM address is equal to the jump address jump_addr, namely, the jump_addr line instruction is re-executed.

The state machine has 8 states, shown in FIG. 4, which are IDLE state IDLE, WRITE state REG_WRITE, WAIT state WAIT_MS, READ-BACK CHECK state REG_READ_CHK, CHECK ready state VALUE_CHECK_PRE, CHECK in-CHECK value_CHECK, READ-BACK monitor state REG_READ_BACK and JUMP state JUMP, respectively.

When the state machine is in IDLE, indicating that the current state is IDLE, addressing can be performed from the ROM, and the state machine detects the high 8 bits of the ROM output data, i.e. the instruction codes in table 1.

If the instruction code is 0x01, the state machine jumps to REG_WRITE, in which state the ROM address is incremented by 1 to prepare for addressing the next instruction code if the spi_done is detected to be valid, and the state machine returns to IDLE, otherwise continues in REG_WRITE state.

If the instruction code is 0x02, the state machine jumps to REG_READ_CHK, in which state the ROM address remains unchanged, if the READ-back enable spi_rd_dv is detected to be valid, the state machine jumps to VALUE_CHECK_PRE, otherwise continues in REG_READ_CHK, in which state the ROM address remains unchanged, and the state machine jumps unconditionally to VALUE_CHECK. In the value_check state, if the CHECK is passed, the ROM address is added with 1 to prepare for addressing the next instruction code, the state machine returns to the IDLE, if the CHECK is not passed but the CHECK number reaches the upper limit of the CHECK number, the ROM address is added with 1 to prepare for addressing the next instruction code, the state machine returns to the IDLE, and if the CHECK is not passed but the CHECK number does not meet the upper limit of the CHECK number, the ROM address is equal to the jump address jump_addr, namely, the jump_addr line instruction is re-executed.

If the instruction code is 0x04, the state machine jumps to REG_READ_BACK, in which state, if the READ-BACK enable spi_rd_dv is detected to be valid, the ROM address is incremented by 1 to prepare for addressing the next instruction code, the state machine returns to IDLE, otherwise, continues at REG_READ_BACK.

If the instruction code is 0x08, the state machine jumps to wait_ms, in which state, if the waiting time reaches the preset value, the ROM address is incremented by 1 to prepare for addressing the next instruction code, the state machine returns to IDLE, otherwise, continues at wait_ms.

If the instruction code is 0x10, the state machine unconditionally jumps back to the IDLE state, and the ROM address is equal to the jump address jump_addr.

When the state machine is in the waiting state wait_ms, starting to start the MS timing counter, and stopping counting when the timing counter value reaches a preset value.

When the state machine is in the READ-back check state reg_read_chk, judging whether the check result is equal to the expected result or not, and giving a check passing identifier check_ passed. The verification times are cleared if the verification passes and the state machine is in the value_check_pre, cleared if the verification times reach the upper limit of the verification times and the state machine is in the value_check, and accumulated if the verification does not pass and the state machine is in the value_check_pre. Otherwise, the number of checks remains unchanged. The upper limit max_check_mes defines a parameter for the macro.

When the instruction code is SPI_WRITE/SPI_READ_CHECK/SPI_READ_BACK, the spi_req is enabled, and a request is initiated to the SPI configuration module.

In consideration of different requirements of an on-board on-orbit operation stage and a ground test stage, the chip configuration also provides a refreshing of certain registers in the chip in the on-board on-orbit stage, and a real-time monitoring of the states of certain registers is also required. After all the register configuration is completed, the state machine completes the monitoring of the register through the READ-BACK monitoring command SPI_READ_BACK and the JUMP command SPI_JUMP, and writes the monitored content and address into the dual-port RAM for the CPU to monitor in real time.

In the ground test and debugging stage, early designers need to be familiar with the configuration flow and method of the chip, and later requirements such as correction and output power adjustment of the EVM are required continuously, so that real-time writing and reading of registers are required. In consideration of design universality and implementation complexity, the function of modifying the register on line is realized by adopting simple universal serial communication. The upper computer end only needs to install a serial port assistant, and on-line modification of the register can be completed according to the agreed serial port format. In consideration of transmission reliability, the serial port data needs to be provided with a frame head for synchronization to prevent subsequent instructions from being incapable of being resolved or resolving errors caused by serial port misoperation.

The invention has the following advantages:

(1) The invention has strong portability and high reusability. For different chips with standard SPI serial universal interfaces, only one ROM instruction code table and some macro definition parameters are required to be maintained. The design difficulty and the time cost of the developer are greatly reduced.

(2) The invention takes into account the different operating environment requirements. The on-orbit operation stage can select the cyclic refreshing configuration, the ground verification and debugging stage can select the on-line modification configuration after the configuration is completed.

(3) The invention can adapt to the defect that the analog devices are inconsistent in performance under different modes. Different configuration parameters are selected for different modes to compensate for the non-uniformity of the analog devices.

Finally, it should be noted that the above embodiments are only for illustrating the technical solution of the present invention and are not limiting. Although the present invention has been described in detail with reference to the embodiments, it should be understood by those skilled in the art that modifications and equivalents may be made thereto without departing from the spirit and scope of the present invention, which is intended to be covered by the appended claims.

Claims

1. The SPI interface chip configuration system is realized based on a Field Programmable Gate Array (FPGA), and is characterized by comprising a command execution module and an SPI time sequence control module,

The command execution module is used for detecting and reading the output of the command code table by using a state machine, carrying out command identification on the output command code according to a contracted format in the command code table, jumping to a corresponding state, extracting a corresponding operand, interacting with the SPI time sequence control module based on the identified command code and the extracted operand, and completing the jumping of the next state according to the jumping condition in the current state, wherein the command code table is pre-stored in ROM, the bit widths of the command code and the operand and the depth of the command code table are defined according to the type of an SPI interface chip and the requirement of an item;

the SPI time sequence control module is used for interacting with the command execution module and configuring an SPI interface chip according to the instruction codes and the operands;

The instruction codes in the instruction code table comprise a part or all of a register writing command, a waiting command, a readback monitoring command, a readback checking command and a jump command; the system uses a single instruction code or a combination of the single instruction code and the single instruction code to realize the configuration of the SPI interface chip;

The command execution module is specifically configured to initiate an SPI configuration request to the SPI timing control module when the instruction code is a write register command, a read-back check command, or a read-back monitor command, and perform ROM addressing after receiving a notification that current register configuration is completed;

The SPI timing control module is particularly used for interacting with the SPI interface chip when detecting an SPI configuration request, completing the read-write operation of the current register, and notifying the command execution module when the configuration of the current register is completed;

The system also comprises a data selector and a serial port on-line debugging module, wherein,

2. The SPI interface chip configuration system of claim 1,

3. An SPI interface chip configuration method implemented based on the SPI interface chip configuration system of claim 1, comprising:

4. The SPI interface chip configuration method of claim 3, wherein the instruction codes in the instruction code table comprise part or all of a write register command, a wait command, a read-back monitor command, a read-back check command and a jump command.

5. The SPI interface chip configuration method of claim 4, wherein the command execution module interacts with the SPI timing control module based on the identified instruction code and the extracted operand, comprising:

The command execution module performs ROM addressing.

6. A SPI interface chip configuration method in accordance with claim 3, further comprising:

7. The SPI interface chip configuration method of claim 3, further comprising a command execution module comprising a plurality of ROMs, each ROM storing an instruction code table, a transmission mode matching an instruction code table, the method further comprising: