CN118555002B - A high-speed satellite data transmission method and system with high dynamic rate - Google Patents

Abstract

A high-speed satellite data transmission method and system with high dynamic rate relate to the technical field of satellite communication. How to realize higher-rate and larger-capacity data transmission under the condition of limited on-board hardware resources, bandwidth, power and data transmission time becomes a difficult problem to be solved. The invention provides the following scheme: the high-speed satellite data transmission system with high dynamic rate is realized based on a high-speed satellite data transmission method, and the system comprises: the data processing unit is used for receiving the high-speed data of the load camera through the FPGA module, processing the data to obtain an intermediate frequency signal and outputting the intermediate frequency signal to the high-speed DAC module; the data digital-to-analog conversion unit is used for performing digital-to-analog conversion and outputting the processed intermediate frequency signals; and the data transmission unit is used for sending the broadcast frame and the instruction frame to the FPGA module and receiving the returned instruction response frame and the engineering parameter frame. The method is suitable for realizing Gbps-level high-speed data transmission in the field of utilizing limited power and bandwidth resources in limited data transmission time.

Description

A high-speed satellite data transmission method and system with high dynamic rate

Technical Field

The present invention relates to the technical field of satellite communications.

Background Art

The satellite data transmission system is an important part of the satellite data transmission link. It is responsible for transmitting the data collected or generated by the satellite back to the ground receiving station. This system is crucial for many applications such as remote sensing, communication, and scientific research. With the rapid development of information and communication technology, the requirements for communication speed are getting higher and higher. The existing communication system is difficult to meet the growing communication speed requirements.

At the same time, the requirements of space exploration missions are becoming more and more complex, the accuracy of satellite payload sensors is constantly improving, and the amount of data transmitted in the satellite-to-ground link has greatly increased. The satellite data transmission system faces many problems. The existing data transmission system using fixed modulation cannot meet the demand for high transmission capacity. How to achieve higher-speed and larger-capacity data transmission under the conditions of limited hardware resources, bandwidth, power and data transmission time on the satellite has become a problem that needs to be solved urgently.

Summary of the invention

The present invention aims to solve the problem that the data transmission system using a single modulation method and a fixed data transmission rate in the prior art cannot meet the demand for high transmission capacity. How to achieve higher-speed and larger-capacity data transmission under the conditions of limited hardware resources, bandwidth, power and data transmission time on the satellite has become a difficult problem that needs to be solved urgently.

To solve the above technical problems, the present invention is achieved through the following technical solutions:

Solution 1: The present invention proposes a high-speed satellite data transmission method with a high dynamic rate, and the high-speed satellite data transmission method comprises the following steps:

S1, receiving high-speed data from the payload camera through the FPGA module, processing the high-speed data to obtain an intermediate frequency signal and outputting it to the high-speed DAC module;

S2, using the high-speed DAC module to perform digital-to-analog conversion and output the processed intermediate frequency signal;

S3, sending broadcast frames and command frames to the FPGA module through the central computer module, and receiving command response frames and engineering parameter frames returned by the FPGA module;

The FPGA module includes a clock switching module, a high-speed data receiving module, a digital coding modulation module and a data transmission status monitoring module;

The clock switching module is used to receive the instruction sent by the central machine module to switch to the clock corresponding to the corresponding data transmission rate and select the appropriate modulation mode;

The high-speed data receiving module is used to receive high-speed data from the payload camera and send the high-speed data to the digital coding modulation module;

The digital coding and modulation module is used to receive the data from the high-speed data receiving module, and perform framing, coding, scrambling, IQ branch output, constellation mapping, shaping filtering and digital intermediate frequency modulation processing to obtain a processed digital intermediate frequency signal, and send the digital intermediate frequency signal to the DAC module;

The data transmission status monitoring module is used to monitor the current status of the high-speed satellite data transmission system with high dynamic rate, record the data transmission rate and modulation mode related information in the current state, and return it to the central machine module;

The DAC module is used to receive the digital intermediate frequency signal from the digital coding modulation module, perform digital-to-analog conversion and power adjustment, and output the digital intermediate frequency signal;

The central machine module is used to send broadcast frames and command frames to the FPGA module through the CAN bus, and receive command response frames and engineering parameter frames returned from the FPGA module through the CAN bus;

The digital coding modulation module is implemented by using a 14-bit coding processing module for encoding.

Solution 2: A high-speed satellite data transmission system with a high dynamic rate, which is implemented based on the high-speed satellite data transmission method with a high dynamic rate described in Solution 1. The system includes: a data processing unit, a data digital-to-analog conversion unit, and a data transmission unit;

A data processing unit, used for receiving high-speed data from the payload camera through the FPGA module, processing the high-speed data to obtain an intermediate frequency signal and outputting the intermediate frequency signal to the high-speed DAC module;

A data digital-to-analog conversion unit, used to use the high-speed DAC module to perform digital-to-analog conversion and output the processed intermediate frequency signal;

The data transmission unit is used to send broadcast frames and command frames to the FPGA module through the central computer module, and receive command response frames and engineering parameter frames returned by the FPGA module;

The FPGA module includes a clock switching module, a high-speed data receiving module, a digital coding modulation module and a data transmission status monitoring module;

The clock switching module is used to receive the instruction sent by the central machine module to switch to the clock corresponding to the corresponding data transmission rate and select the appropriate modulation mode;

The high-speed data receiving module is used to receive high-speed data from the payload camera and send the high-speed data to the digital coding modulation module;

The digital coding and modulation module is used to receive the data from the high-speed data receiving module, and perform framing, coding, scrambling, IQ branch output, constellation mapping, shaping filtering and digital intermediate frequency modulation processing to obtain a processed digital intermediate frequency signal, and send the digital intermediate frequency signal to the DAC module;

The data transmission status monitoring module is used to monitor the current status of the high-speed satellite data transmission system with high dynamic rate, record the data transmission rate and modulation mode related information in the current state, and return it to the central machine module;

The DAC module is used to receive the digital intermediate frequency signal from the digital coding modulation module, perform digital-to-analog conversion and power adjustment, and output the digital intermediate frequency signal;

The central machine module is used to send broadcast frames and command frames to the FPGA module through the CAN bus, and receive command response frames and engineering parameter frames returned from the FPGA module through the CAN bus;

The digital coding modulation module adopts 14 coding processing modules to perform parallel coding operations.

Further, a preferred implementation is provided, wherein the digital coding modulation module includes a shaping filter module and a digital intermediate frequency modulation module, and the shaping filter module includes an interpolation module and a shaping filter module;

The interpolation module is used to determine whether interpolation is required in the working state according to the modulation mode output by the clock switching module, and output the interpolation data to the shaping filter module;

The shaping filter module is used to dynamically configure the coefficients corresponding to the shaping filter according to the modulation mode output by the clock switching module, and adopts a multi-channel distributed architecture;

The digital intermediate frequency modulation module is used to match the data output by the shaping filter module, and also adopts a multi-channel distributed architecture, and transmits the obtained digital intermediate frequency modulation signal to the high-speed DAC module.

Furthermore, a preferred implementation is provided, in which the high-speed DAC module is implemented using AD9739A and ADF4350.

Furthermore, a preferred implementation is provided, wherein the AD9739A core adopts a four-channel switch architecture.

Furthermore, a preferred implementation is provided, wherein the high-speed DAC module adopts DDR mode and SDR mode to provide a clock to the FPGA module.

Solution three: A computer device includes a memory and a processor, wherein the memory stores a computer program, and when the processor runs the computer program stored in the memory, the processor executes any one of the methods described in Solution one.

Solution 4: A computer-readable storage medium storing a computer program, wherein the computer program, when executed by a processor, implements the steps of the method described in any one of Solution 1.

The present invention is beneficial in that:

The high-speed satellite data transmission system with high dynamic rate described in the present invention is applicable to the field of satellite communication, can be dynamically adjusted according to different data transmission task requirements, can reasonably arrange link resources, and avoid causing a large waste of link resources;

The high-speed satellite data transmission system with high dynamic rate described in the present invention is applicable to the field of satellite communications and can realize Gbps-level high-speed data transmission by utilizing limited power and bandwidth resources within a limited data transmission time.

The present invention is also applicable to the field of realizing Gbps-level high-speed data transmission by utilizing limited power and bandwidth resources within a limited data transmission time.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is an overall block diagram of a high-speed satellite data transmission system with a high dynamic rate as described in Embodiment 2.

FIG. 2 is a schematic diagram of various modules of the FPGA described in the eleventh implementation mode.

FIG. 3 is a schematic diagram of a shaping filter module according to the eleventh embodiment.

DETAILED DESCRIPTION

In order to make the purpose, technical solutions and advantages of the implementation methods of the present application clearer, the technical solutions in the implementation methods of the present application will be clearly and completely described below in conjunction with the drawings in the implementation methods of the present application. Obviously, the described implementation methods are only part of the implementation methods of the present application, not all of the implementation methods.

Embodiment 1: This embodiment provides a high-speed satellite data transmission method with a high dynamic rate, and the high-speed satellite data transmission method includes the following steps:

S1, receiving high-speed data from the payload camera through the FPGA module, processing the high-speed data to obtain an intermediate frequency signal and outputting it to the high-speed DAC module;

S2, using the high-speed DAC module to perform digital-to-analog conversion and output the processed intermediate frequency signal;

S3. Send broadcast frames and command frames to the FPGA module through the central computer module, and receive command response frames and engineering parameter frames returned by the FPGA module.

Embodiment 2: This embodiment proposes a high-speed satellite data transmission system with a high dynamic rate. The high-speed satellite data transmission system is implemented based on the high-speed satellite data transmission method with a high dynamic rate described in embodiment 1. The system includes: a data processing unit, a data digital-to-analog conversion unit, and a data transmission unit;

A data processing unit, used for receiving high-speed data from the payload camera through the FPGA module, processing the high-speed data to obtain an intermediate frequency signal and outputting the intermediate frequency signal to the high-speed DAC module;

A data digital-to-analog conversion unit, used for performing digital-to-analog conversion and outputting the processed intermediate frequency signal;

The data transmission unit is used to send broadcast frames and command frames to the FPGA module, and receive command response frames and engineering parameter frames returned by the FPGA module.

Implementation method 3: This implementation method is a further limitation of the high-speed satellite data transmission system with a high dynamic rate described in implementation method 2. The FPGA module includes a clock switching module, a high-speed data receiving module, a digital coding modulation module, and a data transmission status monitoring module.

The clock switching module is used to receive the instruction sent by the central machine module to switch to the clock corresponding to the corresponding data transmission rate and select the appropriate modulation mode;

The high-speed data receiving module is used to receive high-speed data from the payload camera and send the high-speed data to the digital coding modulation module;

The digital coding and modulation module is used to receive the data from the high-speed data receiving module, and perform framing, coding, scrambling, IQ branch output, constellation mapping, shaping filtering and digital intermediate frequency modulation processing to obtain a processed digital intermediate frequency signal, and send the digital intermediate frequency signal to the DAC module;

The data transmission status monitoring module is used to monitor the current status of the high-speed satellite data transmission system with high dynamic rate, record the data transmission rate and modulation mode related information in the current state, and return it to the central machine module;

The DAC module is used to receive the digital intermediate frequency signal from the digital coding modulation module, perform digital-to-analog conversion and power adjustment, and output the digital intermediate frequency signal;

The central machine module is used to send broadcast frames and command frames to the FPGA module through the CAN bus, and receive command response frames and engineering parameter frames returned from the FPGA module through the CAN bus.

Implementation method 4. This implementation method is a further limitation of the high-speed satellite data transmission system with a high dynamic rate described in implementation method 3, and adopts a 14-bit coding processing module for encoding to implement the digital coding modulation module.

The digital coding modulation module can be implemented by using a coding processing module that is a multiple of 7. One of the best is a 14-bit coding module that uses the ldpc (8160, 7136) coding method of the CCSDS specification for encoding, and the corresponding right side of the generation matrix is a 511*14511*2 matrix.

Implementation mode 5. This implementation mode is a further limitation of the high-speed satellite data transmission system with high dynamic rate described in implementation mode 2. The digital coding modulation module includes a shaping filter module and a digital intermediate frequency modulation module. The shaping filter module includes an interpolation module and a shaping filter module.

The interpolation module is used to determine whether interpolation is required in the working state according to the modulation mode output by the clock switching module, and output the interpolation data to the shaping filter module;

The shaping filter module is used to adopt a multi-channel distributed architecture to dynamically configure coefficients corresponding to the shaping filter according to the modulation mode output by the clock switching module;

The digital intermediate frequency modulation module is used to match the data output by the shaping filter module, and also adopts a multi-channel distributed architecture, and transmits the obtained digital intermediate frequency modulation signal to the high-speed DAC module.

Implementation method 6: This implementation method further limits the high-speed satellite data transmission system with high dynamic rate described in implementation method 2. The high-speed DAC module is implemented using AD9739A and ADF4350.

Embodiment 7: This embodiment further limits the high-speed satellite data transmission system with high dynamic rate described in embodiment 6. The AD9739A core adopts a four-channel switch architecture.

Implementation method eight: This implementation method further limits the high-speed satellite data transmission system with a high dynamic rate described in implementation method two. The high-speed DAC module adopts DDR mode and SDR mode to provide a clock to the FPGA module.

Embodiment 9: A computer device includes a memory and a processor, wherein the memory stores a computer program, and when the processor runs the computer program stored in the memory, the processor executes the method described in any one of the embodiments 1.

Embodiment 10: A computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the method described in any one of the embodiments 1 are implemented.

Implementation eleven: This implementation provides an example, which is used to explain the above implementations one to ten. The specific example is as follows:

Referring to FIG. 1 to FIG. 3 , this embodiment provides a high-speed satellite data transmission system and method with a high dynamic rate. The specific implementation method is based on the K7 series development platform of Xilinx Company:

The FPGA module uses the K7 series development board of Xilinx to complete all digital signal processing functions including clock rate switching, high-speed data reception, and digital coding modulation; the LUT resources use 80,000 LUTs, and the resource occupancy is about 39%; the BRAM resources occupy about 8.2%; the DSP resources occupy about 10.24%; the xc7k325t device can meet the resource usage requirements and the derating requirements, and at the same time provides a dedicated IP core for configuration, which greatly simplifies the interface design.

The high-speed DAC module uses AD9739A and ADF4350. The AD9739A core adopts a four-channel switch architecture, equipped with DDR and SDR modes, with a bit width of 14 bits and a maximum rate of up to 2.5Gsps. ADF4350 can generate a phase-locked loop with a clock in the range of 1.6GHz-2.5GHz to provide clock for AD9739A.

The FPGA module mainly completes the functions of clock switching, high-speed data reception, digital coding modulation and status monitoring, obtains the processed intermediate frequency signal and outputs it to the high-speed DAC, and transmits the remote control and telemetry signal with the central computer through the CAN bus;

The present invention is described in detail below with reference to the accompanying drawings and specific embodiments:

Embodiment 1:

This embodiment proposes a high-speed satellite data transmission system with a high dynamic rate. This embodiment is better described in conjunction with FIG. 1. The high-speed satellite data transmission system with a high dynamic rate in this embodiment includes an FPGA module, a high-speed DAC module, and a central machine module. This embodiment meets data transmission rates including 300Mbps, 600Mbps, 900Mbps, and 1.2Gbps, and the corresponding modulation modes are QPSK, 8PSK, and 16QAM, respectively.

The FPGA module includes a clock switching module, a high-speed data receiving module, a digital coding modulation module and a data transmission status monitoring module, in conjunction with FIG2 ;

The clock switching module switches to a suitable clock rate and a corresponding modulation mode according to the instruction issued by the central computer, and then receives data from the payload camera through a high-speed data interface. In this embodiment, the high-speed data interface adopts a high-speed GTX interface with a maximum transmission rate of up to 12.5 Gbps, and transmits the data to the digital coding modulation module;

The digital coding and modulation module includes a framing module, a coding module, a scrambling module, an IQ splitting module, a constellation mapping module, a shaping and filtering module, an intermediate frequency modulation module and a data transmission status monitoring module;

The framing module adds corresponding frame header information according to the set AOS framing format, completes the framing function, and transmits the framed data to the encoding module;

The encoding module receives data from the framing module, and performs parallel encoding on the received framing data according to the (8176, 7154) LDPC code specified in the CCSDS standard. The LDPC encoding module uses 14 encoding processing modules for parallel encoding operation. Each encoding processing module multiplies two matrices in the same row of the LDPC generation matrix with the input vector, completes the encoding process of one frame of data after 511 clock cycles, and transmits the encoded data to the scrambling module. It has been verified that the throughput of the encoding module is as high as 3.142 Gbps, which meets the rate requirement set in this embodiment.

After the scrambling module completes the scrambling of each frame of data according to the set primitive polynomial and the initial scrambling phase, a synchronization header is added to the start position of the frame, and the data with the synchronization header added is sent to the IQ splitting module;

The IQ splitting module receives the data from the scrambling module, performs IQ splitting, and transmits the split data to the constellation mapping module;

The constellation mapping module performs constellation mapping according to the modulation mode output by the clock switching module, and transmits the mapped data to the shaping filtering module;

The shaping filter module includes an interpolation module and a shaping filter module. The interpolation module adaptively selects an interpolation multiple according to the ratio of the sampling rate to the symbol rate, performs interpolation processing on the data from the constellation mapping, and transmits the interpolated data to the shaping filter module. The shaping filter module is limited by the inherent delay of the internal functional circuit of the FPGA, adopts a multi-channel distributed architecture, dynamically configures the corresponding shaping filter coefficients according to the modulation mode and clock rate output by the clock switching module, performs shaping filtering processing on the data from the interpolation module, and outputs the multi-channel data to the intermediate frequency modulation module, in conjunction with Figure 3;

The intermediate frequency modulation module includes an intermediate frequency signal generation module and a modulation module. In order to match the multi-channel data output by the shaping filter module, the intermediate frequency generation module adopts a direct digital synthesis module based on a multi-channel parallel architecture. The frequency control word and phase control sub-corresponding formula corresponding to the direct digital synthesis module are:

in, is the frequency control word corresponding to the direct digital synthesis module, is the phase control word corresponding to the direct digital synthesis module, is the set local oscillator frequency, which is 627 MHz in this embodiment. is the sampling frequency of the high-speed DAC, which is 2.4 GHz in this embodiment, is the number of channels, which is 8 in this embodiment. is the corresponding channel serial number. In this embodiment , is the quantization bit width, which is 19 in this embodiment;

The modulation module includes an intermediate frequency modulation module and a parallel-to-serial conversion module. The intermediate frequency modulation module is matched with the multi-channel data output by the intermediate frequency signal generation module, adopts a multi-channel distributed architecture, receives the intermediate frequency data output by the intermediate frequency modulation module and the shaping filter data output by the shaping filter module, and modulates according to the modulation mode output by the clock switching module, and outputs the modulated data to the parallel-to-serial conversion module. In this embodiment, the parallel-to-serial conversion module uses the dedicated hardware module OSERDES in the K7 series chip of Xilinx Company to perform parallel-to-serial conversion of data, and transmits the converted serial data to the high-speed DAC module;

The data transmission status monitoring module is used to monitor the current status of the high-speed satellite data transmission system with high dynamic rate, record the data transmission rate and modulation mode related information in the current state, and return it to the central computer through the engineering parameter frame via the CAN bus;

The high-speed DAC module receives the digital intermediate frequency signal from the digital coding modulation module, performs digital-to-analog conversion and power adjustment, outputs the digital intermediate frequency signal, adopts a dual-channel DDR mode, operates at a clock of 1/4 of the sampling rate, and provides a clock to the FPGA chip at the same time;

The central machine module sends command frames and broadcast frames to the FPGA module via the CAN bus, and receives engineering parameter frames and command response frames returned from the FPGA module via the CAN bus.

Any process or method description in the flowchart described in FIG. 1 or described in other ways herein can be understood as representing a module, fragment or part of a code including one or more executable instructions for implementing the steps of a custom logic function or process, and the scope of the preferred embodiment of the present invention includes other implementations, in which the functions may be performed in a substantially simultaneous manner or in reverse order according to the functions involved, which should be understood by a person skilled in the art of the present invention. The logic and/or steps represented in the flowchart or described in other ways herein illustrate the possible implementation architecture, functions and operations of the apparatus and methods according to various embodiments of the present disclosure. In this regard, each box in the flowchart or block diagram can represent a module, a program segment, or a part of a code, and the above-mentioned module, program segment, or a part of a code contains one or more executable instructions for implementing the specified logic function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in an order different from that marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in reverse order, depending on the functions involved. It is also noted that each box in the block diagram or flowchart, and the combination of boxes in the block diagram or flowchart, can be implemented by a dedicated hardware-based system that performs the specified function or operation, or can be implemented by a combination of dedicated hardware and computer instructions. For example, it can be considered as an ordered list of executable instructions for implementing logical functions, which can be embodied in any computer-readable medium for use by an instruction execution system, device or apparatus (such as a computer-based system, a system including a processor, or other system that can fetch instructions from an instruction execution system, device or apparatus and execute instructions), or used in conjunction with these instruction execution systems, devices or apparatuses.

For the purposes of the present specification, "computer-readable medium" may be any device that can contain, store, communicate, propagate or transmit a program for use in an instruction execution system, device or apparatus or in conjunction with such instruction execution systems, devices or apparatuses. More specific examples (non-exhaustive list) of computer-readable media include the following: an electrical connection portion (electronic device) with one or N wirings, a portable computer disk case (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable and editable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disk read-only memory (CDROM). In addition, the computer-readable medium may even be paper or other suitable medium on which the program may be printed, because the program may be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, interpreting or processing in other suitable ways as necessary, and then stored in a computer memory. It should be understood that various parts of the present invention may be implemented in hardware, software, firmware or a combination thereof. In the above embodiments, N steps or methods may be implemented in software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented using any one of the following technologies known in the art or a combination thereof: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

Those skilled in the art will appreciate that the above are only preferred embodiments of the present invention, and the various embodiments of the present disclosure and/or the features described in the claims may be combined or combined in various ways, even if such combinations or combinations are not explicitly described in the present disclosure. It is not intended to limit the present invention. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art may still modify the technical solutions described in the aforementioned embodiments, or perform equivalent substitutions on some of the technical features therein. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention shall be included in the protection scope of the present invention.

Although preferred embodiments of the present invention have been described, additional changes and modifications may be made to these embodiments by those skilled in the art once the basic inventive concepts are known. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention. Obviously, those skilled in the art may make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims (7)

1. The high-speed satellite data transmission method with high dynamic rate is characterized by comprising the following steps of:

s1, receiving high-speed data from a load camera through an FPGA module, processing the high-speed data to obtain an intermediate-frequency signal, and outputting the intermediate-frequency signal to a high-speed DAC module;

s2, performing digital-to-analog conversion by adopting the high-speed DAC module, and outputting the processed intermediate frequency signal;

s3, sending a broadcast frame and an instruction frame to the FPGA module through the central machine module, and receiving an instruction response frame and an engineering parameter frame returned by the FPGA module;

the FPGA module comprises a clock switching module, a high-speed data receiving module, a digital code modulation module and a data transmission state monitoring module;

The clock switching module is used for receiving the instruction sent by the central machine module, switching to the corresponding clock of the corresponding data transmission rate and selecting a proper modulation mode;

The high-speed data receiving module is used for receiving the high-speed data from the load camera and sending the high-speed data to the digital code modulation module;

The digital code modulation module is used for receiving the data from the high-speed data receiving module, framing, coding, scrambling, IQ branching output, constellation mapping, shaping filtering and digital intermediate frequency modulation processing, obtaining a processed digital intermediate frequency signal, and sending the digital intermediate frequency signal to the DAC module;

The data transmission state monitoring module is used for monitoring the current state of the high-speed satellite data transmission system with high dynamic rate, recording data transmission rate and modulation mode related information in the current state and returning the data transmission rate and modulation mode related information to the central machine module;

The DAC module is used for receiving the digital intermediate frequency signal from the digital code modulation module, performing digital-to-analog conversion and power adjustment, and outputting the digital intermediate frequency signal;

The central machine module is used for sending a broadcast frame and an instruction frame to the FPGA module through the can bus and receiving an instruction response frame and an engineering parameter frame returned from the FPGA module through the can bus;

the digital code modulation module is realized by adopting a 14 code processing module to realize parallel coding;

the digital code modulation module comprises a shaping filter module and a digital intermediate frequency modulation module, wherein the shaping filter module comprises an interpolation module and a shaping filter module;

The interpolation module is used for judging whether interpolation is needed in the working state according to the modulation mode output by the clock switching module and outputting interpolation data to the forming filter module;

The shaping filter module is used for dynamically configuring coefficients corresponding to the shaping filter according to the modulation mode output by the clock switching module by adopting a multi-channel distributed architecture;

The digital intermediate frequency modulation module is used for matching the data output by the shaping filtering module, adopting a multi-channel distributed architecture, and transmitting the obtained digital intermediate frequency modulation signal to the high-speed DAC module.

2. A high-speed satellite data transmission system with high dynamic rate, wherein the high-speed satellite data transmission system is implemented based on the high-speed satellite data transmission method with high dynamic rate according to claim 1, the system comprising: the device comprises a data processing unit, a data digital-to-analog conversion unit and a data transmission unit;

The data processing unit is used for receiving the high-speed data from the load camera through the FPGA module, processing the high-speed data to obtain an intermediate frequency signal and outputting the intermediate frequency signal to the high-speed DAC module;

the data digital-to-analog conversion unit is used for carrying out digital-to-analog conversion by adopting the high-speed DAC module and outputting the processed intermediate frequency signal;

The data transmission unit is used for sending a broadcast frame and an instruction frame to the FPGA module through the central machine module and receiving an instruction response frame and an engineering parameter frame returned by the FPGA module; the FPGA module comprises a clock switching module, a high-speed data receiving module, a digital code modulation module and a data transmission state monitoring module;

The clock switching module is used for receiving the instruction sent by the central machine module, switching to the corresponding clock of the corresponding data transmission rate and selecting a proper modulation mode;

The high-speed data receiving module is used for receiving the high-speed data from the load camera and sending the high-speed data to the digital code modulation module;

The digital code modulation module is used for receiving the data from the high-speed data receiving module, framing, coding, scrambling, IQ branching output, constellation mapping, shaping filtering and digital intermediate frequency modulation processing, obtaining a processed digital intermediate frequency signal, and sending the digital intermediate frequency signal to the DAC module;

The data transmission state monitoring module is used for monitoring the current state of the high-speed satellite data transmission system with high dynamic rate, recording data transmission rate and modulation mode related information in the current state and returning the data transmission rate and modulation mode related information to the central machine module;

The DAC module is used for receiving the digital intermediate frequency signal from the digital code modulation module, performing digital-to-analog conversion and power adjustment, and outputting the digital intermediate frequency signal;

The central machine module is used for sending a broadcast frame and an instruction frame to the FPGA module through the can bus and receiving an instruction response frame and an engineering parameter frame returned from the FPGA module through the can bus;

the digital code modulation module adopts a 14 code processing module to perform parallel code operation;

the digital code modulation module comprises a shaping filter module and a digital intermediate frequency modulation module, wherein the shaping filter module comprises an interpolation module and a shaping filter module;

The interpolation module is used for judging whether interpolation is needed in the working state according to the modulation mode output by the clock switching module and outputting interpolation data to the forming filter module;

The shaping filter module is used for dynamically configuring coefficients corresponding to the shaping filter according to the modulation mode output by the clock switching module by adopting a multi-channel distributed architecture;

The digital intermediate frequency modulation module is used for matching the data output by the shaping filtering module, adopting a multi-channel distributed architecture, and transmitting the obtained digital intermediate frequency modulation signal to the high-speed DAC module.

3. The high-dynamic-rate high-speed satellite data transmission system according to claim 2, wherein the high-speed DAC module is implemented using AD9739A and ADF 4350.

4. The high-dynamic-rate high-speed satellite data transmission system according to claim 3, wherein the AD9739A core adopts a four-way switch architecture.

5. The high-dynamic-rate high-speed satellite data transmission system according to claim 2, wherein the high-speed DAC module employs a DDR mode and an SDR mode for providing clocks to the FPGA module.

6. Computer device comprising a memory and a processor, characterized in that the memory has stored therein a computer program which, when being executed by the processor, performs the method of claim 1.

7. A computer readable storage medium, characterized in that the computer readable storage medium stores a computer program which, when executed by a processor, implements the steps of the method of claim 1.