CN118553800A - A high-efficiency TOPCon battery and preparation method thereof - Google Patents

Abstract

The application discloses a high-efficiency TOPCon battery and a preparation method thereof, and belongs to the technical field of new energy batteries, wherein the high-efficiency TOPCon battery comprises a silicon wafer, the silicon wafer comprises a front surface and a back surface opposite to the front surface, a metallized area and a non-metallized area are alternately arranged on the front surface of the silicon wafer, a first tunneling oxide layer and a first doped polysilicon layer are overlapped and arranged on the metallized area of the silicon wafer, a front electrode is sintered on the metallized area of the silicon wafer, and the projection width of the first tunneling oxide layer and the first doped polysilicon layer on the front surface of the silicon wafer is larger than or equal to the projection width of the front electrode on the front surface of the silicon wafer. The application has the beneficial effects that the front surface of the silicon wafer adopts a selectively doped polysilicon structure, namely, a metallized grid line area adopts a tunneling oxide layer and a high-concentration doped polysilicon structure, and a non-metallized area adopts a suede structure, thereby greatly reducing parasitic absorption and improving short-circuit current.

Description

A high-efficiency TOPCon battery and preparation method thereof

Technical Field

The present invention relates to the technical field of new energy batteries, and more specifically, to a high-efficiency TOPCon battery and a preparation method thereof.

Background Art

In the existing technology, energy is the foundation of the world's economic and social development. In the future, energy demand will grow with the development of the world economy. Fossil energy will still be the main source of energy to power the world economy, but the opportunity for energy structure transformation is coming. Renewable energy is growing rapidly, and photovoltaic power generation, as a sustainable energy alternative, has developed rapidly in recent years.

At present, the mainstream solar cell technologies are IBC cells (interdigitated back contact cells), TOPCON (tunnel oxide passivated contact) cells, PERC cells (passivated emitter and real cell) and heterojunction cells. The core of the tunnel oxide passivated contact cell (TOPCON) is a passivation structure of ultra-thin silicon oxide and doped polysilicon. The selectivity allows the majority carriers to pass through the tunnel oxide layer, which blocks the minority carriers and achieves the separation of the minority carriers and the majority carriers in the back space, greatly reducing the recombination. The highly doped polysilicon is also conducive to the back metallization. Therefore, the TOPCON cell has obvious advantages in the opening voltage and is one of the hot research of high-efficiency cells. However, since the back side needs high-doped polysilicon matching wire mesh metallization, it leads to serious parasitic absorption of long waves, which will seriously affect the short-circuit current. At the same time, the front emitter Auger recombination will also affect the further improvement of the opening voltage. Therefore, the current solar cell conversion efficiency still has a lot of room for improvement.

Summary of the invention

The content of this application is used to introduce concepts in a brief form, which will be described in detail in the detailed implementation section below. The content of this application is not intended to identify the key features or essential features of the technical solution claimed for protection, nor is it intended to limit the scope of the technical solution claimed for protection.

Some embodiments of the present application propose a high-efficiency TOPCon battery and a method for preparing the same to solve the technical problems mentioned in the above background technology section.

As a first aspect of the present application, some embodiments of the present application provide a high-efficiency TOPCon battery, which includes a silicon wafer for providing a carrier for carrier movement; wherein the silicon wafer includes a front side and a back side opposite to the front side, and metallized areas and non-metallized areas are arranged alternately on the front side of the silicon wafer, a first tunneling oxide layer and a first doped polysilicon layer are superimposed on the metallized area of the silicon wafer, and a front electrode is sintered on the metallized area of the silicon wafer, and the width of the projection of the first tunneling oxide layer and the first doped polysilicon layer on the front side of the silicon wafer is greater than or equal to the width of the projection of the front electrode on the front side of the silicon wafer.

Furthermore, the non-metallized area on the front side of the silicon wafer is constructed into a velvet structure.

Furthermore, a second tunneling oxide layer and a second doped polysilicon layer are sequentially stacked on the back side of the silicon wafer.

Furthermore, it also includes a passivation layer, which is arranged on a side of the first doped polysilicon layer and/or the second doped polysilicon layer away from the silicon wafer.

Furthermore, it also includes a back electrode, and the back electrode is a silver electrode.

Furthermore, the width of the projections of the first tunneling oxide layer and the first doped polysilicon layer on the front side of the silicon wafer ranges from 15 microns to 200 microns.

Furthermore, the width of the projection of the front electrode on the front side of the silicon wafer ranges from 15 microns to 30 microns.

Furthermore, the first doped polysilicon layer is a polysilicon layer doped with phosphorus.

Furthermore, the second doped polysilicon layer is a polysilicon layer doped with boron.

As a first aspect of the present application, some embodiments of the present application provide a method for preparing a high-efficiency TOPCon battery, comprising the following steps:

Double-sided polishing of silicon wafers;

Preparing a first tunneling oxide layer and a first doped polysilicon layer on both sides of the silicon wafer so that the first doped polysilicon forms boron-doped polysilicon and forms a PN junction at the same time;

Remove BSG from the front and sides of the silicon wafer;

Remove the polysilicon on the front and sides;

The second tunneling oxide layer and the second doped polysilicon layer are again prepared on both sides of the silicon wafer so that the second doped polysilicon forms phosphorus-doped polysilicon;

Remove PSG from the non-metallic area on the front side;

Remove PSG on the back and sides and perform texturing on the front non-metallic area, remove poly on the back, remove PSG on the front metal area, and remove BSG on the back;

Depositing a passivation layer on the back of the silicon wafer and an anti-reflection layer on the front and back of the silicon wafer;

Metallize the metallization areas on the front and back sides of the silicon wafer.

Furthermore, the step of preparing a first tunnel oxide layer and a first doped polysilicon layer on both sides of a silicon wafer so that the first doped polysilicon forms boron-doped polysilicon and simultaneously forms a PN junction comprises:

Using LP to prepare a first tunneling oxide layer and intrinsic amorphous silicon on both sides of a silicon wafer, wherein the first tunneling oxide layer has a thickness of 1 nanometer to 3 nanometers, and the intrinsic amorphous silicon has a thickness of 180 nanometers to 400 nanometers;

Boron is diffused on the back of the silicon wafer to convert the back of the silicon wafer into boron-doped polysilicon and form a PN junction at the same time, wherein the square resistance range of the back boron diffusion is 200 to 400Ω.

Furthermore, the method of preparing a second tunneling oxide layer and a second doped polysilicon layer on both sides of the silicon wafer again so that the second doped polysilicon forms phosphorus-doped polysilicon includes:

Using LP to prepare a second tunneling oxide layer and intrinsic amorphous silicon on both sides of a silicon wafer, wherein the first tunneling oxide layer has a thickness of 1 to 3 nanometers, and the intrinsic amorphous silicon has a thickness of 100 to 180 nanometers;

Phosphorus is diffused on the front side of the silicon wafer to convert the back side of the silicon wafer into phosphorus-doped polysilicon.

Furthermore, the method for removing PSG from the front non-metallic area comprises:

The PSG in the non-metallic area on the front side is removed by using a laser, wherein the wavelength of the laser is 200-600nm and the frequency is 100-500KHZ.

The beneficial effects of this application are:

1. Use a tunneling polysilicon structure with the emitter on the back of the battery. Add a tunneling oxide layer structure to reduce the doping concentration of the substrate. At the same time, the selectivity of the tunneling structure for carriers greatly reduces the recombination in the emitter area and increases the open circuit voltage.

2. A selectively doped polysilicon structure is used on the front of the silicon wafer, that is, a tunneling oxide layer and a high-concentration doped polysilicon structure are used in the metallized gate line area, and a normal velvet structure is used in the non-metallized area, which greatly reduces parasitic absorption and increases short-circuit current.

BRIEF DESCRIPTION OF THE DRAWINGS

The drawings constituting a part of this application are used to provide a further understanding of this application, so that other features, purposes and advantages of this application become more obvious. The drawings and descriptions of the exemplary embodiments of this application are used to explain this application and do not constitute an improper limitation on this application.

In addition, throughout the drawings, the same or similar reference numerals represent the same or similar elements. It should be understood that the drawings are schematic and that the components and elements are not necessarily drawn to scale.

In the attached picture:

FIG1 is a schematic structural diagram of a high-efficiency TOPCon battery according to an embodiment of the present application;

FIG2 is a step diagram of a method for preparing a high-efficiency TOPCon battery according to an embodiment of the present application;

Meaning of the symbols in the figure:

100. Silicon wafer;

200, a first doped polysilicon layer;

300, a first tunneling oxide layer;

400, front electrode;

500, silicon nitride layer;

600, a second tunneling oxide layer;

700, a second doped polysilicon layer;

800. Back electrode.

DETAILED DESCRIPTION

Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although certain embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided to provide a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are only for exemplary purposes and are not intended to limit the scope of protection of the present disclosure.

It should also be noted that, for ease of description, only the parts related to the invention are shown in the drawings. In the absence of conflict, the embodiments and features in the embodiments of the present disclosure may be combined with each other.

It should be noted that the concepts such as "first" and "second" mentioned in the present disclosure are only used to distinguish different devices, modules or units, and are not used to limit the order or interdependence of the functions performed by these devices, modules or units.

It should be noted that the modifications of "one" and "plurality" mentioned in the present disclosure are illustrative rather than restrictive, and those skilled in the art should understand that unless otherwise clearly indicated in the context, it should be understood as "one or more".

The names of the messages or information exchanged between multiple devices in the embodiments of the present disclosure are only used for illustrative purposes and are not used to limit the scope of these messages or information.

The present disclosure will be described in detail below with reference to the accompanying drawings and in conjunction with embodiments.

As shown in FIG1 , a high-efficiency TOPCon cell according to an embodiment of the present application includes a silicon wafer 100 for providing a carrier for carrier movement; wherein the silicon wafer 100 includes a front side and a back side opposite to the front side, a metallized area and a non-metallized area are arranged alternately on the front side of the silicon wafer 100, a first tunneling oxide layer 300 and a first doped polysilicon layer 200 are superimposed on the metallized area of the silicon wafer 100, a front electrode 400 is sintered on the metallized area of the silicon wafer 100, a width of a projected area of the first tunneling oxide layer 300 and the first doped polysilicon layer 200 on the front side of the silicon wafer 100 is greater than or equal to a width of a projected area of the front electrode 400 on the front side of the silicon wafer 100, the non-metallized area on the front side of the silicon wafer 100 is constructed into a velvet structure, and the first doped polysilicon layer 200 is a polysilicon layer doped with phosphorus.

Specifically, the "front" and "back" referred to in this application refer to: from the light-receiving front to the back of the solar cell, the side close to the light-receiving front is called the "front", and the side close to the back is called the "back". The silicon wafer 100 is N-type single crystal silicon, and the N-type silicon substrate has no boron-oxygen recombination when exposed to light, which reduces the photo-induced attenuation and thermally assisted light-induced attenuation to a certain extent. The front of the silicon wafer 100 in this application is provided with metallized areas and non-metallic areas arranged alternately, and the metal area refers to the metallized gate line area, and a front electrode 400 is sintered on the metallized area of the silicon wafer 100. A first tunneling oxide layer 300 and a first doped polysilicon layer 200 are superimposed on the metallized gate line area, and a normal velvet structure is constructed in the non-metallized area, which greatly reduces the need for high-doped polysilicon matching wire mesh metallization on the back of the battery, resulting in a phenomenon of more serious parasitic absorption of long waves, and improves the short-circuit current.

More specifically, the first tunneling oxide layer 300 is a silicon oxide layer, which utilizes the quantum tunneling effect to allow electrons to pass smoothly and prevent the recombination of holes. The full-area passivation surface makes the silicon/metal contact interface non-existent, which is beneficial to improving the open circuit voltage Voc, and the full-area collection of carriers reduces the lifetime sensitivity, which is beneficial to improving the fill factor FF; it blocks the passage of minority carriers while allowing majority carriers to pass easily without obstacles, thus reducing recombination. The carrier recombination on the surface of the silicon wafer 100 can be suppressed, and the minority carrier lifetime of the silicon wafer 100 and the open circuit voltage of the battery can be improved. The carrier selective collection passivation contact structure can be applied to the entire surface of the battery without opening holes to form local passivation contacts, which not only simplifies the manufacturing process, but also the carriers only need to be transported in one-dimensional direction without additional lateral transmission, so a higher fill factor can be obtained.

The width of the projection of the first tunneling oxide layer 300 and the first doped polysilicon layer 200 on the front of the silicon wafer 100 is in the range of 15 microns to 200 microns. The width of the projection of the front electrode 400 on the front of the silicon wafer 100 is in the range of 15 microns to 30 microns. The reason why the width of the projection of the first tunneling oxide layer 300 and the first doped polysilicon layer 200 on the front of the silicon wafer 100 is greater than or equal to the width of the projection of the front electrode 400 on the front of the silicon wafer 100 is that the front electrode 400 needs to be sintered in the metallization area where the first tunneling oxide layer 300 and the first doped polysilicon layer 200 are located, and the current process cannot make the width of the projection of the front electrode 400 on the front of the silicon wafer 100 greater than the width of the projection of the first tunneling oxide layer 300 and the first doped polysilicon layer 200 on the front of the silicon wafer 100.

A pyramid-shaped velvet structure is formed on the top surface of the silicon wafer 100 by using a copper metal catalytic etching method. Since the pyramid velvet has a certain angle with the incident angle of sunlight, it allows sunlight to enter the battery again after reflection, which can increase the amount of sunlight entering the battery. According to the light trapping principle, when light is incident on a slope at a certain angle, the light will be reflected to a slope at another angle, forming secondary or multiple absorption, thereby increasing the light absorption rate, and ultimately can increase the photocurrent density, effectively improving the photoelectric conversion efficiency of the battery.

More specifically, the back of the silicon wafer 100 is sequentially stacked with a second tunneling oxide layer 600 and a second doped polysilicon layer 700. The second doped polysilicon layer 700 is a polysilicon layer doped with boron. The P+ layer formed by diffusing boron into the silicon wafer 100 is used to form a PN junction. The emitter of the battery cell is set on the back of the battery, and the tunneling oxide layer structure is added to reduce the doping concentration of the substrate. At the same time, the selectivity of the tunneling structure to carriers greatly reduces the recombination of the emitter region and improves the open circuit voltage of the battery.

In a specific embodiment, the TOPCon cell further includes a passivation layer, which is disposed on the side of the first doped polysilicon layer 200 and/or the second doped polysilicon layer 700 away from the silicon wafer 100. Providing a passivation layer on the side of the first doped polysilicon layer 200 and the second doped polysilicon layer 700 away from the silicon wafer 100 can effectively reduce the surface recombination rate of the silicon wafer 100 and increase the secondary reflection of light.

Specifically, the passivation layer includes an aluminum oxide layer and a silicon nitride layer 500 on the back. The aluminum oxide layer can effectively reduce the recombination phenomenon on the back of the silicon wafer 100 and increase the secondary reflection. A layer of aluminum oxide is plated on the back of the silicon wafer 100 using ALD equipment to improve the passivation and impurity absorption effect on the surface of the silicon wafer 100. It mainly uses the reaction of gaseous Al(CH3)3 with water vapor (H2O) to generate Al(OH)3, which adheres to the surface of the silicon wafer 100 and produces methane gas at the same time. The front and back of the silicon wafer 100 are provided with a silicon nitride layer 500, which is mainly to reduce surface reflection and improve the conversion efficiency of the battery. A layer of silicon nitride anti-reflection film is deposited on both the front and back sides of the silicon wafer 100. The thin film interference principle can reduce the reflection of light. Specifically, the silicon nitride anti-reflection film is prepared using PECVD equipment. The sample is heated to a predetermined temperature by glow discharge, and then an appropriate amount of reaction gases SiH4 and NH3 are introduced. The gases undergo a series of chemical reactions and plasma reactions to form a solid film, namely a silicon nitride layer 500, on the surface of the silicon wafer 100.

In a specific embodiment, the TOPCon battery further includes a back electrode 800, and the back electrode 800 is a silver electrode. That is, the TOPCon battery includes a front electrode 400 and a back electrode 800, and the front electrode 400 and the back electrode 800 are respectively arranged on both sides of the silicon wafer 100. The back electrode 800 is a silver electrode. The front electrode 400 is a silver electrode or an aluminum electrode. Metal electrodes are prepared by screen printing or sintering on the front and back of the silicon wafer 100. The above-mentioned electrode material configuration can obtain better conductive performance and connection tension between the silicon wafer 100, while improving the conductive effect, improving the structural stability of the battery.

As shown in FIG. 2 , another embodiment of the present application provides a method for preparing a high-efficiency TOPCon battery, comprising the following steps:

S100, performing double-sided polishing on the silicon wafer 100.

S200 , preparing a first tunneling oxide layer 300 and a first doped polysilicon layer 200 on both sides of the silicon wafer 100 so that the first doped polysilicon forms boron-doped polysilicon and forms a PN junction at the same time.

S300 , removing BSG on the front and side surfaces of the silicon wafer 100 .

S400, removing the polysilicon on the front and side surfaces.

S500 , preparing a second tunneling oxide layer 600 and a second doped polysilicon layer 700 on both sides of the silicon wafer 100 again so that the second doped polysilicon forms phosphorus-doped polysilicon.

S600, remove the PSG in the non-metallic area on the front side.

S700, remove the PSG on the back and sides and perform texturing on the non-metallic area on the front, remove the poly on the back, remove the PSG on the metal area on the front, and remove the BSG on the back.

S800 , depositing a passivation layer on the back side of the silicon wafer 100 and depositing an anti-reflection layer on the front side and the back side of the silicon wafer 100 .

S900 , metallizing the metallization areas on the front and back sides of the silicon wafer 100 .

Specifically, in step S100, the silicon wafer 100 is double-sided polished using an alkali solution. In step S200, the first tunneling oxide layer 300 and intrinsic amorphous silicon are prepared on both sides of the silicon wafer 100 using LP, wherein the first tunneling oxide layer 300 has a thickness of 1 nanometer to 3 nanometers, and the intrinsic amorphous silicon has a thickness of 180 nanometers to 400 nanometers. Boron element diffusion is performed on the back side of the silicon wafer 100 to transform the back side of the silicon wafer 100 into boron-doped polysilicon and form a PN junction at the same time, wherein the back side boron diffusion square resistance ranges from 200 to 400Ω.

In step S300 and step S400, chain BSG etching is used to remove the oxide layer at the edge and front of the silicon wafer 100 to expose the plated Poly silicon. During the etching process, the silicon oxide layer on the back of the battery is protected by a water film, and then the silicon wafer 100 is processed by trench etching. The silicon oxide on the back can be used as a mask layer to protect the Poly-Si film on the back, and the Poly-Si film on the edge and front is corroded and removed by the etching solution.

In step S500, the method of preparing the second tunneling oxide layer 600 and the second doped polysilicon layer 700 on both sides of the silicon wafer 100 again so that the second doped polysilicon forms phosphorus-doped polysilicon includes: using LP to prepare the second tunneling oxide layer 600 and intrinsic amorphous silicon on both sides of the silicon wafer 100, wherein the first tunneling oxide layer 300 has a thickness of 1 nanometer to 3 nanometers, and the intrinsic amorphous silicon has a thickness of 100 nanometers to 180 nanometers. Phosphorus is diffused on the front side of the silicon wafer 100 so that the back side of the silicon wafer 100 is converted into phosphorus-doped polysilicon.

In step S600, a laser is used to remove the PSG in the front non-metallic area, wherein the wavelength of the laser is 200-600 nm and the frequency is 100-500 KHZ.

It can be seen from the above steps that after the phosphorus diffusion in step S500, SE is applied to the back side of the silicon wafer 100 to form an N++ heavily doped area, and then the polysilicon plating on the front side of the silicon wafer 100 is directly removed; heavy doping is performed in the wire mesh metallization area through laser selective doping to reduce the excessive contact resistance of the back electrode due to the low doping concentration in the metallization area, and the non-metallization area is shallowly doped to reduce the doping concentration, reduce parasitic absorption, increase short-circuit current, and improve the efficiency of the battery.

The high-efficiency TOPCon battery prepared by the preparation method of the high-efficiency TOPCon battery of the present application is compared with the existing technology of the production line, as shown in Table 1 for details:

Table 1

Group Eta/% Uoc/mV Isc/A FF/% Existing technology of production line 26.16 727.5 13.872 86.76 The present invention 26.4 731.6 13.932 86.77 Gap 0.24 4.1 0.06 0.01

As can be seen from Table 1, the efficiency of the TOPCon battery prepared by the present application reaches 26.4%, among which Uoc and Isc are significantly improved, which are 4.2mV and 60mA higher than the existing technical group of the production line. At the same time, the yield is on par with the production line, which is in line with expectations.

The above descriptions are only some preferred embodiments of the present disclosure and an explanation of the technical principles used. Those skilled in the art should understand that the scope of the invention involved in the embodiments of the present disclosure is not limited to the technical solutions formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the above invention concept. For example, the above features are replaced with (but not limited to) technical features with similar functions disclosed in the embodiments of the present disclosure.

Claims (13)

1. A high efficiency TOPCon battery, characterized in that: the device comprises a silicon wafer and a carrier, wherein the silicon wafer is used for providing carrier movement; the silicon wafer comprises a front surface and a back surface opposite to the front surface, wherein a metallized area and a non-metallized area are alternately arranged on the front surface of the silicon wafer, a first tunneling oxide layer and a first doped polysilicon layer are overlapped and arranged on the metallized area of the silicon wafer, a front electrode is sintered on the metallized area of the silicon wafer, and the projection width of the first tunneling oxide layer and the first doped polysilicon layer on the front surface of the silicon wafer is larger than or equal to the projection width of the front electrode on the front surface of the silicon wafer.

2. The high efficiency TOPCon battery as defined in claim 1, wherein: the non-metallized areas of the front side of the silicon wafer are configured as textured structures.

3. The high efficiency TOPCon battery as defined in claim 1, wherein: and a second tunneling oxide layer and a second doped polysilicon layer are sequentially overlapped on the back surface of the silicon wafer.

4. The high efficiency TOPCon battery as defined in claim 1, wherein: the semiconductor device further comprises a passivation layer, wherein the passivation layer is arranged on one side of the first doped polycrystalline silicon layer and/or the second doped polycrystalline silicon layer away from the silicon wafer.

5. The high efficiency TOPCon battery as defined in claim 1, wherein: the back electrode is a silver electrode.

6. The high efficiency TOPCon battery as defined in claim 1, wherein: the width range of the projection of the first tunneling oxide layer and the first doped polysilicon layer on the front surface of the silicon wafer is as follows: 15 micrometers to 200 micrometers.

7. The high efficiency TOPCon battery as defined in claim 6, wherein: the width range of the projection of the front electrode on the front of the silicon wafer is as follows: 15 micrometers to 30 micrometers.

8. The high efficiency TOPCon battery as defined in claim 1, wherein: the first doped polysilicon layer is a phosphorus element doped polysilicon layer.

9. The high efficiency TOPCon battery as set forth in claim 3, wherein: the second doped polysilicon layer is a boron element doped polysilicon layer.

10. A preparation method of a high-efficiency TOPCon battery is characterized by comprising the following steps: the method comprises the following steps:

Double-sided polishing is carried out on the silicon wafer;

Preparing a first tunneling oxide layer and a first doped polysilicon layer on the two sides of the silicon wafer so that the first doped polysilicon forms boron doped polysilicon and PN junction at the same time;

Removing BSG on the front side and the side of the silicon wafer;

removing polysilicon on the front side and the side;

Preparing a second tunneling oxide layer and a second doped polysilicon layer on the two sides of the silicon wafer again so as to enable the second doped polysilicon to form phosphorus doped polysilicon;

Removing PSG of the front non-metal area;

removing PSG of the back and side surfaces, and performing texturing, back poly removal, front metal region PSG and back BSG removal on the front nonmetallic region;

Depositing a passivation layer on the back surface of the silicon wafer and depositing an antireflection layer on the front surface and the back surface of the silicon wafer;

And metallizing the metallized areas on the front and back sides of the silicon wafer.

11. The method for preparing the efficient TOPCon battery according to claim 10, wherein:

preparing a first tunneling oxide layer and a first doped polysilicon layer on the two sides of the silicon wafer so that the first doped polysilicon forms boron doped polysilicon and forms a PN junction simultaneously comprises the following steps:

preparing a first tunneling oxide layer and intrinsic amorphous silicon on the two sides of a silicon wafer by utilizing LP, wherein the thickness of the first tunneling oxide layer is 1-3 nanometers, and the thickness of the intrinsic amorphous silicon is 180-400 nanometers;

And performing boron element diffusion on the back surface of the silicon wafer to convert the back surface of the silicon wafer into boron-doped polysilicon and form a PN junction, wherein the range of the boron diffusion sheet resistance of the back surface is 200 to 400 omega.

12. The method for preparing the efficient TOPCon battery according to claim 10, wherein:

the method for preparing the second tunneling oxide layer and the second doped polysilicon layer on the two sides of the silicon wafer again so as to enable the second doped polysilicon to form phosphorus doped polysilicon comprises the following steps:

preparing a second tunneling oxide layer and intrinsic amorphous silicon on the two sides of the silicon wafer by utilizing LP, wherein the thickness of the first tunneling oxide layer is 1-3 nanometers, and the thickness of the intrinsic amorphous silicon is 100-180 nanometers;

and performing phosphorus element diffusion on the front surface of the silicon wafer to convert the back surface of the silicon wafer into phosphorus-doped polysilicon.

13. The method for preparing the efficient TOPCon battery according to claim 10, wherein:

The method for removing PSG of the front non-metal area comprises the following steps:

The PSG of the front nonmetallic area is removed by laser, wherein the wavelength of the laser is 200-600nm, and the frequency is 100-500KHZ.