CN118539932A - QC-LDPC decoder - Google Patents

Abstract

The invention discloses a QC-LDPC decoder, belonging to the technical field of decoders; the decoder comprises a plurality of decoding units for parallel decoding, each decoding unit is provided with a round counter, after completing a round of decoding operation, a terminator determines whether the obtained decoding result meets the iteration stop condition, if so, the value of the round counter is reset to 0; otherwise, the value of the round counter is incremented by one; correspondingly, a decoding calculator determines current to-be-processed data according to the value of the round counter, when the value of the round counter is 0, the decoding calculator receives the input of the to-be-decoded data as the current to-be-processed data; when the value of the round counter is not 0, the decoding calculator uses the decoding result of the previous round as the current to-be-processed data; the invention reduces the working time of aligning all decoding units to the execution time of one decoding round, and can reduce the waste of time under the premise of ensuring a fast decoding speed.

Description

A QC-LDPC decoder

Technical Field

The present invention belongs to the technical field of decoders, and more specifically, relates to a QC-LDPC decoder.

Background Art

Social progress has brought about an increasing demand for the capacity and speed of storage devices. As an efficient and powerful linear error correction code with performance close to the Shannon limit, low-density parity-check code (LDPC) has become a reliable means to establish a reliable network space in a noisy physical environment. Quasi-cyclic (QC) LDPC code is a variant of LDPC code. It has a standard code structure that is easy to execute in hardware, so it is widely adopted in various wireless communication standards such as WiFi, WiMax, DVB-S2 and CCSDS. It is also used in the field of data storage, such as solid-state drives. The decoder of LDPC code has been widely studied in terms of code architecture, decoding algorithm and hardware implementation.

High-Level Synthesis (HLS) represents an automated design process that compiles the logical behavior of an algorithm from a high-level description language into the implementation of the corresponding hardware (such as FPGA, DSP, etc.) at the register transfer level (RTL). Using HLS for automated hardware development not only improves productivity, but also increases design flexibility, which makes it widely used in large-scale scenarios that require new functions, such as machine learning, graphics processing, and accelerators in specific fields. The main HLS tools on the market, such as Vivado HLS and Intel HLS, support C/C++ as development languages and describe hardware behavior through additional compilation instructions or directives.

LDPC decoding is a complex and dynamic algorithm that requires variable message passing iterations until the stopping rule is met (i.e., all parity check equations are satisfied). The number of iterations depends on the channel noise, message quantization, and LDPC code rate. The decoding unit is the core of the QC-LDPC iterative decoding process. In order to speed up the iterative decoding and improve the throughput of the entire decoder, multiple decoding units are often used in the prior art to decode in parallel. In the existing HLS design, in order to further speed up the decoding speed, a termination decision device is added inside the decoding unit to reduce the number of decodings. However, the addition of the termination decision device also makes the number of decodings of the decoding unit different. With the parallel and synchronous hardware design, HLS cannot solve the problem of decoding time alignment of all decoding units. The fastest decoding unit must wait for the slowest decoding unit to finish decoding before it can work on the next module, resulting in a waste of time. Based on the above analysis, the hardware implementation efficiency of the QC-LDPC decoder based on HLS still needs to be improved.

Summary of the invention

In view of the above defects or improvement needs of the prior art, the present invention provides a QC-LDPC decoder to solve the technical problem that the prior art cannot reduce the time waste while ensuring a faster decoding speed.

In order to achieve the above-mentioned object, in a first aspect, the present invention provides a QC-LDPC decoder, comprising: a plurality of parallel decoding units;

The decoding unit includes: a decoding calculator, a decoding result memory, a round counter and a terminator; the value of the round counter is initially 0;

The decoding calculator is used to obtain the data to be processed in the current round, decode the data to be processed, obtain the decoding result in the current round, and output it to the decoding result memory for storage; wherein, when the value of the round counter is 0, the decoding calculator uses the data to be decoded as the data to be processed in the current round; when the value of the round counter is not 0, the decoding calculator uses the decoding result in the previous round as the data to be processed in the current round;

The terminator is used to read the decoding result of the current round from the decoding result memory to make a termination decision. If the decoding result meets the stopping decision condition of LDPC or the value in the round counter reaches the preset maximum value, the decoding result memory is controlled to output the decoding result and the value of the round counter is set to 0; otherwise, the value of the round counter is incremented by one; wherein the stopping decision condition is that the result of bitwise XOR of the decoding result is 0.

Further preferably, the decoding calculator comprises: a data calculation memory, n parallel check node calculation units, and m parallel variable node calculation units; m and n are the number of rows and columns of the LDPC decoding base matrix respectively;

The data calculation memory is used to obtain the data to be processed in the current round, and divide the data to be processed into n data blocks, and input them one by one into n check node calculation units to update the check nodes, so as to obtain the data after the check nodes are updated; the data after the check nodes are updated is divided into m data blocks, and input them one by one into m parallel variable node calculation units to update the variable nodes, so as to obtain m decoding data blocks, which constitute the decoding results in the current round, and save them, and output them to the decoding result memory for storage.

Further preferably, the terminator comprises: a termination module and a decision controller;

The termination module includes: a judgment calculation memory; when the current round is the first round, the judgment value of the previous round stored in the judgment calculation memory is 1;

The decision controller is used to obtain the decision value of the previous round from the decision calculation memory, and determine whether the decision value is 0. If so, it is determined that the decoding result of the current round meets the stop decision condition of the LDPC; otherwise, it is determined that the decoding result of the current round does not meet the stop decision condition of the LDPC;

The termination module is used for reading the decoding result of the current round from the decoding result memory when the decoding result of the current round does not meet the stop decision condition of LDPC, backing up the m decoding data blocks in the decoding result based on the LDPC decoding base matrix respectively, and storing the copies of the backed-up decoding data blocks at different positions of the decision calculation memory to form an OMBA memory array; obtaining the kijth data of the copy of the decoding data block stored in the memory block of the i-th row and j-th _column of the OMBA memory array, recorded as the marking data; performing an XOR operation on all the marking data on each column in the OMBA memory array to obtain the corresponding column XOR result, and performing an OR operation on the column XOR results of all columns to obtain the decision value of the current round, and storing it in the decision calculation memory;

The i -th decoded data block in the decoding result is denoted as OMB _i , i =1,2,...,m; the number of copies of OMB _i is the same as the number of non-zero elements in the i - th row of the LDPC decoding base matrix; the copy of OMB _i is stored in the i- th row of the OMBA memory array, and the relative position in the row is consistent with the relative position of the non-zero elements in the i -th row of the LDPC decoding base matrix;

k _ij is a copy of the decoded data block stored in the memory block in the i-th row and j- th column of the OMBA memory array, from which The position number after the current sub-iteration number starts from the position where the data is located and moves right cyclically; is the value of the i- th row and j -th column of the LDPC decoding base matrix; each round includes M sub-iterations; M is the ratio of the number of bits of the data to be decoded to the length n of the base matrix; each sub-iteration corresponds to the decoding process of one bit of the data to be decoded in the current round; j =1,2,...,n.

Further preferably, the QC-LDPC decoder further includes: an input and output module;

The input and output modules include: an input module for caching data to be decoded, and an output module for caching decoding results; the input module includes: a plurality of input buffers; the output module includes: a plurality of output buffers; the number of input buffers, output buffers and decoding units is the same, and there is a one-to-one correspondence between them;

When the value of the round counter is 0, the decoding calculator reads the data to be decoded from the corresponding input buffer as the data to be processed in the current round;

The terminator is used to control the decoding result memory to output the decoding result to the output buffer and set the value of the round counter to 0 when the decoding result in the current round meets the stop decision condition of LDPC or the value in the round counter reaches the preset maximum value.

Further preferably, an input FIFO queue is arranged between the decoding unit and the corresponding input buffer; and an output FIFO queue is arranged between the decoding unit and the corresponding output buffer.

Further preferably, a first global task counter is provided in the input module, a second global task counter is provided in the output module, and a local task counter is provided in each decoding unit;

The local task counter is used to perform an increment operation when the decoding result memory in the decoding unit where it is located outputs a decoding result each time; and when the value of the local task counter reaches a preset local decoding number, the decoding unit where it is located is controlled to stop working;

The first global task counter is used to perform an increment operation when any input buffer outputs a decoding result to the corresponding decoding unit; and when the value of the first global task counter reaches a preset overall decoding quantity, the input module is controlled to stop working;

The second global task counter is used to perform an increment operation when any output buffer receives a decoding result from the corresponding decoding unit; and when the value of the second global task counter reaches a preset overall decoding quantity, the QC-LDPC decoder is controlled to stop working.

In a second aspect, the present invention provides a storage device, comprising the QC-LDPC decoder provided in the first aspect of the present invention.

In general, the above technical solutions conceived by the present invention can achieve the following beneficial effects:

1. The present invention provides a QC-LDPC decoder, which includes a plurality of decoding units for parallel decoding, each of which is provided with a round counter, and the flow of data stream is controlled by using the round counter to record the number of decoding rounds of the decoding unit; specifically, after completing a round of decoding operation, a terminator determines whether the obtained decoding result meets the stop decision condition of LDPC or the value in the round counter reaches a preset maximum value, and if so, the value of the round counter is reset to 0; otherwise, the value of the round counter is incremented by one; correspondingly, the decoding calculator determines whether the decoding result meets the stop decision condition of LDPC or the value in the round counter reaches a preset maximum value. The value of the round counter determines the current data to be processed. When the value of the round counter is 0, the decoding calculator receives the input of the data to be decoded as the current data to be processed; when the value of the round counter is not 0, the decoding calculator uses the decoding result of the previous round as the current data to be processed; through the above operations, the present invention reduces the working time of aligning all decoding units to the execution time of one decoding round, avoiding the situation that the fastest decoding unit waits for the slowest decoding unit to finish decoding before it can proceed to the work of the next module, and can reduce the waste of time while ensuring a faster decoding speed.

2. Furthermore, in the QC-LDPC decoder provided by the present invention, each decoding unit is provided with a terminator for terminating iterative decoding. The terminator backs up the decoding result into multiple copies, and multiple copies of data can be read in parallel during calculation, and the result of XOR and OR calculation is used as the basis for the decoding unit to terminate iterative decoding. By copying multiple copies of the decoding result and constructing an OMBA memory array to achieve extended memory reading, the terminator can read data in parallel from different positions of the OMBA memory array, avoiding the access delay problem caused by the conflict and competition of data access due to limited memory ports when a single decoding data block is calculated in parallel.

3. Furthermore, the QC-LDPC decoder provided by the present invention takes into account that the variable node calculation unit and the terminator inside the decoding unit operate in parallel, and the calculation order of the variable node calculation unit is inconsistent with the calculation order of the terminator. There may be a situation where the result calculated by the terminator uses the old value before the update, and there is a lag of one round. The decision controller in the present invention obtains the decision value of the previous round from the decision calculation memory as the basis for decision. By delaying the decision once, the decoding error influence caused by the lag of one round can be eliminated, thereby ensuring the accuracy of decoding.

4. Furthermore, in the QC-LDPC decoder provided by the present invention, an input FIFO queue is arranged between the decoding unit and the corresponding input buffer; an output FIFO queue is arranged between the decoding unit and the corresponding output buffer, and a hardware FIFO queue is used to buffer the data flow of the input module-decoding unit-output module, thereby significantly improving the decoding throughput of the decoder.

5. Furthermore, the QC-LDPC decoder provided by the present invention counts the number of completed tasks by setting corresponding counters in the input module, output module and decoding unit, so that when the corresponding part completes a certain amount of tasks, it can choose to stop working, which has high flexibility.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a schematic diagram of the structure of a QC-LDPC decoder provided in an embodiment of the present invention.

FIG. 2 is a schematic diagram of the structure of a decoder unit provided in an embodiment of the present invention.

FIG. 3 is a schematic diagram of the structure of a terminator provided in an embodiment of the present invention.

FIG. 4 is a flowchart of a termination decision of a decoding unit provided by an embodiment of the present invention.

DETAILED DESCRIPTION

In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

In order to achieve the above-mentioned object, in a first aspect, the present invention provides a QC-LDPC decoder, comprising: a plurality of parallel decoding units;

The decoding unit includes: a decoding calculator, a decoding result memory, a round counter and a terminator; the value of the round counter is initially 0;

The decoding calculator is used to obtain the data to be processed in the current round, decode the data to be processed, obtain the decoding result in the current round, and output it to the decoding result memory for storage; wherein, when the value of the round counter is 0, the decoding calculator uses the data to be decoded as the data to be processed in the current round; when the value of the round counter is not 0, the decoding calculator uses the decoding result in the previous round as the data to be processed in the current round;

The terminator is used to read the decoding result of the current round from the decoding result memory to make a termination decision. If the decoding result meets the stopping decision condition of LDPC or the value in the round counter reaches the preset maximum value, the decoding result memory is controlled to output the decoding result and the value of the round counter is set to 0; otherwise, the value of the round counter is incremented by one; wherein the stopping decision condition is that the result of bitwise XOR of the decoding result is 0.

In an optional implementation, the decoding calculator includes: a data calculation memory, n parallel check node calculation units, and m parallel variable node calculation units; m and n are the number of rows and columns of the LDPC decoding base matrix respectively;

The data calculation memory is used to obtain the data to be processed in the current round, and divide the data to be processed into n data blocks, and input them one by one into n check node calculation units to update the check nodes, so as to obtain the data after the check nodes are updated; the data after the check nodes are updated is divided into m data blocks, and input them one by one into m parallel variable node calculation units to update the variable nodes, so as to obtain m decoding data blocks, which constitute the decoding results in the current round, and save them, and output them to the decoding result memory for storage.

Preferably, in an optional implementation manner, the terminator includes: a decision controller and a termination module;

The termination module includes: a judgment calculation memory; when the current round is the first round, the judgment value of the previous round stored in the judgment calculation memory is 1;

The decision controller is used to obtain the decision value of the previous round from the decision calculation memory, and determine whether the decision value is 0. If so, it is determined that the decoding result of the current round meets the stop decision condition of the LDPC; otherwise, it is determined that the decoding result of the current round does not meet the stop decision condition of the LDPC;

The termination module is used for reading the decoding result of the current round from the decoding result memory when the decoding result of the current round does not meet the stop decision condition of LDPC, backing up the m decoding data blocks in the decoding result based on the LDPC decoding base matrix respectively, and storing the copies of the backed-up decoding data blocks at different positions of the decision calculation memory to form an OMBA memory array; obtaining the kijth data of the copy of the decoding data block stored in the memory block of the i-th row and j-th _column of the OMBA memory array, recorded as the marking data; performing an XOR operation on all the marking data on each column in the OMBA memory array to obtain the corresponding column XOR result, and performing an OR operation on the column XOR results of all columns to obtain the decision value of the current round, and storing it in the decision calculation memory;

The i -th decoded data block in the decoding result is denoted as OMB _i , i =1,2,...,m; the number of copies of OMB _i is the same as the number of non-zero elements in the i - th row of the LDPC decoding base matrix; the copy of OMB _i is stored in the i- th row of the OMBA memory array, and the relative position in the row is consistent with the relative position of the non-zero elements in the i -th row of the LDPC decoding base matrix;

k _ij is a copy of the decoded data block stored in the memory block in the i-th row and j- th column of the OMBA memory array, from which The position number after the current sub-iteration number starts from the position where the data is located and moves right cyclically; is the value of the i- th row and j -th column of the LDPC decoding base matrix; each round includes M sub-iterations; M is the ratio of the number of bits of the data to be decoded to the length n of the base matrix; each sub-iteration corresponds to the decoding process of one bit of the data to be decoded in the current round; j =1,2,...,n.

In an optional implementation manner, the QC-LDPC decoder further includes: an input and output module;

The input and output modules include: an input module for caching data to be decoded, and an output module for caching decoding results; the input module includes: a plurality of input buffers; the output module includes: a plurality of output buffers; the number of input buffers, output buffers and decoding units is the same, and there is a one-to-one correspondence between them;

When the value of the round counter is 0, the decoding calculator reads the data to be decoded from the corresponding input buffer as the data to be processed in the current round.

The terminator is used to control the decoding result memory to output the decoding result to the output buffer and set the value of the round counter to 0 when the decoding result in the current round meets the stop decision condition of LDPC or the value in the round counter reaches the preset maximum value.

In an optional implementation manner, an input FIFO queue is provided between the decoding unit and the corresponding input buffer; and an output FIFO queue is provided between the decoding unit and the corresponding output buffer.

The input FIFO queue with a buffering function can buffer data that has not yet been decoded, and the output FIFO queue with a buffering function can buffer the decoding results output by the decoding unit that ends decoding early.

In an optional implementation, each module in the decoder can choose not to work after completing a certain task. Specifically, a first global task counter is set in the input module, a second global task counter is set in the output module, and a local task counter is set in each decoding unit;

The local task counter is used to increase the value by one when the decoding result memory in the decoding unit where the local task counter is located outputs a decoding result each time; and when the value of the local task counter reaches the preset local decoding quantity, the decoding unit where the local task counter is located is controlled to stop working;

The first global task counter is used to perform an increment operation when any input buffer outputs a decoding result to the corresponding decoding unit; and when the value of the first global task counter reaches a preset overall decoding quantity, the input module is controlled to stop working;

The second global task counter is used to perform an increment operation when any output buffer receives a decoding result from the corresponding decoding unit; and when the value of the second global task counter reaches a preset overall decoding quantity, the QC-LDPC decoder is controlled to stop working.

In order to further illustrate the QC-LDPC decoder provided by the present invention, a specific embodiment is described in detail below:

The QC-LDPC decoder can be implemented based on programmable logic devices such as FPGA and DSP. The QC-LDPC decoder of this embodiment is implemented based on FPGA.

FIG1 is a diagram showing the overall structure of a multi-unit QC-LDPC decoder with HLS-based iterative decoding that can terminate early, as proposed in this embodiment.

The off-chip memory of FPGA is a high bandwidth memory (HBM). The program on the host side transfers the data to HBM through the Pcie bus and waits for the FPGA decoder to decode it.

Specifically, the QC-LDPC decoder includes: an input-output module and N decoding units;

The input-output module is used to read or write the data to be decoded from the HBM, and specifically includes an input module and an output module. In order to efficiently utilize the interface of the FPGA, burst transmission is used. The input module reads data from the external high-speed memory HBM of the FPGA in batches and synchronously; the output module reads the decoding results and outputs the results to the host in batches and synchronously. Specifically, the input-output module is used to cache the data to be decoded and the decoding results, and includes multiple pairs of input buffers and output buffers; one decoding unit corresponds to a pair of input buffers and output buffers. Each input buffer constitutes an input module, and each output buffer constitutes an output module.

N decoding units are used to decode data. Each decoding unit includes its own decoding calculator and terminator. Data is read by the input module and entered into the decoding unit for decoding. After multiple iterations, it is returned to the output module and output to the HBM to interact with the host.

The multiple decoding units of the QC-LDPC decoder dynamically execute the above process without waiting for the latest unit to finish.

As shown in Figure 2, it is a structural diagram of a single decoding unit. An input FIFO queue is set between the decoding unit and the corresponding input buffer, which is used to cache data between the decoding unit and the corresponding input buffer; an output FIFO queue is set between the decoding unit and the corresponding output buffer, which is used to cache data between the decoding unit and the corresponding output buffer.

The decoding unit includes: a decoding calculator, a decoding result memory, a round counter and a terminator; the value of the round counter is initially 0;

The decoding calculator is used to obtain the data to be processed in the current round, decode the data to be processed, obtain the decoding result in the current round, and output it to the decoding result memory for storage; wherein, when the value of the round counter is 0, the decoding calculator uses the data to be decoded as the data to be processed in the current round; when the value of the round counter is not 0, the decoding calculator uses the decoding result in the previous round as the data to be processed in the current round.

Specifically, the decoding calculator includes: a data calculation memory, n parallel check node calculation units (CNUs), and m parallel variable node calculation units (VNUs); m and n are the number of rows and columns of the LDPC decoding base matrix respectively;

The check node calculation unit is used to update the check nodes of the input data;

The variable node calculation unit is used to update the variable nodes of the input data;

The data calculation memory is used to obtain the data to be processed in the current round, and divide the data to be processed into n data blocks, and input them one by one into n check node calculation units to update the check nodes, so as to obtain n data blocks after the check nodes are updated, which constitute the data after the check nodes are updated; the data after the check nodes are updated are divided into m data blocks, and input them one by one into m parallel variable node calculation units to update the variable nodes, so as to obtain m decoding data blocks (the codeword lengths of the m decoding data blocks are the same), which constitute the decoding results in the current round, and are saved and output to the decoding result memory for storage.

As shown in Fig. 3, the terminator (TM) is used to perform a decision of a termination condition check in the decoding unit. The terminator includes: a termination module and a decision controller;

The termination module includes: judgment calculation memory;

The termination module is used to read the decoding result of the current round from the decoding result memory, back up the m decoding data blocks in the decoding result based on the LDPC decoding base matrix respectively, and store the copies of the backed up decoding data blocks at different positions of the decision calculation memory to form an OMBA memory array; specifically, the i -th decoding data block in the decoding result is recorded as OMB _i , i =1,2,...,m; the number of copies of OMB _i is the same as the number of non-zero elements in the i- th row of the LDPC decoding base matrix; the copy of OMB _i is stored in the i- th row of the OMBA memory array, and the relative position in the row is consistent with the relative position of the non-zero elements in the i-th row of the LDPC decoding base matrix;

Get _{the kijth} data of the decoded data block copy stored in the memory block of the i-th row and j-th column of the OMBA memory array, and record it as the marked data; perform XOR operation on all the marked data on each column in the OMBA memory array to obtain the corresponding column XOR result, and perform OR operation on the column XOR results of all columns to obtain the decision value under the current round, and store it in the decision calculation memory; where kij is the decoded data block _copy stored in the memory block of the i-th row and j- th column of the OMBA memory array, from its The position number after the current sub-iteration number starts from the position where the data is located and moves right cyclically; is the value of the i- th row and j -th column of the LDPC decoding base matrix; each round includes M sub-iterations; M is the ratio of the number of bits of the data to be decoded to the length n of the base matrix; each sub-iteration corresponds to the decoding process of one bit of the data to be decoded in the current round; j =1,2,...,n.

The decision controller is used to obtain the decision value of the previous round from the decision calculation memory (when the current round is the first round, the decision value of the previous round is recorded as 1), and determine whether the decision value is 0. If so, it is determined that the decoding result of the current round meets the LDPC stop decision condition; otherwise, it is determined that the LDPC stop decision condition is not met.

It should be noted that by copying multiple copies of the decoding results and building an OMBA memory array to achieve extended memory reading, the terminator can read data in parallel from different locations of the OMBA memory array, avoiding the access delay problem caused by data access conflicts and competition due to limited memory ports when a single decoded data block is calculated in parallel.

As shown in FIG4 , the decision process performed by the decision controller is as follows:

First, the column XOR results of all columns of the OMBA memory array are ORed in parallel, and the result of the ORed operation is saved in a temporary register of the decision calculation memory as a decision value F for deciding whether to terminate the exit;

F = Res ₁ | Res ₂ | Res ₃ |…| Res _n

Wherein, Res _j is the column XOR result of the i -th column of the OMBA memory array, j = 1, 2, ..., n.

The decision to terminate decoding in the current round is based on the decision value in the previous round. The decision machine will first read the decision value F in the previous round from the temporary register. If F is 0, it means that decoding can be terminated. Otherwise, the decision value F of the current iteration will be calculated and written into the temporary register, and the next iteration decoding will continue.

The process of using the decision value F in the previous round as the basis for decision is called delayed decision. Taking into account that the variable node calculation unit and the terminator in the decoding unit operate in parallel, the calculation order of the variable node calculation unit is inconsistent with the calculation order of the terminator. There may be a situation where the result calculated by the terminator uses the old value before the update, and there is a lag of one round. By delaying the decision once, the decoding error caused by the lag of one round can be eliminated.

Specifically, in this embodiment, the design process of dynamic execution of the decoding unit includes:

Define a decoding unit class, which contains: array member decoding data blocks, OMBA memory array, and a round counter and local task counter. The decoding unit class declares N decoding unit instances and generates N decoding unit hardware working in parallel. Each decoding unit instance will call its member function to perform LDPC decoding. The member function only needs to perform one round of decoding, and the member function needs to be called again for the next round of decoding. At the same time, all decoding unit instances will perform one round of decoding calculations in parallel.

Define input array and output array, which store variables of Stream data type, and are implemented as FIFO queues with buffering function in hardware; specifically, the input array includes N input FIFO queues, and the output array includes N output FIFO queues. The decoder reads data into the input array in batches and synchronously in the input module, and then decodes the data from the input array to each decoding unit. After each decoding unit completes the decoding, it writes the result to the output array, and the data of the output array flows to the output module of the decoder.

The relationship among the input module, the decoding unit and the output module is as follows: a plurality of decoding units share the same input module, and a plurality of decoding units share the same output module.

The data flow is: using the above input FIFO queue and output FIFO queue, a data flow path of the hardware decoder from the input module to the decoding unit to the output module can be established. The data flow path is: the data of the i -th input FIFO queue will only flow to the corresponding i -th decoding unit, and the decoding result data of the i -th decoding unit will only be in the i -th output FIFO queue. The entire decoder has N data flow paths. This data flow can decouple the synchronization of the decoding unit and alleviate the delay overhead of some decoding units waiting in vain due to the difference in the decoding time of the decoding units.

The design process of synchronous decoupling of the decoding unit is as follows:

Each decoding unit instance uses the variables in the round counter to record its current decoding round. When the variable in the round counter is 0, the decoding unit reads data from the corresponding input FIFO queue and initializes it for decoding. When the variable in the round counter is not 0, the decoding unit does not need to read data from the input FIFO queue. At this time, the input FIFO queue buffers multiple decoding codewords. At this time, the internal data flow of the decoding unit occurs in the following two situations when calling member functions:

1) When the decoding result of the current round meets the stop decision condition of LDPC or the variable in the round counter reaches the preset maximum value (the value is 10 in this embodiment), the variable in the round counter is set to 0, the decoding result of the current round is written to the corresponding output FIFO queue, and the value in the local task counter is increased by 1.

2) When the decoding result of the current round does not meet the stop decision condition of LDPC or the variable in the round counter has not reached the maximum number of iterations, there is no data flow at this time, and the decoding unit only performs decoding. Each time its member function ends calling, the variable in the round counter will be increased by 1.

Each decoding unit maintains its own round counter and local task counter, and uses input FIFO queue and output FIFO queue to buffer the asynchronous data flow caused by the difference in decoding time of different decoding units.

When the number of decodings of each decoding unit reaches a preset local decoding number (the value is 300 in this embodiment), the decoding unit is controlled to stop working and no further decoding operation is required.

A global task counter is set in each of the input module and the output module. For the input module, when any input buffer therein outputs a data to be decoded, the global task counter therein is incremented by one; for the output module, when any output buffer therein receives a decoding result, the global task counter therein is incremented by one. When the value of the global task counter in the input module reaches the preset overall decoding number (the value is 3000 in this embodiment, assuming that there are 10 decoding units), the input module is controlled not to work; when the value of the global task counter in the output module reaches the preset overall decoding number, the entire decoder is controlled to end work.

The workflow of the QC-LDPC decoder based on HLS design includes:

Step S1: The input module reads N groups of data in batches and stores them in N input FIFO queues respectively;

Step S2: The member function of the i -th decoding unit determines whether it needs to be initialized based on the value in its round counter. When the value in the round counter is 0, the i -th decoding unit reads data from the i input FIFO queues, initializes, and performs a round of decoding; when the value in the round counter is not 0, the i -th decoding unit does not need to be initialized and performs a round of iterative decoding.

Step S3: The i -th decoding unit determines whether the LDPC stop decision condition is met or the value in its round counter reaches the preset maximum value. If successful, the decoding result is written to the i -th output FIFO queue, the round counter value is set to 0, and the count of the first global task counter in the output module is increased. Otherwise, only the round counter value needs to be increased by 1.

Step S4: The output module reads the data in N output FIFO queues in batches and outputs the decoding results to the outside of the FPGA.

Step S5: When the value of the first global task counter in the output module reaches the preset overall decoding quantity, the output module outputs an end signal to complete the work of the entire decoder.

In a second aspect, the present invention provides a storage device, comprising the QC-LDPC decoder provided in the first aspect of the present invention.

The related technical solution is the same as the QC-LDPC decoder provided in the first aspect of the present invention, and will not be described in detail here.

It will be easily understood by those skilled in the art that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims (7)

1. A QC-LDPC decoder, characterized in that it comprises: a plurality of parallel decoding units; The decoding unit comprises: a decoding calculator, a decoding result memory, a round counter and a terminator; the value of the round counter is initially 0; The decoding calculator is used to obtain the data to be processed in the current round, decode the data to be processed, obtain the decoding result in the current round, and output it to the decoding result memory for storage; wherein, when the value of the round counter is 0, the decoding calculator uses the data to be decoded as the data to be processed in the current round; when the value of the round counter is not 0, the decoding calculator uses the decoding result in the previous round as the data to be processed in the current round; The terminator is used to read the decoding result of the current round from the decoding result memory to make a termination decision. If the decoding result meets the stopping decision condition of LDPC or the value in the round counter reaches a preset maximum value, the decoding result memory is controlled to output the decoding result and the value of the round counter is set to 0; otherwise, the value of the round counter is added by one; the stopping decision condition is that the result of the bitwise XOR of the decoding result is 0. 2. The QC-LDPC decoder according to claim 1, characterized in that the decoding calculator comprises: a data calculation memory, n parallel check node calculation units, and m parallel variable node calculation units; m and n are the number of rows and columns of the LDPC decoding base matrix respectively; The data calculation memory is used to obtain the data to be processed in the current round, and divide the data to be processed into n data blocks, and input them one by one into n check node calculation units to update the check nodes, so as to obtain the data after the check nodes are updated; the data after the check nodes are updated are divided into m data blocks, and input them one by one into m parallel variable node calculation units to update the variable nodes, so as to obtain m decoding data blocks, which constitute the decoding results in the current round, and save them, and output them to the decoding result memory for storage. 3. The QC-LDPC decoder according to claim 2, characterized in that the terminator comprises: a termination module and a decision controller; The termination module includes: a judgment calculation memory; when the current round is the first round, the judgment value of the previous round stored in the judgment calculation memory is 1; The decision controller is used to obtain the decision value of the previous round from the decision calculation memory, and determine whether the decision value is 0. If so, it is determined that the decoding result of the current round meets the stop decision condition of the LDPC; otherwise, it is determined that the decoding result of the current round does not meet the stop decision condition of the LDPC; The termination module is used for reading the decoding result of the current round from the decoding result memory when the decoding result of the current round does not meet the stop decision condition of LDPC, backing up the m decoding data blocks in the decoding result based on the LDPC decoding base matrix respectively, and storing the backed-up decoding data block copies at different positions of the decision calculation memory to form an OMBA memory array; obtaining the kijth data of the decoding data block copy stored in the memory block of the i-th row and j-th _column of the OMBA memory array, recorded as the mark data; performing an XOR operation on all the mark data on each column in the OMBA memory array to obtain the corresponding column XOR result, and performing an OR operation on the column XOR results of all columns to obtain the decision value of the current round, and store it in the decision calculation memory; The i -th decoded data block in the decoding result is denoted as OMB _i , i =1,2,...,m; the number of copies of OMB _i is the same as the number of non-zero elements in the i - th row of the LDPC decoding base matrix; the copy of OMB _i is stored in the i- th row of the OMBA memory array, and the relative position in the row is consistent with the relative position of the non-zero elements in the i -th row of the LDPC decoding base matrix; k _ij is a copy of the decoded data block stored in the memory block in the i-th row and j- th column of the OMBA memory array, from which The position number after the current sub-iteration number starts from the position where the data is located and moves right cyclically; is the value of the i- th row and j -th column of the LDPC decoding base matrix; each round includes M sub-iterations; M is the ratio of the number of bits of the data to be decoded to the length n of the base matrix; each sub-iteration corresponds to the decoding process of one bit of the data to be decoded in the current round; j =1,2,...,n. 4. The QC-LDPC decoder according to any one of claims 1 to 3, further comprising: an input and output module; The input and output modules include: an input module for caching data to be decoded, and an output module for caching decoding results; the input module includes: a plurality of input buffers; the output module includes: a plurality of output buffers; the number of input buffers, output buffers and decoding units is the same, and there is a one-to-one correspondence between them; When the value of the round counter is 0, the decoding calculator reads the data to be decoded from the corresponding input buffer as the data to be processed in the current round; The terminator is used to control the decoding result memory to output the decoding result to the output buffer and set the value of the round counter to 0 when the decoding result in the current round meets the stop decision condition of LDPC or the value in the round counter reaches a preset maximum value. 5. The QC-LDPC decoder according to claim 4 is characterized in that an input FIFO queue is set between the decoding unit and the corresponding input buffer; an output FIFO queue is set between the decoding unit and the corresponding output buffer. 6. The QC-LDPC decoder according to claim 4, characterized in that the input module is provided with a first global task counter, the output module is provided with a second global task counter, and each of the decoding units is provided with a local task counter; The local task counter is used to increase the value of the local task counter by one each time a decoding result is output from the decoding result memory in the decoding unit where the local task counter is located; and when the value of the local task counter reaches a preset local decoding quantity, the decoding unit where the local task counter is located is controlled to stop working; The first global task counter is used to perform an increment operation when any input buffer outputs a decoding result to the corresponding decoding unit; and when the value of the first global task counter reaches a preset overall decoding quantity, the input module is controlled to stop working; The second global task counter is used to perform an increment operation when any output buffer receives a decoding result from the corresponding decoding unit; and when the value of the second global task counter reaches a preset overall decoding quantity, the QC-LDPC decoder is controlled to stop working. 7. A storage device, characterized in that it comprises the QC-LDPC decoder described in any one of claims 1-6.