CN118538614B - Method for manufacturing packaging substrate - Google Patents
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- CN118538614B CN118538614B CN202311681299.7A CN202311681299A CN118538614B CN 118538614 B CN118538614 B CN 118538614B CN 202311681299 A CN202311681299 A CN 202311681299A CN 118538614 B CN118538614 B CN 118538614B
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- insulating layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
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- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Manufacturing Of Printed Wiring (AREA)
Abstract
一种封装基板的制法，包括于核心板体的线路层上形成导电柱，且绝缘层包覆该导电柱，以令该导电柱外露于该绝缘层的表面，接着将该封装基板浸入于低浓度化学液并同时利用研磨机研磨，故本发明的封装基板可达到无凹槽深度的高度均匀性基板。
A method for manufacturing a packaging substrate includes forming a conductive column on a circuit layer of a core board, and an insulating layer covering the conductive column so that the conductive column is exposed on the surface of the insulating layer. The packaging substrate is then immersed in a low-concentration chemical liquid and simultaneously ground using a grinder. Therefore, the packaging substrate of the present invention can achieve a highly uniform substrate without groove depth.
Description
Technical Field
The present invention relates to a method for manufacturing a package substrate for supporting a chip, and more particularly, to a method for manufacturing a package substrate with conductive pillars.
Background
The technology currently applied to the field of Chip packaging includes, for example, chip size packaging (CHIP SCALE PACKAGE, CSP for short), direct Chip attach packaging (DIRECT CHIP ATTACHED, DCA for short), or Multi-Chip Module (MCM for short) and other types of packaging modules. Regardless of the packaging technology used, it is one of the common and necessary steps to remove excess conductive material during a series of steps in the manufacturing process to thin or planarize the conductive material.
Several methods for removing the excess conductive material are widely used, such as mechanical grinding (MECHANICAL GRINDING), chemical liquid etching, chemical Mechanical Polishing (CMP), or contact electrolysis, however, each of the above conventional methods has disadvantages.
Fig. 1A to 1D are cross-sectional views illustrating a conventional method for manufacturing a package substrate 1.
As shown in fig. 1A, a substrate 110 is provided, a dielectric layer 120 is formed on the substrate 110, and a metal layer 130 is formed on the patterned dielectric layer 120, wherein the metal layer 130 covering the surface of the dielectric layer 120 has a surface with uneven thickness (such as the concave-convex surface shown in fig. 1A). Then, a grinding wheel 140 is used to rotate the surface of the metal layer 130 at a high speed to grind and reduce the thickness of the metal layer 130.
As shown in fig. 1B, to facilitate the subsequent planarization process (e.g., chemical etching), the surface of the metal layer 130 is mechanically ground multiple times by the grinding wheel 140, so that the surface thickness is further thinned to present the metal layer surface 130d shown in fig. 1B.
As shown in fig. 1C, the package substrate 1 of fig. 1B after mechanical grinding is then immersed in a tank containing a chemical etching solution 150 to etch the metal layer surface 130d by chemical solution etching.
Finally, as shown in fig. 1D, after chemical etching, the metal layer surface 130D shown in fig. 1C is planarized to form a metal layer surface 130e, and the metal layer surface 130e is flush with the surface of the patterned dielectric layer 120.
As can be seen from the above, the conventional polishing method is to polish the surface of the metal layer to be flat, and then immerse the polished substrate in the etching solution. However, there are several disadvantages and risks in this method, such as that the excessive conductive material (e.g. copper shave) generated during polishing process contaminates the surface of the board, uneven stress is generated and concentrated to deform the substrate, and a grinder and a jig with corresponding substrate size need to be customized, and then the substrate immersed in the etching solution cannot guarantee the uniformity of etching the conductive metal (e.g. recess depth and side etching).
Therefore, how to overcome the above problems of the conventional methods has been an urgent problem.
Disclosure of Invention
The present invention is directed to a method for manufacturing a package substrate, which solves at least one of the above problems.
In view of the above-mentioned drawbacks of the prior art, the present invention provides a method for manufacturing a package substrate, which includes providing a substrate, forming a plurality of conductive pillars on the substrate, coating the plurality of conductive pillars with an insulating layer, exposing the plurality of conductive pillars on the surface of the insulating layer, immersing the exposed surfaces of the plurality of conductive pillars and the insulating layer in a chemical solution, and polishing the exposed surfaces of the plurality of conductive pillars and the insulating layer by using a polishing machine.
In one embodiment, the substrate has a first side and a second side opposite to each other and a plurality of core plates with conductive vias connecting the first side and the second side, and circuit layers electrically connected to the plurality of conductive vias are formed on the first side and the second side of the core plates, respectively.
In one embodiment, the plurality of conductive pillars are formed on the circuit layer on the first side and the second side of the core board body, and the plurality of conductive pillars are electrically connected to the circuit layer.
In one embodiment, the insulating layer is formed on the first side and the second side of the core plate body to cover the plurality of conductive pillars and expose the plurality of conductive pillars on the surface of the insulating layer.
In one embodiment, the plurality of conductive pillars are copper pillars.
In one embodiment, after the polishing by the polishing machine, the surfaces of the plurality of conductive pillars are flush with the surface of the insulating layer.
In one embodiment, the grinder grinds the plurality of conductive posts horizontally to the surface of the plurality of conductive posts.
In one embodiment, the chemical liquid includes an etching liquid and a polishing liquid.
In one embodiment, the step of forming the plurality of conductive pillars and the insulating layer includes forming the plurality of conductive pillars on the substrate, forming an insulating layer covering the plurality of conductive pillars on the surface of the substrate, and removing a portion of the insulating layer to expose the plurality of conductive pillars on the surface of the insulating layer.
For example, a resist layer is formed on two opposite surfaces of the substrate, and a plurality of patterned openings (e.g. after exposure and development) are formed on each resist layer, so that the circuit layer on the substrate is exposed outside each patterned opening. The resist layer may be a dry film (dry film) to form the plurality of patterned openings through an exposure and development process. Then, a metal layer such as copper is formed on the resist layer. The metal layer is formed, for example, via a plating process. Before, a seed layer made of copper can be formed on the surfaces of the resist layer and the patterned opening in a sputtering manner, or a graphene film is stuck in a pressing manner to serve as the seed layer, and then a metal layer is formed by electroplating.
In another embodiment, the step of forming the plurality of conductive pillars and the insulating layer includes forming an insulating layer having a plurality of openings on the substrate, forming a metal layer on the insulating layer and in the plurality of openings, and removing the metal layer on the insulating layer, leaving the material of the metal layer in the plurality of openings to obtain the plurality of conductive pillars exposed on the surface of the insulating layer.
In the embodiment of the substrate taking the core plate as an example, the insulating layer and the plurality of conductive pillars are formed on the opposite first side and the second side of the core plate, and the circuit build-up can be performed on both sides of the substrate by the method of the present invention.
As can be seen from the above, the package substrate and the method for manufacturing the same according to the present invention are mainly characterized in that the insulating layer is removed by plasma etching, the substrate is immersed in a low-concentration chemical solution and polished in a manner of being horizontal to the surfaces of the plurality of conductive pillars by a polishing machine, so that the substrate is planarized to form a coplanar surface.
Furthermore, the substrate is immersed in the low-concentration chemical liquid, namely the chemical liquid is used as etching liquid to perform dual functions of the etching liquid and the polishing liquid during polishing of the polishing machine, so that the effects of cooling, cleaning and reducing polishing resistance are achieved during polishing.
Drawings
Fig. 1A to 1D are cross-sectional views illustrating a conventional method for manufacturing a package substrate.
Fig. 2A to 2F are schematic cross-sectional views of a first embodiment of a method for manufacturing a package substrate according to the present invention.
Fig. 3A to 3E are schematic cross-sectional views illustrating a second embodiment of a method for manufacturing a package substrate according to the present invention.
The reference numerals are as follows:
1,2,3 package substrate
20. Core plate body
20A first side
20B second side
21,25,31,35 Conductive column
21A,21b surfaces of conductive pillars
23. Chemical liquid
24. Grinding machine
29. Barrier layer
200. Conductive via
201,202 Line layer
200A plug hole material
110. Substrate board
211. Insulating layer
120. Dielectric layer
130. Metal layer
130D surface of metal layer
130E metal layer surface
140. Grinding wheel
150. Chemical etching solution
210. Metal layer
211A,211b surface of the insulating layer
290. Patterning openings
310. Perforating the hole
Detailed Description
Other advantages and effects of the present invention will become readily apparent to those skilled in the art from the present disclosure, as illustrated by the following specific examples.
It should be understood that the structures, proportions, sizes, etc. shown in the drawings and described herein are for illustration purposes only and not for the purpose of limiting the invention to the precise nature of the disclosure, therefore, without any technical significance, any structural modification, proportional relation change or size adjustment should still fall within the scope of the technical disclosure without affecting the efficacy and achievement of the present invention. Also, the terms "upper", "a" and the like recited in the present specification are used for descriptive purposes only and are not intended to limit the scope of the invention, which is otherwise defined without any substantial modification to the technical context.
Fig. 2A to 2E are schematic cross-sectional views of a first embodiment of a method for manufacturing a package substrate 2 according to the present invention.
As shown in fig. 2A, a substrate, such as a core board 20, is provided, which has a first side 20a and a second side 20b opposite to each other, and a plurality of conductive vias 200 connecting the first side 20a and the second side 20b, and circuit layers 201 and 202 are patterned on the first side 20a and the second side 20b of the core board 20, respectively, such that the plurality of conductive vias 200 are electrically connected to the plurality of circuit layers 201 and 202.
In this embodiment, the core plate 20 may be an organic polymeric plate or other plates including bismaleimide/tri-nitrogen trap (Bismaleimide triazine, BT), prepreg with glass fiber (Prepreg, PP), and the plurality of conductive vias 200 may be hollow columns, which may fill the hole-plugging material 200a in the hollow space, wherein the hole-plugging material 200a is various, such as conductive adhesive, ink, and the like, and is not limited. It should be appreciated that in other embodiments, the plurality of conductive vias 200 may be solid metal pillars without filling the plug material 200a.
As shown in fig. 2B, a resist layer 29 is formed on the first side 20a and the second side 20B of the core board 20, and a plurality of patterned openings 290 (e.g. after exposure and development) are formed on each resist layer 29, such that the plurality of circuit layers 201,202 are exposed out of each patterned opening 290.
In this embodiment, the resist layer 29 is a dry film (dry film) to form the plurality of patterned openings 290 through an exposure and development process.
As shown in fig. 2C, a metal layer 210 such as copper is formed on the resist layer 29. The metal layer 210 is formed, for example, via a plating process. In one embodiment, a seed layer made of copper may be formed on the surface of the resist layer and the patterned opening by sputtering, or a graphene film may be stuck to the surface of the resist layer by pressing to form the seed layer, followed by electroplating to form a metal layer (not shown).
As shown in fig. 2D, the material of the metal layer 210 on the resist layer 29 is removed, and only the material of the metal layer 210 in the patterned openings 290 is remained for being used as a plurality of conductive pillars 21, such as copper pillars, so that the plurality of conductive pillars 21 are electrically connected to the plurality of circuit layers 201,202. Next, the resist layer 29 is removed to expose the first side 20a and the second side 20b of the core plate 20.
As shown in fig. 2E, insulating layers 211 are formed on the first side 20a and the second side 20b of the core board 20, respectively. In this embodiment, each insulating layer 211 is a dielectric layer, such as an ABF film (Ajinomoto build-up film) or other dielectric materials. After the insulating layer 211 is formed, the circuit layers 201,202 and the plurality of conductive pillars 21 are embedded in the insulating layer 211, wherein a portion of the surfaces 21a, e.g., the top surfaces, of the plurality of conductive pillars 21 are flush with the surfaces 211a,211b of the insulating layer 211, or a portion of the plurality of conductive pillars 21 protrude from the surfaces 211a,211b of the insulating layer 211, so that the plurality of conductive pillars 21 are exposed on the surface of each insulating layer 211.
Further, portions of the insulating layer 211 are removed by Plasma (Plasma), polishing, or other means such that the surface 211a,211b of each insulating layer 211 is flush with the surface 21a,21b of the plurality of conductive pillars 21, such that the plurality of conductive pillars 21 are exposed at the surface 211a,211b of each insulating layer 211.
Next, the conductive pillars 21 exposed on the surfaces 211a,211b of the insulating layer 211 and the surfaces 211a,211b of the insulating layer 211 are immersed in the chemical liquid 23, and the conductive pillars 21 immersed in the chemical liquid 23 are planarized by the grinder 24.
In this embodiment, the chemical solution 23 is a low-concentration etching solution, which etches the conductive material (e.g., the conductive pillars 21) immersed therein.
In some embodiments, the chemical solution 23 is a low concentration chemical solution including an etching solution and a polishing solution, which facilitates etching and polishing of the conductive material immersed therein, such as the conductive pillars 21.
In this embodiment, the polishing machine 24 polishes the conductive pillars 21 (e.g., the surfaces 21a,21b of the conductive pillars 21) immersed in the chemical solution 23 and/or the surfaces 211a,211b of the insulating layer 211 in a direction horizontal to the surfaces 21a,21b and/or the surfaces 211a,211 b.
As shown in fig. 2F, according to the process of fig. 2A to 2D, another plurality of conductive pillars 25 are formed on the insulating layer 211 and the conductive pillars 21 planarized by the chemical solution 23 and the polishing machine 24 in fig. 2E, and then the plurality of conductive pillars 25 coated in the insulating layer are planarized by the chemical solution and the polishing machine according to the process of fig. 2E. It should be appreciated that the process of fig. 2A-2E may be repeated with additional conductive pillar build-up on the insulating layer 211 and the plurality of conductive pillars 21.
Therefore, in the method of the first embodiment, after removing a portion of the insulating layer 211 by plasma etching, the plurality of conductive pillars 21 are immersed in the chemical solution 23, and the plurality of conductive pillars 21 are planarized by the grinder 24 in a manner substantially horizontal to the plurality of conductive pillars 21.
Fig. 3A to 3E are schematic cross-sectional views of a second embodiment of a method for manufacturing a package substrate 3 according to the present invention. The difference between the present embodiment and the first embodiment is that the process steps are substantially the same as those of the structure obtained after the process, so the following description will not be repeated.
As shown in fig. 3A, following the process of fig. 2A, an insulating layer 211 is formed on the first side 20a and the second side 20b of the core board 20, and a plurality of openings 310 are formed on each insulating layer 211, so that the plurality of circuit layers 201,202 are exposed out of each opening 310.
In this embodiment, a Plasma (Plasma) etching or other method is used to remove a portion of the insulating layer 211 to form the openings 310.
As shown in fig. 3B, a metal layer 210 is formed on the insulating layer 211 and in the opening 310 by electroplating or other methods.
As shown in fig. 3C, the material of the metal layer 210 on the insulating layer 211 is removed, and only the material of the metal layer 210 in the openings 310 is remained for being used as a plurality of conductive pillars 31, so that the plurality of conductive pillars 31 are electrically connected to the plurality of circuit layers 201 and 202, wherein the surfaces of the plurality of conductive pillars 31 are substantially flush with the surface of each insulating layer 211, so that the plurality of conductive pillars 31 are exposed out of each opening 310. However, it should be understood that in the embodiment shown in fig. 3C, the surface of the plurality of conductive pillars 31 may be higher than the surface of each of the insulating layers 211.
Therefore, the second embodiment is manufactured by forming the openings 310 on the insulating layer 211 to manufacture the plurality of conductive pillars 31, so that the resist layer 29 is not required to be formed.
As shown in fig. 3D, the conductive pillars 21 exposed on the surfaces 211a,211b of the insulating layer 211 and the surfaces 211a,211b of the insulating layer 211 are immersed in the chemical liquid 23, and the conductive pillars 21 immersed in the chemical liquid 23 are planarized by the grinder 24. The chemical solution 23 is a low-concentration etching solution, which etches the conductive material (e.g., the conductive pillars 21) immersed therein.
In some embodiments, the chemical solution 23 is a low concentration chemical solution including an etching solution and a polishing solution, which facilitates etching and polishing of the conductive material immersed therein, such as the conductive pillars 21.
In this embodiment, the polishing machine 24 polishes the conductive pillars 21 (e.g., the surfaces 21a,21b of the conductive pillars 21) immersed in the chemical solution 23 and/or the surfaces 211a,211b of the insulating layer 211 in a direction horizontal to the surfaces 21a,21b and/or the surfaces 211a,211 b.
As shown in fig. 3E, another plurality of conductive pillars 35 are formed on the insulating layer 211 and the conductive pillars 21 planarized by the chemical liquid 23 and the polishing machine 24 in fig. 3D, and then the plurality of conductive pillars 35 wrapped in the insulating layer are planarized by the chemical liquid and the polishing machine according to the process in fig. 3D. It should be appreciated that the process of fig. 2A-2E or fig. 3A-3C may be repeated for additional conductive pillar build-up.
In summary, in the method for manufacturing the package substrate 2,3 of the present invention, after removing the part of the insulating layer 211 by plasma etching, the plurality of conductive pillars 21 are immersed in the chemical solution 23 and the plurality of conductive pillars 21 are planarized by the grinder 24 in a manner substantially horizontal to the plurality of conductive pillars 21, so the package substrate 2,3 and the method for manufacturing the same of the present invention have the following advantages and characteristics compared with the prior art:
The method for manufacturing the packaging substrates 2 and 3 of the invention can reach the double-sided substrate with high uniformity without groove depth (RECESS DEPTH and RD) by grinding and etching and immersing the substrates in low-concentration chemical liquid.
In the manufacturing method of the invention, the grinding machine grinds in a mode of being horizontal to the grinding surface, and compared with a horizontal line and vertical grinding mode, the grinding machine has the advantages of large contact area, uniform vertical pressure, suitability for thin substrates, no limitation of thickness processing of equipment substrates and the like.
In the manufacturing method of the invention, the copper column is used for replacing laser via holes and removing glue residues, so that the cost of the process and the instrument after molding is saved.
In the method of the present invention, a fine L/S pattern can be realized on the outer layer by a copper pillar method using a high resolution dry film.
By the method of the present invention, the thickness over the entire substrate is less than typical substrates by thinner dielectric layer materials (e.g., 10 or 20 μm thickness).
Compared with the traditional process, the method of the invention can be realized by only using a manual or typical grinder without a special grinder or grinder.
In the method of the present invention, the substrate is immersed in a low concentration chemical liquid which helps polishing to planarize like a lubricant and a thinner substrate can be achieved by polishing and polishing to remove the protrusions (copper pillar shape).
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications to the above would be obvious to those of ordinary skill in the art, without departing from the spirit and scope of the present invention. The scope of the invention is therefore intended to be indicated by the appended claims.
Claims (9)
1. A method of fabricating a package substrate, comprising:
providing a substrate;
forming a plurality of conductive posts on the substrate, coating the conductive posts with an insulating layer to expose the conductive posts on the surface of the insulating layer, and
Immersing the exposed conductive posts and the surface of the insulating layer in a chemical liquid and grinding the exposed conductive posts and the surface of the insulating layer by using a grinder,
Wherein the chemical liquid comprises etching liquid and grinding liquid.
2. The method of claim 1, wherein the substrate has opposite first and second sides and a plurality of core plates with conductive vias connecting the first and second sides, and the first and second sides of the core plates are respectively formed with circuit layers electrically connected to the plurality of conductive vias.
3. The method of claim 2, wherein the plurality of conductive pillars are formed on the circuit layer on the first side and the second side of the core board body, and the plurality of conductive pillars are electrically connected to the circuit layer.
4. The method of claim 3, wherein the insulating layer is formed on the first side and the second side of the core board body to encapsulate the plurality of conductive pillars, and expose the plurality of conductive pillars on the surface of the insulating layer.
5. The method of claim 1, wherein the plurality of conductive pillars are copper pillars.
6. The method of claim 1, wherein the surface of the plurality of conductive pillars is flush with the surface of the insulating layer after the polishing by the polishing machine.
7. The method of claim 1, wherein the grinder grinds the plurality of conductive posts horizontally to the surface of the plurality of conductive posts.
8. The method of claim 1, wherein the step of forming the plurality of conductive pillars and the insulating layer comprises forming the plurality of conductive pillars on the substrate, forming an insulating layer covering the plurality of conductive pillars on a surface of the substrate, and removing a portion of the insulating layer to expose the plurality of conductive pillars on the surface of the insulating layer.
9. The method of claim 1, wherein the step of forming the plurality of conductive pillars and the insulating layer comprises forming an insulating layer with a plurality of openings on the substrate, forming a metal layer on the insulating layer and in the plurality of openings, and removing the metal layer on the insulating layer, and preserving the material of the metal layer in the plurality of openings to obtain the plurality of conductive pillars exposed on the surface of the insulating layer.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311681299.7A CN118538614B (en) | 2023-12-08 | 2023-12-08 | Method for manufacturing packaging substrate |
| TW112151401A TWI871155B (en) | 2023-12-08 | 2023-12-28 | A fabricating method of package substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311681299.7A CN118538614B (en) | 2023-12-08 | 2023-12-08 | Method for manufacturing packaging substrate |
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| Publication Number | Publication Date |
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| CN118538614A CN118538614A (en) | 2024-08-23 |
| CN118538614B true CN118538614B (en) | 2025-03-28 |
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| CN202311681299.7A Active CN118538614B (en) | 2023-12-08 | 2023-12-08 | Method for manufacturing packaging substrate |
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| CN (1) | CN118538614B (en) |
| TW (1) | TWI871155B (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102573337A (en) * | 2010-12-30 | 2012-07-11 | 北大方正集团有限公司 | Manufacturing method of multilayer circuit board, laminating device and multilayer circuit board |
| CN106024749A (en) * | 2015-03-31 | 2016-10-12 | 意法半导体有限公司 | Semiconductor packages with pillar and bump structures |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI470757B (en) * | 2009-10-22 | 2015-01-21 | Unimicron Technology Corp | Package substrate and fabrication method thereof |
| US9449947B2 (en) * | 2014-07-01 | 2016-09-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor package for thermal dissipation |
| US10468339B2 (en) * | 2018-01-19 | 2019-11-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Heterogeneous fan-out structure and method of manufacture |
| US10804254B2 (en) * | 2018-06-29 | 2020-10-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fan-out package with cavity substrate |
| US10971461B2 (en) * | 2018-08-16 | 2021-04-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method of manufacture |
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2023
- 2023-12-08 CN CN202311681299.7A patent/CN118538614B/en active Active
- 2023-12-28 TW TW112151401A patent/TWI871155B/en active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102573337A (en) * | 2010-12-30 | 2012-07-11 | 北大方正集团有限公司 | Manufacturing method of multilayer circuit board, laminating device and multilayer circuit board |
| CN106024749A (en) * | 2015-03-31 | 2016-10-12 | 意法半导体有限公司 | Semiconductor packages with pillar and bump structures |
Also Published As
| Publication number | Publication date |
|---|---|
| CN118538614A (en) | 2024-08-23 |
| TWI871155B (en) | 2025-01-21 |
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