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CN118522699A - DBC substrate with high power density and high heat dissipation and power module - Google Patents

DBC substrate with high power density and high heat dissipation and power module Download PDF

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Publication number
CN118522699A
CN118522699A CN202410587550.1A CN202410587550A CN118522699A CN 118522699 A CN118522699 A CN 118522699A CN 202410587550 A CN202410587550 A CN 202410587550A CN 118522699 A CN118522699 A CN 118522699A
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electrode region
layer
electrode
insulating layer
dbc substrate
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王素
戴鑫宇
张鹏
农一清
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Jiangsu Solidep Semiconductor Technology Co ltd
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Jiangsu Solidep Semiconductor Technology Co ltd
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Priority to CN202410587550.1A priority Critical patent/CN118522699A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/15—Ceramic or glass substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/46—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/46—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids
    • H01L23/473—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids by flowing liquids
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Geometry (AREA)
  • Ceramic Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

The invention discloses a DBC substrate with high power density and high heat dissipation and a power module, and relates to the field of semiconductor packaging, comprising an insulator, wherein the insulator comprises an upper insulating layer and a lower insulating layer corresponding to the upper insulating layer; an upper connecting layer is prepared on the upper insulating layer, a lower connecting layer is prepared on the lower insulating layer, and the upper connecting layer and/or the lower connecting layer are/is used for packaging the chip. The power module packaged by the DBC substrate can improve the power density and heat dissipation capacity of the power module.

Description

DBC substrate with high power density and high heat dissipation and power module
Technical Field
The invention relates to the field of semiconductor packaging, in particular to a DBC substrate with high power density and high heat dissipation performance and a power module.
Background
Along with the rapid development of social economy and the continuous progress of technical process, new energy automobiles, charging piles, intelligent equipment manufacturing, internet of things, new energy power generation, rail transit and other emerging application fields gradually become important application markets of power semiconductors, the power semiconductor requirements are driven to rapidly increase, and simultaneously, higher requirements of low loss, high power density, high heat dissipation, high reliability and the like are also provided for power modules.
The conventional power module generally includes a copper-clad ceramic board (DBC, direct Bonding Copper) and a power chip encapsulated on the copper-clad ceramic board, and the conventional copper-clad ceramic board includes a front surface and a back surface corresponding to the front surface, and generally, the front surface of the conventional copper-clad ceramic board is used for encapsulating the chip, and the back surface is used for fixing the copper-clad ceramic board to an external structure, which makes the conventional copper-clad ceramic board have a low power density and a single heat dissipation path, and severely limits the power density and heat dissipation capability of the power module. Meanwhile, parasitic parameters such as parasitic resistance, parasitic inductance and the like of the power module are larger, so that the loss of the power module is increased, and the normal operation of the power chip is influenced. In summary, the existing copper-clad ceramic plate structure cannot meet the requirements of high power density, high heat dissipation and high reliability of the power module.
Disclosure of Invention
The inventor provides a DBC substrate with high power density and high heat dissipation and a power module aiming at the problems and the technical requirements, and the technical scheme of the invention is as follows:
The DBC substrate with high power density and high heat dissipation comprises an insulator, wherein the insulator comprises an upper insulating layer and a lower insulating layer corresponding to the upper insulating layer;
An upper connecting layer is prepared on the upper insulating layer, a lower connecting layer is prepared on the lower insulating layer, and the upper connecting layer and/or the lower connecting layer are/is used for packaging the chip.
The DBC substrate further comprises a connecting structure, wherein the connecting structure surrounds the upper insulating layer and the lower insulating layer and is fixedly connected with the upper insulating layer and the lower insulating layer;
after the connecting structure is fixedly connected with the upper insulating layer and the lower insulating layer, a cavity is formed between the upper insulating layer and the lower insulating layer, and cooling medium is filled in the cavity.
The further technical proposal is that the upper connecting layer comprises an upper layer first electrode zone, the lower connecting layer comprises a lower layer third electrode zone, wherein,
The upper layer first electrode region penetrates through the upper insulating layer and the lower insulating layer and is connected with the lower layer third electrode region into a whole.
The upper connecting layer further comprises an upper layer second electrode region and an upper layer third electrode region, wherein the upper layer first electrode region, the upper layer second electrode region and the upper layer third electrode region are isolated in an insulating way through an upper insulating layer, and the upper layer first electrode region and the upper layer second electrode region are positioned at the same end of the upper connecting layer;
the lower connecting layer further comprises a lower first electrode zone and a lower second electrode zone, wherein the lower first electrode zone, the lower second electrode zone and the lower third electrode zone are isolated in an insulating way through a lower insulating layer, and the lower first electrode zone and the lower second electrode zone are located at the same end of the lower connecting layer.
The further technical scheme is that the upper first electrode area and the upper second electrode area are overlapped with the lower third electrode area;
the upper third electrode region overlaps the lower first electrode region and the lower second electrode region, and the upper third electrode region overlaps the lower third electrode region partially.
The area of the upper third electrode area is larger than that of the upper first electrode area, and the area of the upper first electrode area is larger than that of the upper second electrode area;
And/or the area of the lower third electrode region is larger than the area of the lower first electrode region, and the area of the lower first electrode region is larger than the area of the lower second electrode region.
The upper insulating layer is provided with a first through hole and a second through hole which are communicated with the cavity;
When the cooling medium is cooling liquid, the cooling medium is injected into the cavity through the first through hole and/or the second through hole, and the cooling medium is static in the cavity or flows from the first through hole to the second through hole in the cavity.
The power module is characterized by comprising the DBC substrate, and an upper chip set and a lower chip set which are arranged on the DBC substrate, wherein the upper chip set and the lower chip set are electrically connected.
The further technical proposal is that the upper chip group and the lower chip group both comprise a plurality of chips, wherein,
The welding surface of the chip in the upper chip set is welded on an upper third electrode area of a connecting layer on the DBC substrate through welding flux;
And the welding surface of the chip in the lower chip set is welded on the lower third electrode area of the lower connecting layer of the DBC substrate through welding flux.
The further technical proposal is that the device also comprises an upper layer signal terminal group and a lower layer signal terminal group, wherein,
The upper layer signal terminal group comprises an upper layer first signal terminal welded on the upper layer first electrode region, an upper layer second signal terminal welded on the upper layer second electrode region, a module power supply positive electrode power terminal welded on the upper layer third electrode region and a module power output terminal welded on the upper layer third electrode region;
The lower layer signal terminal group comprises a lower layer first signal terminal welded on the lower layer first electrode region, a lower layer second signal terminal welded on the lower layer second electrode region and a module power supply negative electrode power terminal welded on the lower layer first electrode region.
The beneficial technical effects of the invention are as follows:
The DBC substrate provided by the invention comprises the upper connecting layer prepared on the upper insulating layer and the lower connecting layer prepared on the lower insulating layer, and when the DBC substrate is used for packaging a power module, the upper connecting layer and the lower connecting layer can both package the power chip, so that the power density of the power module is improved. Meanwhile, the radiators can be arranged on the four side faces of the power module, so that the radiating capacity of the power module is improved. In addition, the DBC substrate provided by the invention is also provided with the cavity filled with the cooling medium between the upper insulating layer and the lower insulating layer, so that the heat dissipation path of the DBC substrate is further increased, and the power module is ensured to work normally under high power density.
In addition, the DBC substrate provided by the invention connects the upper layer first electrode area in the upper connecting layer and the lower layer third electrode area in the lower connecting layer into a whole, so that a bonding wire connecting the upper layer first electrode area and the lower layer third electrode area is omitted, the parasitic resistance and parasitic inductance of a power module formed by packaging the DBC substrate are reduced, the power module has lower loss, the packaging cost is reduced, and the packaging yield and reliability are improved.
Drawings
Fig. 1 is a schematic front view of an embodiment of a DBC substrate provided by the present invention.
Fig. 2 is a schematic back view of an embodiment of a DBC substrate provided by the present invention.
FIG. 3 is a cross-sectional view of a DBC substrate at A-A' in one embodiment provided by the invention.
FIG. 4 is a cross-sectional view of a DBC substrate at B-B' in one embodiment provided by the invention.
FIG. 5 is a cross-sectional view of a DBC substrate at C-C' in one embodiment provided by the invention.
Fig. 6 is a schematic front view of an embodiment of a power module according to the present invention.
Fig. 7 is a schematic rear view of an embodiment of a power module according to the present invention.
Reference numerals: 1-upper IGBT chip, 2-upper FRD chip, 3-first connecting strip, 4-second connecting strip, 5-first connecting wire, 6-lower first signal terminal, 7-module power supply positive electrode power terminal, 8-lower second signal terminal, 9-upper first signal terminal, 10-connecting structure, 11-module power output terminal, 12-upper second signal terminal, 13-outer copper frame, 14-module power supply negative electrode power terminal, 15-lower IGBT chip, 16-lower FRD chip, 17-third connecting strip, 18-fourth connecting strip, 19-second connecting wire, 101-upper insulating layer, 102-lower insulating layer, 111-upper first electrode region, 112-upper second electrode region, 113-upper third electrode region, 121-lower first electrode region, 122-lower second electrode region, 123-lower third electrode region, 131-first through hole, 132-second through hole.
Detailed Description
The following describes the embodiments of the present invention further with reference to the drawings.
In order to improve the power density and heat dissipation capacity of the DBC substrate, the invention provides a DBC substrate with high power density and high heat dissipation performance, which comprises an insulator, wherein the insulator comprises an upper insulating layer 101 and a lower insulating layer 102 corresponding to the upper insulating layer 101;
an upper connection layer is prepared on the upper insulating layer 101, a lower connection layer is prepared on the lower insulating layer 102, and the upper connection layer and/or the lower connection layer are used for packaging the chip.
As shown in fig. 1 and 2, the DBC substrate provided by the present invention includes a front surface and a back surface corresponding to the front surface, and optionally, the upper insulating layer 101 and the upper connection layer prepared on the upper insulating layer 101 correspond to the front surface of the DBC substrate, and at this time, the lower insulating layer 102 and the lower connection layer prepared on the lower insulating layer 102 correspond to the back surface of the DBC substrate. The upper insulating layer 101 corresponds to the lower insulating layer 102, and preferably, the upper insulating layer 101 and the lower insulating layer 102 are completely overlapped, that is, when the upper insulating layer 101 projects toward the lower insulating layer 102, the projection of the upper insulating layer 101 and the projection of the lower insulating layer 102 are completely overlapped. Typically, the area of the upper connection layer is not greater than the area of the upper insulation layer 101, and the area of the lower connection layer is not greater than the area of the lower insulation layer 102. Specifically, the upper connection layer may be formed on the upper insulation layer 101 and the lower connection layer may be formed on the lower insulation layer 102 by a conventional process in the DBC process, which will not be described herein.
Optionally, the materials of the upper insulating layer 101 and the lower insulating layer 102 may be Al 2O3, alN, si 3N4, or the like. The upper connecting layer and the lower connecting layer are made of Cu. In practical implementation, the materials of the upper insulating layer 101, the lower insulating layer 102, the upper connection layer and the lower connection layer may be selected according to practical requirements.
Preferably, the front and back sides of the DBC substrate with high power density and high heat dissipation are used for packaging the power chip at the same time, that is, the upper connection layer and the lower connection layer are used for packaging the power chip at the same time, and the specific manner of packaging the chip on the upper connection layer and the lower connection layer can be referred to as the following description. Compared with the traditional DBC capable of only packaging chips on one side, the DBC substrate provided by the invention can package more chips on the same area, so that the power density of a power module formed after packaging is improved.
Further, the DBC substrate further includes a connection structure 10, where the connection structure 10 surrounds the upper insulating layer 101 and the lower insulating layer 102 and is fixedly connected with the upper insulating layer 101 and the lower insulating layer 102;
After the connection structure is fixedly connected with the upper insulating layer and the lower insulating layer, a cavity 100 is formed between the upper insulating layer 101 and the lower insulating layer 102, and a cooling medium is filled in the cavity 100.
As can be seen from the background, in the conventional DBC, the DBC is fixed on the external structure through the connection layer on the back side of the DBC, and since the front side and the back side of the DBC substrate provided in the present invention are used for packaging the chip, the DBC cannot be fixed on the external structure by using the back side of the DBC, the connection structure 10 is disposed around the DBC substrate, that is, around the upper insulating layer 101 and the lower insulating layer 102, and the DBC substrate is fixed on the external structure by using the connection structure 10. In particular, cu may be used as the material of the connection structure 10. Different from the traditional power module, only the radiator can be installed on one side, and when the power module is formed based on the DBC substrate provided by the invention, the radiator can be installed on four sides of the power module, and sufficient heat dissipation of the power module can be realized through a plurality of radiators, so that the heat dissipation capacity of the power module is improved. The manner in which the power module is formed based on the DBC substrate provided by the present invention, and the specific form in which the heat sinks are mounted on the four sides of the power module, may be referred to as the following description.
In order to further enhance the heat dissipation capability of the DBC substrate, a cooling medium, which may be a cooling liquid, is disposed in the DBC substrate, that is, a cavity 100 is formed between the upper insulating layer 101 and the lower insulating layer 102, and the cavity 100 is filled with the cooling medium. By incorporating a cooling medium in the DBC substrate, the heat dissipation path of the DBC substrate can be increased, thereby improving the heat dissipation performance of the DBC substrate. When the DBC substrate is used for forming the power module, the normal operation of the power module under high frequency and high power density can be ensured.
In order to increase the contact area between the cooling medium and the upper insulating layer 101 and the lower insulating layer 102, in an embodiment of the present invention, the upper insulating layer 101 is separated from the lower insulating layer 102 and forms a gap with a predetermined thickness, and the cavity 100 is formed around the gap by using the connection structure 10, as shown in fig. 4, at this time, the cooling medium in the cavity 100 may cover the side of the upper insulating layer 101 away from the upper connection layer and the side of the lower insulating layer 102 away from the lower connection layer, so that the cooling medium has a larger contact area with the upper insulating layer 101 and the lower insulating layer 102, thereby improving the heat exchange efficiency and further improving the heat dissipation performance of the DBC substrate.
Further, the upper insulating layer 101 is provided with a first through hole 131 and a second through hole 132 which are communicated with the cavity 100;
When the cooling medium is a cooling liquid, the cooling medium is injected into the cavity 100 through the first through hole 131 and/or the second through hole 132, and the cooling medium is kept standing in the cavity 100 or flows from the first through hole 131 to the second through hole 132 in the cavity 100.
As shown in fig. 1, in the present embodiment, the first through hole 131 and the second through hole 132 are respectively disposed on the upper insulating layer 101 at two sides of the upper connection layer, and the centers of the first through hole 131 and the second through hole 132 are both located on the central axis of the DBC substrate in the length direction. Fig. 3 shows a cross-sectional view of the DBC substrate along a central axis in a length direction, i.e., a cross-sectional view of the DBC substrate at A-A', and as shown in fig. 3, the first and second through holes 131 and 132 extend perpendicularly from the surface of the upper insulating layer 101 toward the cavity 100 and communicate with the cavity 100.
Preferably, when the cooling medium is a cooling liquid, the first through hole 131 is used as a liquid inlet hole, the second through hole 132 is used as a liquid outlet hole, so that the cooling medium flows from the first through hole 131 to the second through hole 132 in the cavity 100, and the flowing cooling liquid can more efficiently take away the heat emitted by the power chip packaged on the DBC substrate, so that the packaged power module has more excellent heat dissipation and cooling performance, and is suitable for application of the power module with higher power requirement.
Further, the upper connection layer includes an upper first electrode region 111, and the lower connection layer includes a lower third electrode region 123, wherein,
The upper first electrode region 111 penetrates the upper insulating layer 101 and the lower insulating layer 102, and is integrally connected to the lower third electrode region 123.
Specifically, as shown in fig. 1, the upper connection layer is divided into an upper first electrode region 111, an upper second electrode region 112, and an upper third electrode region 113, which upper first electrode region 111, upper second electrode region 112, and upper third electrode region 113 are insulated and isolated by an upper insulating layer 101. As shown in fig. 2, the lower connection layer is divided into a lower first electrode region 121, a lower second electrode region 122, and a lower third electrode region 123, which are insulated and isolated by a lower insulating layer 102.
As shown in fig. 3 and 5, when the cavity 100 is disposed between the upper insulating layer 101 and the lower insulating layer 102, the upper first electrode region 111 penetrates through the upper insulating layer 101, the cavity 100 and the lower insulating layer 102, and is integrally connected to the lower third electrode region 123. When the upper first electrode region 111 and the lower third electrode region 123 are connected into a whole and the power module is formed by using the DBC substrate, not only can the bonding wire connecting the upper first electrode region 111 and the lower third electrode region 123 be omitted, but also the parasitic resistance and parasitic inductance of the power module can be reduced, so that the power module has lower loss and simultaneously reduces the packaging cost. Meanwhile, the problems of breakage and failure of bonding wires connecting the upper layer first electrode region 111 and the lower layer third electrode region 123 are avoided, and the packaging yield of the power module and the reliability of the module are improved.
Further, the upper first electrode region 111 and the upper second electrode region 112 overlap with the lower third electrode region 123;
The upper third electrode region 113 overlaps the lower first electrode region 121 and the lower second electrode region 122, and the upper third electrode region 113 overlaps the lower third electrode region 123 partially.
As shown in fig. 1, the DBC substrate is rectangular as a whole, the upper first electrode region 111, the upper second electrode region 112 and the upper third electrode region 113 in the upper connection layer are also rectangular, and the upper first electrode region 111 and the upper second electrode region 112 are located at the same end. One end of the upper third electrode region 113 is used as a first end of the DBC substrate, and one ends of the upper first electrode region 111 and the upper second electrode region 112 are used as a second end of the DBC substrate.
As shown in fig. 2, the lower first electrode region 121, the lower second electrode region 122 and the lower third electrode region 123 in the lower connection layer are all rectangular, and the lower first electrode region 121 and the lower second electrode region 122 are both located at the first end of the DBC substrate, and the lower third electrode region 123 is located at the second end of the DBC substrate.
As shown in fig. 3, the upper first electrode region 111 and the upper second electrode region 112 overlap the lower third electrode region 123, specifically, when the upper first electrode region 111 and the upper second electrode region 112 project toward the lower third electrode region 123, the projections of the upper first electrode region 111 and the upper second electrode region 112 overlap the lower third electrode region 123. When the upper first electrode region 111 overlaps the lower third electrode region 123, the upper first electrode region 111 extends vertically toward the lower third electrode region 123 and is connected as one body.
The upper third electrode region 113 overlaps the lower first electrode region 121 and the lower second electrode region 122, and the upper third electrode region 113 overlaps the lower third electrode region 123 partially, specifically, when the upper third electrode region 113 projects toward the lower first electrode region 121, the lower second electrode region 122 and the lower third electrode region 123, the projection of the upper third electrode region 113 overlaps the lower first electrode region 121 and the lower second electrode region 122, and the projection of the upper third electrode region 113 overlaps the lower third electrode region 123 partially.
Further, the area of the upper third electrode region 113 is larger than the area of the upper first electrode region 111, and the area of the upper first electrode region 111 is larger than the area of the upper second electrode region 112;
and/or the area of the lower third electrode region 123 is larger than the area of the lower first electrode region 121, and the area of the lower first electrode region 121 is larger than the area of the lower second electrode region 122.
Specifically, when the DBC substrate package provided by the present invention is used to form a power module, the upper third electrode region 113 in the upper connection layer and the lower third electrode region 123 in the lower connection layer are used to package a chip, so that the area of the upper third electrode region 113 in the upper connection layer is preferably made larger than the areas of the upper first electrode region 111 and the upper second electrode region 112; the area of the lower third electrode region 123 in the lower connection layer is made larger than the areas of the lower first electrode region 121 and the lower second electrode region 122, so that the chip package is facilitated.
In addition, when the DBC substrate package is used to form the power module, the upper first electrode region 111 in the upper connection layer and the lower first electrode region 121 in the lower connection layer need to be used to connect more signal terminals, so in this embodiment, the area of the upper first electrode region 111 is larger than the area of the upper second electrode region 112, and the area of the lower first electrode region 121 is larger than the area of the lower second electrode region 122.
Preferably, in order to facilitate the preparation of the DBC substrate, the area of the upper first electrode region 111 is made equal to the area of the lower first electrode region 121, the area of the upper second electrode region 112 is made equal to the area of the lower second electrode region 122, and the area of the upper third electrode region 113 is made equal to the area of the lower third electrode region 123. Meanwhile, the distribution of each electrode area in the upper connection layer and the lower connection layer is centrosymmetric, that is, each electrode area in the lower connection layer rotates 180 ° around the center of the DBC substrate as a rotation center and then projects onto the upper connection layer, and at this time, the projections of the lower first electrode area 121, the lower second electrode area 122 and the lower third electrode area 123 in the lower connection layer are respectively overlapped with the upper first electrode area 111, the upper second electrode area 112 and the upper third electrode area 113 in the upper connection layer.
The invention also provides a power module, which comprises the DBC substrate, and an upper chip set and a lower chip set which are arranged on the DBC substrate, wherein the upper chip set is electrically connected with the lower chip set.
Specifically, the power module is packaged by the DBC substrate, and as can be seen from the above description, the upper first electrode region 111 and the lower third electrode region 123 of the DBC substrate are connected integrally, and the upper chipset is electrically connected to the lower third electrode region 123 through the upper first electrode region 111, so as to realize the electrical connection with the lower chipset.
Further, the upper chip set and the lower chip set comprise a plurality of chips, wherein,
The welding surface of the chip in the upper chip set is welded on the upper third electrode area 113 of the connecting layer on the DBC substrate through welding flux;
the bonding surface of the die in the lower chip set is bonded to the lower third electrode region 123 of the lower connection layer of the DBC substrate by solder.
Optionally, the solder includes, but is not limited to, sn, ag, and the like. In the implementation, the types, the number and the connection modes of the chips in the upper chip set and the lower chip set can be determined according to the circuit topology structure of the required power module, and the material of the solder can be selected according to the actual requirement.
In an embodiment of the present invention, the power module is a half-bridge module, and the structure of the power module formed by using the DBC substrate package is described below with reference to fig. 6 and 7 by taking the half-bridge module as an example:
The circuit topology of the half-bridge module is consistent with the prior art, and will not be described in detail herein. When the power module is a half-bridge module, the upper layer chipset includes an upper layer IGBT chip 1 and an upper layer FRD chip 2 antiparallel to the upper layer IGBT chip 1, and the lower layer chipset includes a lower layer IGBT chip 15 and a lower layer FRD chip 16 antiparallel to the lower layer IGBT chip 15. The IGBT chip and the FRD chip both comprise a front surface and a back surface corresponding to the front surface, and in general, the back surface of the IGBT chip is provided with a collector, and the front surface of the IGBT chip is provided with an emitter and a base. The back of the FRD chip is provided with a cathode, and the front of the FRD chip is provided with an anode, and in this embodiment, the IGBT chip and the back of the FRD chip are used as the bonding surfaces.
As shown in fig. 6, the bonding surfaces of the upper IGBT chip 1 and the upper FRD chip 2 are bonded in parallel to the upper third electrode region 113 by solder, and the emitter of the upper IGBT chip 1 is connected to the anode of the upper FRD chip 2 by the first connection strap 3. The emitter of the upper IGBT chip 1 is also connected to the upper first electrode region 111 via the second connection strap 4, and the base of the upper IGBT chip 1 is connected to the upper second electrode region 112 via the first connection strap 5.
As shown in fig. 7, the bonding surfaces of the lower IGBT chip 15 and the lower FRD chip 16 are bonded in parallel to the lower third electrode region 123 by solder, and the emitter of the lower IGBT chip 15 is connected to the anode of the lower FRD chip 16 by the third connection strap 17. The emitter of the lower IGBT chip 15 is also connected to the lower first electrode region 121 via the fourth connection strap 18, and the base of the lower IGBT chip 15 is connected to the lower second electrode region 122 via the second connection strap 19. Since the upper first electrode region 111 is connected integrally with the lower third electrode region 123, the emitter of the upper IGBT chip 1 is connected with the collector of the lower IGBT chip 15. The materials of the first connecting strip 3, the second connecting strip 4, the first connecting wire 5, the third connecting strip 17, the fourth connecting strip 18 and the second connecting wire 19 can be Cu.
Further, the power module further comprises an upper layer signal terminal group and a lower layer signal terminal group, wherein,
The upper layer signal terminal group comprises an upper layer first signal terminal 9 welded to the upper layer first electrode region 111, an upper layer second signal terminal 12 welded to the upper layer second electrode region 112, a module power supply positive electrode power terminal 7 welded to the upper layer third electrode region 113, and a module power output terminal 11 welded to the upper layer third electrode region 113;
The lower signal terminal group includes a lower first signal terminal 6 welded to the lower first electrode region 121, a lower second signal terminal 8 welded to the lower second electrode region 122, and a module power supply negative power terminal 14 welded to the lower first electrode region 121.
As can be seen from the above description, the conventional DBC is fixed on the external structure through the connection layer on the back side of the DBC during packaging, and typically, the external structure adopts a copper substrate, the copper substrate can provide mechanical support and a heat conduction path for the DBC, and at the same time, a heat sink can be further arranged on the surface of the copper substrate, on which the DBC is not fixed, to further dissipate heat of the DBC.
However, since the front and back sides of the DBC substrate provided by the present invention are used for packaging chips, the connection structure 10 is used to replace the conventional connection layer on the back side of the DBC to fix the DBC to the external structure, and in order to adapt to the connection structure 10, in one embodiment of the present invention, the external structure adopts an external copper frame 13 surrounding and fixed on the outer side of the connection structure 10. The outer copper frame 13 is utilized to provide mechanical support and a thermally conductive path for the DBC substrate in place of the copper substrate in a conventional DBC package. In addition, compared with a copper substrate with a radiator only arranged on one side, the radiator can be arranged on all four outer side surfaces of the outer copper frame 13, so that the radiating capability of the DBC substrate can be further improved.
It should be noted that the words "front", "back", "left", "right", "upper" and "lower" used in the above description refer to directions in the drawings of the present application, and the words "front" and "back", "inner" and "outer" refer to directions toward or away from, respectively, a specific component. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated.
The above is only a preferred embodiment of the present invention, and the present invention is not limited to the above examples. It is to be understood that other modifications and variations which may be directly derived or contemplated by those skilled in the art without departing from the spirit and concepts of the present invention are deemed to be included within the scope of the present invention.

Claims (10)

1. The DBC substrate with high power density and high heat dissipation performance is characterized by comprising an insulator, wherein the insulator comprises an upper insulating layer and a lower insulating layer corresponding to the upper insulating layer;
An upper connecting layer is prepared on the upper insulating layer, a lower connecting layer is prepared on the lower insulating layer, and the upper connecting layer and/or the lower connecting layer are/is used for packaging the chip.
2. The DBC substrate with high power density and high heat dissipation according to claim 1, further comprising a connection structure surrounding and fixedly connected to the upper and lower insulating layers;
after the connecting structure is fixedly connected with the upper insulating layer and the lower insulating layer, a cavity is formed between the upper insulating layer and the lower insulating layer, and cooling medium is filled in the cavity.
3. The high power density high heat sink DBC substrate of claim 1, wherein the upper interconnect layer includes an upper first electrode region and the lower interconnect layer includes a lower third electrode region, wherein,
The upper layer first electrode region penetrates through the upper insulating layer and the lower insulating layer and is connected with the lower layer third electrode region into a whole.
4. The DBC substrate with high power density and high heat dissipation according to claim 3, wherein the upper connection layer further comprises an upper second electrode region and an upper third electrode region, wherein the upper first electrode region, the upper second electrode region and the upper third electrode region are insulated and isolated by an upper insulation layer, and the upper first electrode region and the upper second electrode region are located at the same end of the upper connection layer;
the lower connecting layer further comprises a lower first electrode zone and a lower second electrode zone, wherein the lower first electrode zone, the lower second electrode zone and the lower third electrode zone are isolated in an insulating way through a lower insulating layer, and the lower first electrode zone and the lower second electrode zone are located at the same end of the lower connecting layer.
5. The DBC substrate with high power density and high heat dissipation according to claim 4, wherein the upper first electrode region and the upper second electrode region are overlapped with the lower third electrode region;
the upper third electrode region overlaps the lower first electrode region and the lower second electrode region, and the upper third electrode region overlaps the lower third electrode region partially.
6. The DBC substrate with high power density and high heat dissipation according to claim 5, wherein an area of the upper third electrode region is larger than an area of the upper first electrode region, and an area of the upper first electrode region is larger than an area of the upper second electrode region;
And/or the area of the lower third electrode region is larger than the area of the lower first electrode region, and the area of the lower first electrode region is larger than the area of the lower second electrode region.
7. The high power density high heat dissipation substrate according to any one of claims 1-6, wherein said upper insulating layer is provided with a first via hole and a second via hole communicating with said cavity;
When the cooling medium is cooling liquid, the cooling medium is injected into the cavity through the first through hole and/or the second through hole, and the cooling medium is static in the cavity or flows from the first through hole to the second through hole in the cavity.
8. A power module comprising the DBC substrate of any one of claims 1-7, and an upper chipset and a lower chipset disposed on the DBC substrate, the upper chipset electrically connected to the lower chipset.
9. The power module of claim 8, wherein the upper and lower chipsets each include a number of chips, wherein,
The welding surface of the chip in the upper chip set is welded on an upper third electrode area of a connecting layer on the DBC substrate through welding flux;
And the welding surface of the chip in the lower chip set is welded on the lower third electrode area of the lower connecting layer of the DBC substrate through welding flux.
10. The power module of claim 8, further comprising an upper signal terminal set and a lower signal terminal set, wherein,
The upper layer signal terminal group comprises an upper layer first signal terminal welded on the upper layer first electrode region, an upper layer second signal terminal welded on the upper layer second electrode region, a module power supply positive electrode power terminal welded on the upper layer third electrode region and a module power output terminal welded on the upper layer third electrode region;
The lower layer signal terminal group comprises a lower layer first signal terminal welded on the lower layer first electrode region, a lower layer second signal terminal welded on the lower layer second electrode region and a module power supply negative electrode power terminal welded on the lower layer first electrode region.
CN202410587550.1A 2024-05-13 2024-05-13 DBC substrate with high power density and high heat dissipation and power module Pending CN118522699A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN118782576A (en) * 2024-09-10 2024-10-15 四川富乐华半导体科技有限公司 Ceramic copper-clad carrier board and power supply board capable of mounting chips on both sides and manufacturing method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN118782576A (en) * 2024-09-10 2024-10-15 四川富乐华半导体科技有限公司 Ceramic copper-clad carrier board and power supply board capable of mounting chips on both sides and manufacturing method thereof
CN118782576B (en) * 2024-09-10 2024-12-27 四川富乐华半导体科技有限公司 Ceramic copper-clad carrier plate capable of mounting chips on two sides, power supply plate and manufacturing method

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