CN118522334A

CN118522334A - Read voltage adjusting method and memory device

Info

Publication number: CN118522334A
Application number: CN202410977852.XA
Authority: CN
Inventors: 请求不公布姓名; 吴宗霖
Original assignee: Hosin Global Electronics Co Ltd
Current assignee: Hosin Global Electronics Co Ltd
Priority date: 2024-07-22
Filing date: 2024-07-22
Publication date: 2024-08-20

Abstract

The invention provides a read voltage adjusting method and a memory device. The method comprises the following steps: reading the first physical unit based on a plurality of first read voltage levels to obtain detection information, wherein the detection information reflects the total number of first memory cells in the plurality of memory cells, and the critical voltage of the first memory cells is in a first voltage range; performing curve fitting according to the detection information to obtain a first function, wherein the first function is used for simulating the threshold voltage distribution of the memory cells in a two-dimensional space; acquiring first voltage regulation information according to a first function; and adjusting a second read voltage level corresponding to the first physical unit according to the first voltage adjustment information. Therefore, the correction efficiency of the read voltage level can be effectively improved, and the service life of the storage device can be prolonged.

Description

Read voltage adjusting method and memory device

Technical Field

The present invention relates to the field of memory technologies, and in particular, to a read voltage adjustment method and a memory device.

Background

As memory technology advances, the number of bits that each memory cell in a memory module (e.g., a flash memory module) can store increases. When data is to be read from the memory module, a plurality of predetermined read voltage levels can be used to read the data stored in the memory cells belonging to different states (states). However, after the memory module is used for a period of time, as the wear of the memory module increases, the preset read voltage levels may be severely shifted with respect to the threshold voltage distribution of the memory cells, thereby greatly reducing the correctness of the read data and possibly shortening the service life of the memory module.

Conventionally, although the read voltage level can be corrected by scanning the threshold voltage distribution of the memory cell, the correction efficiency of the conventional read voltage correction mechanism is greatly reduced if the threshold voltage distribution of the memory cell is too irregular.

Therefore, a method for adjusting the read voltage is needed to solve the above-mentioned problems.

Disclosure of Invention

The invention provides a read voltage adjusting method and a storage device, which can improve the correction efficiency of read voltage level and further prolong the service life of the storage device.

The embodiment of the invention provides a read voltage adjusting method for a memory device. The memory device includes a memory module. The memory module includes a plurality of physical units. The plurality of entity units includes a first entity unit. The first entity unit includes a plurality of storage units. The read voltage adjustment method includes: step a: reading the first physical unit based on a plurality of first read voltage levels to obtain detection information, wherein the detection information reflects the total number of first memory cells in the plurality of memory cells, and the critical voltage of the first memory cells is in a first voltage range; step b: performing curve fitting according to the detection information to obtain a first function, wherein the first function is used for simulating the threshold voltage distribution of the memory cells in a two-dimensional space; step c: acquiring first voltage adjustment information according to the first function; and d: and adjusting a second reading voltage level corresponding to the first entity unit according to the first voltage adjustment information.

The embodiment of the invention further provides a storage device, which comprises a connection interface, a memory module and a memory controller. The connection interface is used for connecting to a host system. The memory controller is connected to the connection interface and the memory module. The memory module includes a plurality of physical units. The plurality of entity units includes a first entity unit. The first entity unit includes a plurality of storage units. The memory controller is to: step a is performed to read the first physical unit based on a plurality of first read voltage levels to obtain detection information, wherein the detection information reflects the total number of first memory cells in the plurality of memory cells, and the threshold voltage of the first memory cells is within a first voltage range; executing step b to perform curve fitting according to the detection information to obtain a first function, wherein the first function is used for simulating the threshold voltage distribution of the memory cells in a two-dimensional space; executing step c to obtain first voltage adjustment information according to the first function; and executing step d to adjust a second read voltage level corresponding to the first physical unit according to the first voltage adjustment information.

Based on the above, after the first physical unit is read based on the plurality of first read voltage levels, the detection information can be obtained. In particular, the detection information may reflect a total number of first memory cells of the plurality of memory cells, and a threshold voltage of the first memory cells is within a first voltage range. After the detection information is obtained, a first function may be obtained by performing curve fitting based on the detection information. In particular, the first function may be used to simulate the threshold voltage distribution of the plurality of memory cells in two dimensions. According to the first function, first voltage adjustment information may be obtained. Then, a second read voltage level corresponding to the first physical unit may be adjusted according to the first voltage adjustment information. Therefore, the correction efficiency of the read voltage level can be effectively improved, and the service life of the storage device can be prolonged.

Drawings

FIG. 1 is a schematic diagram of a data storage system shown in accordance with an embodiment of the present invention;

FIG. 2 is a schematic diagram of a memory controller shown according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of a managed memory module shown in accordance with an embodiment of the present invention;

FIG. 4 is a schematic diagram showing the threshold voltage distribution of a plurality of memory cells according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of acquiring detection information according to an embodiment of the present invention;

FIG. 6 is a schematic diagram illustrating performing curve fitting according to a first reference point, according to an embodiment of the present invention;

FIG. 7 is a schematic diagram illustrating performing curve fitting according to a second reference point, according to an embodiment of the present invention;

FIG. 8 is a schematic diagram showing that the first candidate voltage adjustment information and the second candidate voltage adjustment information meet a preset condition according to an embodiment of the present invention;

fig. 9 is a flowchart of a read voltage adjustment method according to an embodiment of the present invention.

Detailed Description

Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.

FIG. 1 is a schematic diagram of a data storage system shown in accordance with an embodiment of the present invention. Referring to fig. 1, a data storage system 10 includes a host system 11 and a storage device 12. The storage device 12 may be connected to the host system 11 and may be used to store data from the host system 11. For example, the host system 11 may be a smart phone, a tablet computer, a notebook computer, a desktop computer, an industrial computer, a game machine, a server, or a computer provided in a specific carrier (e.g., a vehicle), or the like, and the type of the host system 11 is not limited thereto. Further, the storage device 12 may include a solid state disk, a USB flash drive, a memory card, or other type of non-volatile storage device.

The memory device 12 includes a connection interface 121, a memory module 122, and a memory controller 123. The connection interface 121 is used to connect the storage device 12 to the host system 11. For example, connection interface 121 may support an embedded multimedia card (embedded Multi-MEDIA CARD, EMMC), universal flash memory (Universal Flash Storage, UFS), peripheral component interconnect Express (PERIPHERAL COMPONENT INTERCONNECT EXPRESS, PCI Express), non-volatile memory Express (Non-Volatile Memory Express, NVM Express), serial advanced technology attachment (SERIAL ADVANCED Technology Attachment, SATA), universal serial bus (Universal Serial Bus, USB), or other types of connection interface standards. Accordingly, storage device 12 may communicate (e.g., exchange signals, instructions, and/or data) with host system 11 via connection interface 121.

The memory module 122 is used for storing data. For example, the memory module 122 may include one or more rewritable non-volatile memory modules. Each of the rewritable non-volatile memory modules may include one or more memory cell arrays. Memory cells in a memory cell array store data in the form of voltages (also referred to as threshold voltages). For example, the memory module 122 may include a single level memory cell (SINGLE LEVEL CELL, SLC) NAND-type flash memory module, a second level memory cell (Multi LEVEL CELL, MLC) NAND-type flash memory module, a third level memory cell (TRIPLE LEVEL CELL, TLC) NAND-type flash memory module, a fourth level memory cell (Quad LEVEL CELL, QLC) NAND-type flash memory module, and/or other memory modules having the same or similar characteristics.

The memory controller 123 is connected to the connection interface 121 and the memory module 122. Memory controller 123 may be considered a control core of storage device 12 and may be used to control storage device 12. For example, the memory controller 123 may be used to control or manage the operation of the storage device 12 in whole or in part. For example, the memory controller 123 may include a central processing unit (Central Processing Unit, CPU), or other programmable general purpose or special purpose microprocessor, digital signal Processor (DIGITAL SIGNAL Processor, DSP), programmable controller, application SPECIFIC INTEGRATED Circuits (ASIC), programmable logic device (Programmable Logic Device, PLD), or other similar device or combination of devices. In an embodiment, the memory controller 123 may comprise a flash memory controller.

Memory controller 123 may send a sequence of instructions to memory module 122 to access memory module 122. For example, memory controller 123 may send a sequence of write instructions to memory module 122 to instruct memory module 122 to store data in a particular memory location. For example, memory controller 123 can send a sequence of read instructions to memory module 122 to instruct memory module 122 to read data from a particular memory location. For example, memory controller 123 can send a sequence of erase instructions to memory module 122 to instruct memory module 122 to erase data stored in a particular memory cell. In addition, memory controller 123 may send other types of instruction sequences to memory module 122 to instruct memory module 122 to perform other types of operations, as the invention is not limited. The memory module 122 may receive a sequence of instructions from the memory controller 123 and access memory locations within the memory module 122 according to the sequence of instructions.

FIG. 2 is a schematic diagram of a memory controller according to an embodiment of the invention. Referring to fig. 1 and 2, the memory controller 123 includes a host interface 21, a memory interface 22, and a memory control circuit 23. The host interface 21 is used to connect to the host system 11 through the connection interface 121 to communicate with the host system 11. The memory interface 22 is used to connect to the memory module 122 to access the memory module 122.

The memory control circuit 23 is connected to the host interface 21 and the memory interface 22. The memory control circuit 23 may be used to control or manage the operation of the memory controller 123 in whole or in part. For example, the memory control circuit 23 may communicate with the host system 11 through the host interface 21 and access the memory module 122 through the memory interface 22. For example, the memory control circuit 23 may include a control circuit such as an embedded controller or a microcontroller. In the following embodiment, the explanation of the memory control circuit 23 is equivalent to the explanation of the memory controller 123.

In one embodiment, memory controller 123 may also include buffer memory 24. The buffer memory 24 is used for buffering data. For example, buffer memory 24 may be used to buffer instructions from host system 11, data from host system 11, and/or data from memory module 122. In one embodiment, the memory controller 123 may also include various circuit modules of other types (e.g., power management circuits, etc.), which are not limiting.

FIG. 3 is a schematic diagram illustrating managing memory modules according to an embodiment of the invention. Referring to fig. 1 to 3, the memory module 122 includes a plurality of physical units 301 (1) to 301 (D). Each physical unit comprises a plurality of memory cells and is used for nonvolatile memory data.

In one embodiment, a physical unit may include one or more physical programming units. One physical programming unit may include a plurality of physical sectors (sectors). For example, a physical sector may have a data size of 512 Bytes (Bytes, B), and a physical programming unit may include 8 physical sectors. However, the data capacity of one physical fan and/or the total number of physical fans included in one physical programming unit can be adjusted according to the practical requirements, and the present invention is not limited thereto. In one embodiment, a physical programmer may be considered a physical page. For example, the data capacity of one physical programming unit may be 4 kilobytes (4 KB), and the present invention is not limited thereto.

In one embodiment, one physical programmer is the minimum unit of synchronous write data in the memory module 122. For example, when performing a programming operation (also referred to as a write operation or a data write operation) on a physical programming unit to write data into the physical programming unit, a plurality of memory cells in the physical programming unit may be synchronously programmed to store corresponding data. For example, when programming a physical programming unit, a write voltage may be applied to the physical programming unit to change the threshold voltage of at least some of the memory cells in the physical programming unit. The threshold voltage of each memory cell may reflect the bit data stored by the memory cell.

In one embodiment, a physical erase unit may include a plurality of physical program units. Multiple physical program units in the same physical erase unit can be erased simultaneously. For example, when performing an erase operation on a physically erased cell, an erase voltage may be applied to a plurality of physically programmed cells in the physically erased cell to change the threshold voltage of at least some of the physically programmed cells. By performing an erase operation on a physically erased cell, data stored in the physically erased cell may be erased.

In one embodiment, the memory control circuit 23 may logically associate the physical units 301 (1) -301 (A) to the data area 31. The physical units 301 (1) -301 (a) in the data area 31 all store data (also referred to as user data) from the host system 11. For example, any entity in the data area 31 may store valid (valid) data and/or invalid (invalid) data.

In one embodiment, the memory control circuit 23 may logically associate the physical units 301 (A+1) -301 (B) to the idle (spare) region 32. For example, none of the physical units 301 (A+1) -301 (B) in the idle region 32 store data (e.g., valid data).

In one embodiment, if a certain physical unit does not store valid data, the physical unit may be associated with the idle area 32. In addition, the physical cells in the spare area 32 may be erased to erase the data in the physical cells. In one embodiment, the physical units in the idle region 32 are also referred to as idle physical units. In one embodiment, the free area 32 is also referred to as a free pool (free pool).

In one embodiment, when data is to be stored, the memory control circuit 23 may select one or more physical units from the idle area 32 and instruct the memory module 122 to store the data in the selected physical units. After storing data in a physical unit, the physical unit may be associated with the data area 31.

In one embodiment, the memory control circuit 23 may configure a plurality of logic units 302 (1) -302 (C) to map physical units in the data area 31. For example, a logical unit may correspond to a logical block address (Logical Block Address, LBA) or other logical management unit. One logical unit may be mapped to one or more physical units in the data area 31.

In one embodiment, if a physical unit is currently mapped by any logical unit, the memory control circuit 23 may determine that the data currently stored in the physical unit includes valid data. Conversely, if a physical unit is not currently mapped by any logical unit, the memory control circuit 23 may determine that the physical unit does not currently store any valid data.

In one embodiment, the memory control circuit 23 may record the mapping relationship between the logical unit and the physical unit in the logical-to-physical mapping table. In one embodiment, the memory control circuit 23 may instruct the memory module 122 to perform data reading, writing or erasing operations according to the information in the logical-to-physical mapping table.

In the following embodiments, a TLC NAND type flash memory module is used as an example of the memory module 122. However, in another embodiment, the same or similar operations may also be applied to SLC NAND type, MLC NAND type, QLC NAND type, or other types of memory modules, and the present invention is not limited.

In one embodiment, the memory control circuit 23 may instruct the memory module 122 to write specific data to at least one physical unit (also referred to as a first physical unit) in the memory module 122. The specific data may be, for example, data from the host system 11 or arbitrary data. For example, the particular data may be randomized such that the total number of bits "0" and "1" in the particular data tends to agree. For example, a plurality of memory cells in a programmed first physical cell may be programmed equally to store bits "111", "101", "001", "011", "010", "110", "100", and "000".

FIG. 4 is a schematic diagram illustrating threshold voltage distribution of a plurality of memory cells according to an embodiment of the present invention. FIG. 4 shows the threshold voltage distribution of the programmed memory cells after programming the plurality of memory cells in the first physical cell according to the specific data, wherein the horizontal axis represents the threshold voltage of the memory cells and the vertical axis represents the number of memory cells.

Referring to FIG. 4, in one embodiment, a programmed memory cell may have 8 states 41-48. The memory cells belonging to states 41-48 are used to store bits "111", "101", "001", "011", "010", "110", "100" and "000", respectively. In other words, states 41-48 correspond to preset bit values "111", "101", "001", "011", "010", "110", "100", and "000", respectively. However, in one embodiment, the total number of states 41-48 may be adjusted, and the predetermined bit value corresponding to each state may also be adjusted, which is not limited by the present invention.

In one embodiment, voltage levels (also referred to as read voltage levels) 401-407 may be applied to the first physical cells to read data stored by respective memory cells in the first physical cells. For example, by applying voltage levels 401-407 to each of the first physical cells, each of the first physical cells may be determined to belong to one of states 41-48, thereby obtaining data stored by each of the memory cells. For example, after applying the voltage levels 401-407 to the first physical cell, if a certain memory cell of the first physical cell is turned on by the voltage level 402 but not turned on by the voltage level 401, the threshold voltage of the memory cell is between the voltage levels 401 and 402. In this case, the memory control circuit 23 may determine that this memory cell belongs to state 42 and is used to store bit "101".

However, as the usage time of the first entity increases and/or the operating environment changes, performance degradation (degradation) may occur for at least some of the storage units in the first entity. After performance degradation occurs, states 41-48 may gradually approach each other or even overlap each other. In addition, after performance degradation occurs, states 41-48 may also become flatter. Therefore, after performance degradation, voltage levels 401-407 may be severely shifted compared to states 41-48. In this case, if the uncorrected voltage levels 401-407 are continuously used to read the first physical cell, the states of many memory cells in the first physical cell are misjudged, and thus the data read from the first physical cell contains too many errors. Therefore, how to correct the shifted read voltage level to improve the performance of the memory device 12 is one of the subjects of the study by those skilled in the art.

In one embodiment, the memory control circuit 23 may instruct the memory module 122 to read the first physical unit based on a plurality of voltage levels (also referred to as a first read voltage level) to obtain the detection information. In particular, the detection information may reflect a total number of specific memory cells (also referred to as first memory cells) in the first physical unit, and the threshold voltage of the first memory cells is within a specific voltage range (also referred to as a first voltage range).

In one embodiment, after instructing the memory module 122 to read the first physical unit based on the plurality of first read voltage levels, the memory control circuit 23 may retrieve (e.g., receive) the response data from the memory module 122. The response data may reflect the read results of each memory cell in the first physical cell in response to the plurality of first read voltage levels. The memory control circuit 23 can acquire the detection information based on the response data.

Fig. 5 is a schematic diagram of acquiring detection information according to an embodiment of the present invention. Referring to FIG. 5, the voltage level 501 may be one of the voltage levels 401-407 of FIG. 4. States 51 and 52 may be any two adjacent states of states 41-48 of fig. 4. For example, assuming states 51 and 52 are states 41 and 42 of fig. 4, voltage level 501 may be voltage level 401. Alternatively, assuming states 51 and 52 are states 42 and 43 of FIG. 4, voltage level 501 may be voltage level 402, and so on.

It should be noted that in the embodiment of fig. 5, voltage level 501 has been shifted (e.g., toward state 52) as compared to states 51 and 52. In this case, if the voltage level 501 is continuously used to read data from the first physical unit, it is easy to read a large number of erroneous bits from the first physical unit (e.g., misjudging many memory cells belonging to state 52 as belonging to state 51).

In one embodiment, the first read voltage level may include voltage levels 501-509. In one embodiment, the memory control circuit 23 may determine the voltage levels 502-509 according to the voltage level 501. For example, the memory control circuit 23 may subtract a predetermined voltage difference from the voltage level 501 to obtain the voltage level 502 and add the predetermined voltage difference to the voltage level 501 to obtain the voltage level 503. For example, the memory control circuit 23 may subtract 2 times the preset voltage difference from the voltage level 501 to obtain the voltage level 504 and add 2 times the preset voltage difference to the voltage level 501 to obtain the voltage level 505. By analogy, the memory control circuit 23 can determine the voltage levels 502-509 one by one according to the voltage level 501. In addition, the voltage difference between any two adjacent voltage levels 501 to 509 may be the same or different, which is not limited in the present invention.

In one embodiment, the voltage levels 501-509 may be used to define the voltage ranges R (1) -R (8). For example, voltage levels 501 and 502 may define voltage range R (1), voltage levels 501 and 503 may define voltage range R (2), voltage levels 502 and 504 may define voltage range R (3), voltage levels 503 and 505 may define voltage range R (4), voltage levels 504 and 506 may define voltage range R (5), voltage levels 505 and 507 may define voltage range R (6), voltage levels 506 and 508 may define voltage range R (7), and voltage levels 507 and 509 may define voltage range R (8). In one embodiment, the total number of the voltage levels 501-509 and the total number of the voltage ranges R (1) -R (8) can be adjusted according to the practical requirements, which is not limited by the present invention.

In one embodiment, the memory control circuit 23 may instruct the memory module 122 to read the first physical unit and obtain the response data from the memory module 122 based on the voltage levels 501-509. The response data may reflect the read results of each memory cell in the first physical cell in response to the voltage levels 501-509. For example, the read result may reflect whether a certain memory cell in the first physical cell is turned on by at least one of the voltage levels 501-509. Then, the memory control circuit 23 can obtain the detection information according to the response data. For example, the detection information may reflect the total number of all the memory cells (i.e., the first memory cells) having the threshold voltage within the voltage range R (i) (i.e., the first voltage range) in the first physical cell. For example, if one of the memory cells in the first physical unit is turned on by the voltage level 504 but not turned on by the voltage level 506, the threshold voltage of the memory cell is in the voltage range R (5).

In one embodiment, the detection information may include the number information N (1) to N (8). The quantity information N (i) may reflect the total number of all memory cells in the first physical cell whose threshold voltages are within the voltage range R (i). For example, let N (i) be "200", which means that the threshold voltage of "200" memory cells in the first physical cell is within the voltage range R (i). That is, the quantity information N (1) to N (8) may reflect the total number of all the memory cells having the threshold voltages within the voltage ranges R (1) to R (8) in the first physical cell, respectively.

In one embodiment, the memory control circuit 23 may perform curve fitting (curve fitting) to obtain at least one function (also referred to as a first function) according to the detection information. The first function may be used to simulate the threshold voltage distribution of a plurality of memory cells in the first physical cell in two dimensions. It should be noted that the threshold voltage distribution of the plurality of memory cells in the first physical unit simulated by the first function may reflect or be close to the actual threshold voltage distribution of a portion of the plurality of memory cells in the first physical unit, but there may still be a difference therebetween.

In an embodiment, the memory control circuit 23 may establish a plurality of reference points (also referred to as first reference points) in a two-dimensional space according to the detection information. The memory control circuit 23 may perform curve fitting according to the plurality of first reference points to obtain a first function.

FIG. 6 is a schematic diagram illustrating performing curve fitting according to a first reference point, according to an embodiment of the present invention. Referring to fig. 6, it is assumed that the X-axis and the Y-axis of the two-dimensional space shown in fig. 6 correspond to the horizontal axis and the vertical axis of fig. 5, respectively. For example, similar to fig. 5, the X-axis and the Y-axis of the two-dimensional space shown in fig. 6 may correspond to the voltage value (i.e., the threshold voltage) and the number of memory cells, respectively.

In one embodiment, the memory control circuit 23 can establish the reference points 611-618 (i.e. the first reference points) in the two-dimensional space of fig. 6 according to the detection information. For example, the memory control circuit 23 can establish the reference points 611-618 according to the quantity information N (1) -N (8). The reference points 611-618 may reflect the total number of all the memory cells having the threshold voltages within the voltage ranges R (1) -R (8) in the first physical cell. For example, the reference point 611 may reflect the total number of all memory cells (i.e., N (1)) in the first physical cell whose threshold voltage is within the voltage range R (1). Thus, the value of the reference point 611 corresponding to the X-axis may be a representative value of the voltage range R (1) (e.g., a voltage value corresponding to the voltage range R (1)), and the value of the reference point 611 corresponding to the Y-axis may be N (1). Similarly, the reference point 612 may reflect the total number of all memory cells (i.e., N (2)) having threshold voltages within the voltage range R (2) in the first physical cell. Thus, the value of reference point 612 corresponding to the X-axis may be a representative value of voltage range R (2) (e.g., a voltage value corresponding to voltage range R (2)), while the value of reference point 612 corresponding to the Y-axis may be N (2), and so on. It should be noted that the distribution of the reference points 611 to 618 in the two-dimensional space can be as shown in fig. 6, but can also be changed according to the actual situation, and the invention is not limited thereto.

In one embodiment, the memory control circuit 23 may perform curve fitting according to the reference points 611-618 to obtain the first function. For example, the first function may reflect a curve (also referred to as a simulated curve) 61 in the two-dimensional space of fig. 6. Curve 61 may be used to simulate the threshold voltage distribution of a plurality of memory cells in a first physical cell in the two-dimensional space. In particular, curve 61 may be used to simulate the threshold voltage distribution of the plurality of memory cells at the interface of states 51 and 52 of FIG. 5 in the two-dimensional space.

In one embodiment, the first function may be expressed as y=f (x). For example, f (x) is a quadratic polynomial obtained by the curve fitting. In one embodiment, the first function may be expressed by other mathematical formulas, which is not limited by the present invention.

In one embodiment, after the first function is obtained, the memory control circuit 23 may obtain the voltage adjustment information (also referred to as the first voltage adjustment information) according to the first function. For example, according to curve 61, memory control circuit 23 may determine the first voltage adjustment information as Δv. The first voltage adjustment information may be used to adjust a read voltage level (also referred to as a second read voltage level) corresponding to the first physical cell.

It should be noted that, in the embodiment of fig. 6, the voltage adjustment direction indicated by the first voltage adjustment information is left-adjusted along the X-axis in the two-dimensional space (i.e. the second reading voltage level is lowered), so Δv is negative (i.e. Δv < 0). However, in one embodiment, if the voltage adjustment direction indicated by the first voltage adjustment information is right-adjusted along the X-axis in the two-dimensional space (i.e. the second reading voltage level is increased), Δv may also be positive (i.e. Δv > 0).

In one embodiment, the memory control circuit 23 can adjust the read voltage level (i.e. the second read voltage level) corresponding to the first physical unit according to the first voltage adjustment information. For example, the memory control circuit 23 may adjust the second read voltage level from the voltage level 501 to the voltage level 601 according to the first voltage adjustment information (i.e., Δv). For example, the memory control circuit 23 may add Δv to the voltage level 501 to obtain the voltage level 601. In one embodiment, the corrected voltage level 601 is closer to the valley position of the curve 61 than the voltage level 501.

In one embodiment, the operation of adjusting the second read voltage level may be regarded as an operation of correcting the second read voltage level. In one embodiment, reading the first physical unit based on the corrected voltage level 601 may read more accurate (e.g., less erroneous bits) data from the first physical unit than the voltage level 501.

In an embodiment, the memory control circuit 23 may determine another reference point (also referred to as a third reference point) in the two-dimensional space according to a first function. The third reference point may reflect an extremum position of the simulated curve. Taking fig. 6 as an example, the third reference point may be reference point 62. The reference point 62 may reflect the extremum position of the curve 61 (i.e., the valley position of the curve 61). For example, the reference point 62 may reflect the smallest y that can be obtained by substituting the value of the reference point 62 corresponding to the X-axis into the first function (e.g., y=f (X)). Then, the memory control circuit 23 can obtain the first voltage adjustment information according to the third reference point. For example, the first voltage adjustment information may reflect a difference (i.e., ΔV) between a value of the reference point 62 corresponding to the X-axis and the voltage level 501.

It should be noted that in the embodiment of FIG. 6, the reference points 611-618 are all located on the curve 61. That is, the curve 61 may connect (i.e., serially connect) the reference points 611-618 and exhibit a smooth parabolic shape. In practice, however, the first reference points may not be regularly distributed over the curve 61 as shown in fig. 6. Or after connecting the first reference points, the curve 61 may not exhibit a smooth parabolic shape. In this case, the first function may not be able to be obtained by simply performing the curve fitting on the first reference point.

In an embodiment, the memory control circuit 23 may obtain a plurality of reference points (also referred to as a second reference point) in the two-dimensional space according to the plurality of first reference points. In particular, the distribution of the plurality of first reference points in the two-dimensional space may be different from the distribution of the plurality of second reference points in the two-dimensional space. The memory control circuit 23 may perform the curve fitting according to the plurality of second reference points to obtain a first function.

Fig. 7 is a schematic diagram illustrating performing curve fitting according to a second reference point, according to an embodiment of the present invention. Referring to fig. 7, assume that the first reference points include reference points 711-718. In one embodiment, no curve may connect (i.e., series) the reference points 711-718 and may exhibit a smooth parabolic shape.

In one embodiment, the memory control circuit 23 may obtain reference points 721-726 (i.e., second reference points) according to the reference points 711-718. Reference points 711-718 and 721-726 are all located in the same two-dimensional space. However, the distribution of the reference points 721 to 726 in the two-dimensional space is different from the distribution of the reference points 711 to 718 in the two-dimensional space. It should be noted that the distribution of the reference points 711-718 and 721-726 in the two-dimensional space may be as shown in fig. 7, but may also be changed according to the actual situation, and the present invention is not limited thereto.

In one embodiment, the memory control circuit 23 may perform curve fitting according to the reference points 721-726 to obtain the first function. For example, the first function may reflect a curve (i.e., a simulated curve) 71 in the two-dimensional space of FIG. 7. Curve 71 may be used to simulate the threshold voltage distribution of a plurality of memory cells in a first physical cell in the two-dimensional space. In particular, similar to curve 61 of FIG. 6, curve 71 may also be used to simulate the threshold voltage distribution of the plurality of memory cells at the interface of states 51 and 52 of FIG. 5 in the two-dimensional space.

It should be noted that in the embodiment of fig. 7, the reference points 721-726 (i.e., the second reference points) are all located on the curve 71. Curve 71 may connect (i.e., series) reference points 721-726 and exhibit a smooth parabolic shape. In addition, at least one of the reference points 711-718 (i.e., the first reference point) is not located on the curve 71. That is, the curve 71 is not connected (i.e., serially connected) to at least one of the reference points 711-718.

In the embodiment of fig. 7, the first function can be generated based on the reference points 721-726 by re-establishing the reference points 721-726 (i.e., the second reference points) in the second space, even though the reference points 711-718 (i.e., the first reference points) in the second space cannot be directly used to generate the first function, as compared to fig. 6. Thus, the technical problem that the first function cannot be obtained by performing the curve fitting on the first reference point in some cases can be overcome.

In one embodiment, the memory control circuit 23 may obtain the second reference point according to the following equations (1.1) - (1.3).

A=lerp(P0, P1, t)=(1-t)×P0+t×P1 (1.1)

B=lerp(P1, P2, t)=(1-t)×P1+t×P2 (1.2)

P=lerp(A, B, t)=(1-t)×A+t×B (1.3)

In equations (1.1) - (1.3), lerp () is a linear difference algorithm, P0, P1, and P2 represent three first reference points (e.g., reference points 711, 712, and 713) adjacent to each other in the two-dimensional space, P is one second reference point (e.g., reference point 721) in the two-dimensional space calculated based on P0, P1, and P2, and t is a constant (e.g., t is between 0 and 1). It should be noted that equations (1.1) - (1.3) may be adjusted or replaced according to the practical requirements, and the present invention is not limited.

In one embodiment, the coordinate information of each second reference point (i.e., P) can be obtained by sequentially substituting the coordinate information of the first reference points (i.e., P0, P1, and P2) in the two-dimensional space into equations (1.1) - (1.3). The second reference point may then be used to generate the first function. Thus, the technical problem that the first function cannot be obtained by performing the curve fitting on the first reference point in some cases can be overcome.

In one embodiment, after the first voltage adjustment information is obtained, the memory control circuit 23 may adjust at least one of the plurality of first read voltage levels (e.g., at least one of the voltage levels 501-509 of fig. 5) according to the first voltage adjustment information. Then, the memory control circuit 23 may repeat (i.e. iterate) the above-mentioned operations (also referred to as step a) of reading the first physical unit based on the plurality of first read voltage levels to obtain the detection information, performing curve fitting (also referred to as step b) of obtaining the first function based on the detection information, and obtaining the first voltage adjustment information (also referred to as step c) based on the first function. Details of the related operations are described above, and the detailed description thereof is not repeated here.

In one embodiment, the first voltage adjustment information is finally converged (approached) to the optimal value by repeating (i.e., iterating) the steps a to c. Then, the memory control circuit 23 may adjust the second read voltage level (e.g., the voltage level 501 of fig. 5) according to the first voltage adjustment information. Therefore, the correction efficiency of the second reading voltage level can be effectively improved, and the number of error bits read when the first physical unit is read by using the second reading voltage level later can be effectively reduced.

In one embodiment, the memory control circuit 23 may update a count value every time an iteration is performed (e.g., every time steps a through c are performed). For example, the memory control circuit 23 may increment the count value by one to update the count value. If the count value reaches the predetermined value, the memory control circuit 23 may stop the iteration. Thus, the above iterative operation can be prevented from being excessively performed. However, if the count value does not reach the preset value, the memory control circuit 23 may continue to perform the above-mentioned iteration to continuously optimize the first voltage adjustment information.

In one embodiment, the memory control circuit 23 may determine whether the first voltage adjustment information (also referred to as the first candidate voltage adjustment information) obtained in the previous time and the first voltage adjustment information (also referred to as the second candidate voltage adjustment information) obtained in the current time (i.e. the next time) meet the preset condition. For example, the first candidate voltage adjustment information includes first voltage adjustment information obtained by performing step c (i.e., the operation of obtaining the first voltage adjustment information according to the first function) last time. The second candidate voltage adjustment information includes the first voltage adjustment information obtained by currently (i.e., the next time) performing step c.

In one embodiment, if the first candidate voltage adjustment information and the second candidate voltage adjustment information meet the preset condition, the memory control circuit 23 may obtain another voltage adjustment information (also referred to as the second voltage adjustment information) according to the first candidate voltage adjustment information and the second candidate voltage adjustment information. After acquiring the second voltage adjustment information, the memory control circuit 23 may determine the second voltage adjustment information as the first voltage adjustment information. The memory control circuit 23 may then proceed to perform the next iteration based on the first voltage adjustment information or adjust the second read voltage level (e.g., voltage level 501 of fig. 5) based on the first voltage adjustment information. However, in an embodiment, if the first candidate voltage adjustment information and the second candidate voltage adjustment information do not meet the preset condition, the memory control circuit 23 may not perform the operation of determining the second voltage adjustment information as the first voltage adjustment information.

In an embodiment, the voltage adjustment range indicated by the second voltage adjustment information may be between the voltage adjustment range indicated by the first candidate voltage adjustment information and the voltage adjustment range indicated by the second candidate voltage adjustment information. For example, assuming that the voltage adjustment amplitude indicated by the first candidate voltage adjustment information is |Δv (1) | and the voltage adjustment amplitude indicated by the second candidate voltage adjustment information is |Δv (2) |, the voltage adjustment amplitude indicated by the second voltage adjustment information may be between |Δv (1) | and |Δv (2) |.

In one embodiment, the memory control circuit 23 may determine whether the voltage adjustment direction indicated by the first candidate voltage adjustment information is the same as the voltage adjustment direction indicated by the second candidate voltage adjustment information. If the voltage adjustment direction indicated by the first candidate voltage adjustment information is different from the voltage adjustment direction indicated by the second candidate voltage adjustment information (for example, Δv (1) >0 and Δv (2) <0, or Δv (1) <0 and Δv (2) > 0), the memory control circuit 23 may determine that the first candidate voltage adjustment information and the second candidate voltage adjustment information meet the preset condition (as shown in fig. 8). However, if the voltage adjustment direction indicated by the first candidate voltage adjustment information is the same as the voltage adjustment direction indicated by the second candidate voltage adjustment information (e.g., Δv (1) >0 and Δv (2) >0, or Δv (1) <0 and Δv (2) < 0), the memory control circuit 23 may determine that the first candidate voltage adjustment information and the second candidate voltage adjustment information do not meet the preset condition. It should be noted that, the operation of determining whether the first candidate voltage adjustment information and the second candidate voltage adjustment information meet the preset condition may also be adjusted according to the actual requirement, which is not limited by the present invention.

Fig. 9 is a flowchart of a read voltage adjustment method according to an embodiment of the present invention. Referring to fig. 9, in step S901, a first physical unit is read based on a plurality of first read voltage levels to obtain detection information, wherein the detection information reflects a total number of first memory cells in the first physical unit, and a threshold voltage of the first memory cells is within a first voltage range (i.e. step a). In step S902, curve fitting is performed according to the detection information to obtain a first function, wherein the first function is used to simulate the threshold voltage distribution of a plurality of memory cells in the first physical cell in two-dimensional space (i.e. step b). In step S903, first voltage adjustment information is obtained according to a first function (i.e., step c). In step S904, a second read voltage level corresponding to the first physical unit is adjusted according to the first voltage adjustment information (i.e., step d).

However, the steps in fig. 9 are described in detail above, and will not be described again here. It should be noted that each step in fig. 9 may be implemented as a plurality of program codes or circuits, which is not limited by the present invention. In addition, the method of fig. 9 may be used with the above exemplary embodiment, or may be used alone, and the present invention is not limited thereto.

In summary, the read voltage adjustment method and the memory device provided by the present invention can obtain a first function for simulating the threshold voltage distribution of a plurality of memory cells in a first physical cell by performing curve fitting (and reconstructing parameter points), and correct the read voltage level corresponding to the first physical cell according to the first function. Therefore, the correction efficiency of the read voltage level can be effectively improved, and the service life of the storage device can be prolonged.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.

Claims

1. A read voltage adjustment method for a memory device, wherein the memory device comprises a memory module comprising a plurality of physical units including a first physical unit comprising a plurality of memory units, and the read voltage adjustment method comprises:

Step a: reading the first physical unit based on a plurality of first read voltage levels to obtain detection information, wherein the detection information reflects the total number of first memory cells in the plurality of memory cells, and the critical voltage of the first memory cells is in a first voltage range;

Step b: performing curve fitting according to the detection information to obtain a first function, wherein the first function is used for simulating the threshold voltage distribution of the memory cells in a two-dimensional space;

Step c: acquiring first voltage adjustment information according to the first function; and

Step d: and adjusting a second reading voltage level corresponding to the first entity unit according to the first voltage adjustment information.

2. The read voltage adjustment method of claim 1, wherein the step of performing the curve fitting to obtain the first function according to the detection information comprises:

establishing a plurality of first reference points in the two-dimensional space according to the detection information; and

The curve fitting is performed according to the plurality of first reference points to obtain the first function.

3. The method of claim 2, wherein performing the curve fit from the plurality of first reference points to obtain the first function comprises:

Obtaining a plurality of second reference points in the two-dimensional space according to the plurality of first reference points, wherein the distribution of the plurality of first reference points in the two-dimensional space is different from the distribution of the plurality of second reference points in the two-dimensional space; and

The curve fitting is performed according to the plurality of second reference points to obtain the first function.

4. The method of claim 3, wherein the first function reflects a simulated curve in the two-dimensional space, and the plurality of second reference points are all located on the simulated curve.

5. The read voltage adjustment method of claim 2, wherein the first function reflects a simulated curve in the two-dimensional space and at least one of the plurality of first reference points is not located on the simulated curve.

6. The read voltage adjustment method according to claim 1, wherein the first function reflects a simulation curve in the two-dimensional space, and the step of obtaining the first voltage adjustment information according to the first function includes:

Determining a third reference point in the two-dimensional space according to the first function, wherein the third reference point reflects the extreme value position of the simulation curve; and

And acquiring the first voltage adjustment information according to the third reference point.

7. The read voltage adjustment method according to claim 1, further comprising:

Adjusting the plurality of first read voltage levels according to the first voltage adjustment information; and

Repeating steps a to c according to the adjusted plurality of first read voltage levels.

8. The read voltage adjustment method of claim 7, further comprising:

Judging whether first candidate voltage adjustment information and second candidate voltage adjustment information meet preset conditions, wherein the first candidate voltage adjustment information comprises the first voltage adjustment information obtained in the previous execution of the step c, and the second candidate voltage adjustment information comprises the first voltage adjustment information obtained in the current execution of the step c;

if the first candidate voltage adjustment information and the second candidate voltage adjustment information accord with the preset condition, obtaining second voltage adjustment information according to the first candidate voltage adjustment information and the second candidate voltage adjustment information; and

The second voltage adjustment information is determined as the first voltage adjustment information.

9. The method of claim 8, wherein the voltage adjustment magnitude indicated by the second voltage adjustment information is between the voltage adjustment magnitude indicated by the first candidate voltage adjustment information and the voltage adjustment magnitude indicated by the second candidate voltage adjustment information.

10. The method of claim 8, wherein determining whether the first candidate voltage adjustment information and the second candidate voltage adjustment information meet the predetermined condition comprises:

And if the voltage adjustment direction indicated by the first candidate voltage adjustment information is different from the voltage adjustment direction indicated by the second candidate voltage adjustment information, judging that the first candidate voltage adjustment information and the second candidate voltage adjustment information accord with the preset condition.

11. A memory device, comprising:

A connection interface for connecting to a host system;

A memory module; and

A memory controller connected to the connection interface and the memory module,

Wherein the memory module comprises a plurality of physical units including a first physical unit comprising a plurality of memory units, and the memory controller is to:

Step a is executed to read the first physical unit based on a plurality of first read voltage levels to obtain detection information, wherein the detection information reflects the total number of first memory cells in the plurality of memory cells, and the critical voltage of the first memory cells is within a first voltage range;

executing step b to perform curve fitting according to the detection information to obtain a first function, wherein the first function is used for simulating the threshold voltage distribution of the memory cells in a two-dimensional space;

executing step c to obtain first voltage adjustment information according to the first function; and

Step d is performed to adjust a second read voltage level corresponding to the first physical unit according to the first voltage adjustment information.

12. The storage device of claim 11, wherein the operation of the memory controller performing the curve fit to retrieve the first function in accordance with the detection information comprises:

13. The storage device of claim 12, wherein the operation of the memory controller performing the curve fit from the plurality of first reference points to derive the first function comprises:

14. The storage device of claim 13, wherein the first function reflects a simulated curve in the two-dimensional space and the plurality of second reference points are all located on the simulated curve.

15. The storage device of claim 12, wherein the first function reflects a simulated curve in the two-dimensional space and at least one of the plurality of first reference points is not located on the simulated curve.

16. The storage device of claim 11, wherein the first function reflects a simulated curve in the two-dimensional space, and the operation of the memory controller to retrieve the first voltage adjustment information according to the first function comprises:

17. The storage device of claim 11, wherein the memory controller is further to:

18. The storage device of claim 17, wherein the memory controller is further to:

19. The memory device of claim 18, wherein a voltage adjustment magnitude indicated by the second voltage adjustment information is between a voltage adjustment magnitude indicated by the first candidate voltage adjustment information and a voltage adjustment magnitude indicated by the second candidate voltage adjustment information.

20. The memory device of claim 18, wherein the operation of the memory controller determining whether the first candidate voltage adjustment information and the second candidate voltage adjustment information meet the preset condition comprises: