CN118508962B - Circuitry to reduce sampling skew in analog-to-digital converters - Google Patents
Circuitry to reduce sampling skew in analog-to-digital converters Download PDFInfo
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- CN118508962B CN118508962B CN202410661846.3A CN202410661846A CN118508962B CN 118508962 B CN118508962 B CN 118508962B CN 202410661846 A CN202410661846 A CN 202410661846A CN 118508962 B CN118508962 B CN 118508962B
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- 238000006243 chemical reaction Methods 0.000 claims abstract description 32
- 230000000630 rising effect Effects 0.000 claims abstract description 18
- 230000015556 catabolic process Effects 0.000 abstract description 3
- 238000006731 degradation reaction Methods 0.000 abstract description 3
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/10—Calibration or testing
- H03M1/1009—Calibration
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/0617—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
- H03M1/1245—Details of sampling arrangements or methods
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
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Abstract
The invention discloses a circuit system for reducing sampling deflection of an analog-to-digital converter, which comprises the analog-to-digital converter, a conversion clock signal, N paths of phase clock signals, a clock selection circuit and a clock selection circuit, wherein the conversion clock signal is sent to the analog-to-digital converter by a host computer, the conversion clock signal starts conversion of the analog-to-digital converter, the N paths of phase clock signals are arranged in the analog-to-digital converter, the periods of the N paths of phase clock signals are identical and are t clk, the phase difference between two adjacent paths of clock signals is t clk/N, N > =2, the clock selection circuit is connected with the conversion clock signal and the N paths of phase clock signals, and after the analog-to-digital converter receives the conversion clock signal, the clock selection circuit selects a path of clock signal with the nearest rising edge distance from the N paths of phase clock signals as a sampling edge of the analog-to-digital converter, and samples an input signal. The system can reduce sampling edge jitter of the analog-to-digital converter of asynchronous clock trigger sampling, thereby reducing degradation of signal-to-noise ratio of the analog-to-digital converter of clock jitter.
Description
Technical Field
The present invention relates to the field of integrated circuit design. More particularly, the present invention relates to circuitry for reducing sample skew in analog to digital converters.
Background
In some analog-to-digital converters (ADCs), the conversion clock is derived from the clock clk_cnv sent from the host, and the rising edge of clk_cnv initiates the conversion of the ADC, which is the frequency of clk_cnv. In order to realize the oversampling function, it is also necessary to generate a clock with a higher frequency than the slew rate inside the chip. The method realized at present comprises 1, using PLL (Phase Locked Loop) to generate a high-frequency clock, 2, using DLL (Delay-locked Loop) to generate a high-frequency clock, and 3, using OSC (Operation System Clock) to generate a high-frequency clock. In both method 1 and method 2, clk_cnv is required to be a periodic signal, which limits the application scenario of ADC. For example, the host initiates the ADC conversion aperiodically from clk_cnv, in which case the PLL and DLL cannot function properly. In the method 3, an OSC is designed inside the chip, and a clock clk_osc which is not homologous to clk_cnv is generated, wherein clk_cnv is a low frequency clock, and clk_osc is a high frequency clock. After the rising edge of clk_cnv arrives, the ADC completes sampling the input signal with the first rising edge of clk_osc as the sampling edge of the ADC, and the skew between this rising edge and the rising edge of clk_cnv is noted tskew. Since clk_osc and clk_cnv are non-homologous clocks, there is a frequency deviation between them, which results in tskew being not fixed, ranging between 0 and 1 clk_osc clock period (tclk), a variation called jitter of the ADC sampling edge, which can cause degradation of the ADC signal-to-noise ratio (SNR), especially at high frequency signal inputs.
Disclosure of Invention
The present invention provides a circuit system for reducing analog-to-digital converter sampling skew, which can reduce sampling edge jitter of an analog-to-digital converter of asynchronous clock trigger sampling, thereby reducing degradation of signal-to-noise ratio of the clock jitter.
To achieve these objects and other advantages and in accordance with the purpose of the invention, a circuit system for reducing sampling skew of an analog-to-digital converter is provided, comprising:
An analog-to-digital converter;
A conversion clock signal which is sent to the analog-to-digital converter by the host computer and starts the conversion of the analog-to-digital converter;
The N paths of phase clock signals are arranged in the analog-to-digital converter, the periods of the N paths of phase clock signals are the same and are t clk, and the phase difference of two adjacent paths of clock signals is t clk/N, wherein N > =2;
And the clock selection circuit is connected with the conversion clock signal and the N-path phase clock signals, and when the analog-to-digital converter receives the conversion clock signal, the clock selection circuit selects one path of clock signal with the rising edge closest to the rising edge of the conversion clock signal from the N-path phase clock signals as the sampling edge of the analog-to-digital converter to sample the input signal.
Preferably, the circuitry for reducing sampling skew of the analog-to-digital converter, the clock selection circuit specifically includes:
The switching clock signals are connected with the data pin D and the RN reset pin of each first-stage D trigger, and the N paths of phase clock signals are sequentially connected with the N first-stage D triggers in a one-to-one correspondence manner;
The output ends of the N first-stage D triggers are sequentially connected with the N AND gates in a one-to-one correspondence manner, and the output end of the other first-stage D trigger adjacent to each first-stage D trigger is connected to the AND gate corresponding to the first-stage D trigger after being subjected to non-processing;
the output ends of the N AND gates are correspondingly connected with the N second-stage D triggers one by one;
The output end of each second-stage D trigger is connected with the enabling signal input end of a tri-state gate, wherein phase clock signals corresponding to the tri-state gate, the second-stage D trigger, the AND gate and the first-stage D trigger are also connected to the tri-state gate;
wherein a phase clock signal that causes the tri-state gate enable signal to go to a1 level is provided as an output clock onto the clk_sel pin.
Preferably, the circuitry for reducing sampling skew of the analog-to-digital converter is configured to convert the clock signal to a low frequency clock signal and the N-way phase clock signal to a high frequency clock signal.
Preferably, the circuit system for reducing sampling skew of the analog-to-digital converter is characterized in that data pins D of N second stage D flip-flops are grounded, and the tri-state gate is a unidirectional tri-state gate.
Preferably, the circuitry for reducing the sampling skew of the analog-to-digital converter uses a multiphase clock of a ring oscillator of the analog-to-digital converter when the value of N is 4.
Preferably, the circuit system for reducing sampling skew of the analog-to-digital converter, and the clock selection circuit is specifically connected with the following relationship:
the conversion clock signal CLK_CNV is respectively connected to the RN reset pins of the 4 first-stage D flip-flops, the data pins D of the 4 first-stage D flip-flops and the RN reset pins of the 4 second-stage D flip-flops;
The first phase clock signal CK0 is connected with a first-stage D trigger and a first three-state gate T0, the second phase clock signal CK1 is connected with a second first-stage D trigger and a second three-state gate T1, the third phase clock signal CK2 is connected with a third first-stage D trigger and a third three-state gate T2, and the fourth phase clock signal CK3 is connected with a fourth first-stage D trigger and a fourth three-state gate T3;
the output end signal Q0 of the first-stage D trigger is connected with a second AND gate, is connected with the first AND gate after being subjected to non-processing, the output end signal Q1 of the second first-stage D trigger is connected with a third AND gate after being subjected to non-processing, the output end signal Q2 of the third first-stage D trigger is connected with a fourth AND gate, is connected with the third AND gate after being subjected to non-processing, and the output end signal Q3 of the fourth first-stage D trigger is connected with the first AND gate and is connected with the fourth AND gate after being subjected to non-processing;
The output end signal P0 of the first AND gate is connected with a fourth second-stage D trigger, the output end signal P1 of the second AND gate is connected with the first second-stage D trigger, the output end signal P2 of the third AND gate is connected with the second-stage D trigger, and the output end signal P3 of the fourth AND gate is connected with the third second-stage D trigger;
The output end signal S0 of the first second-stage trigger is connected with the first three-state gate phase T0, the output end signal S1 of the second-stage trigger is connected with the second three-state gate phase T1, the output end signal S2 of the third second-stage trigger is connected with the third three-state gate phase T2, and the output end signal S3 of the fourth second-stage trigger is connected with the fourth three-state gate phase T3;
four tri-state gates are connected to clk_sel.
The invention has the advantages that as N paths of phase clock signals are arranged in the analog-to-digital converter, the periods of the N paths of phase clock signals are the same and are t clk, and the phase difference of two adjacent paths of clock signals is t clk/N, when the analog-to-digital converter receives the converted clock signals, the clock selection circuit selects one path of clock signals with the nearest rising edge from the N paths of phase clock signals as the sampling edge of the analog-to-digital converter, compared with the traditional structure, the maximum clock skew is reduced to be 1/N, and the influence of clock jitter on the signal-to-noise ratio of the analog-to-digital converter is obviously reduced. In addition, the circuit system provided by the invention is suitable for converting clock signals sent by a host into periodic signals and also suitable for converting clock signals into sporadic signals, and has no limitation, so that the sampling conversion with low power consumption is realized.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention.
Drawings
FIG. 1 is a schematic diagram of a clock selection circuit according to an embodiment of the present invention;
FIG. 2 is a timing diagram of a clock selection circuit according to an embodiment of the invention;
FIG. 3 is a schematic diagram showing a relationship structure of a ring oscillator inside an analog-to-digital converter according to an embodiment of the present invention;
Fig. 4 is a timing diagram of an asynchronous clock-triggered analog-to-digital converter in a conventional structure.
Detailed Description
The present invention is described in further detail below with reference to the drawings to enable those skilled in the art to practice the invention by referring to the description.
It will be understood that terms, such as "having," "including," and "comprising," as used herein, do not preclude the presence or addition of one or more other elements or groups thereof.
It should be noted that, in the description of the present invention, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "disposed" are to be construed broadly, and may be fixedly connected, disposed, or detachably connected, disposed, or integrally connected and disposed, for example. The specific meaning of the above terms in the present invention will be understood in specific cases by those of ordinary skill in the art.
As shown in FIG. 1, the circuit system for reducing sampling skew of an analog-to-digital converter provided by the embodiment of the invention comprises an analog-to-digital converter, a conversion clock signal, N paths of phase clock signals, a clock selection circuit and a clock selection circuit, wherein the conversion clock signal is sent to the analog-to-digital converter by a host computer and used for starting conversion of the analog-to-digital converter, the N paths of phase clock signals are arranged in the analog-to-digital converter, the periods of the N paths of phase clock signals are identical and are t clk, the phase difference between two adjacent paths of clock signals is t clk/N, N > =2, the clock selection circuit is connected with the conversion clock signal and the N paths of phase clock signals, and after the analog-to-digital converter receives the conversion clock signal, the clock selection circuit selects one path of clock signal with the nearest rising edge from the N paths of phase clock signals as a sampling edge of the analog-to-digital converter and samples an input signal. The conversion clock signal is a low-frequency clock signal, and the N-path phase clock signal is a high-frequency clock signal.
In the above embodiment, N phase clock signals are provided in the analog-to-digital converter, and periods of the N phase clock signals are the same and are both t clk, and a phase difference between two adjacent clock signals is t clk/N, so, when the analog-to-digital converter receives the converted clock signal, the clock selection circuit selects, from the N phase clock signals, a clock signal having a rising edge closest to a rising edge of the converted clock signal as a sampling edge of the analog-to-digital converter. Since only one high-frequency clock signal is provided in the analog-to-digital converter, the deviation between the converted clock signal and the high-frequency clock signal, i.e., the variation range of the skew t skew, is between 0 and 1 period (t clk) of the high-frequency clock, as shown in fig. 4, when a plurality of phase clock signals are provided, compared with the conventional structure, the maximum clock skew is reduced to 1/N, and the influence of clock jitter on the signal-to-noise ratio of the analog-to-digital converter is significantly reduced. The value of N is not particularly limited, and if the value of N is 3, the maximum clock skew is reduced to one third of the original clock skew, if the value of N is 4, the maximum clock skew is reduced to one fourth of the original clock skew, and if the value of N is 8, the maximum clock skew is reduced to one eighth of the original clock skew.
In one embodiment, the circuitry for reducing sampling skew of the analog-to-digital converter, the clock selection circuit specifically includes:
The switching clock signals are connected with the data pin D and the RN reset pin of each first-stage D trigger, and the N paths of phase clock signals are sequentially connected with the N first-stage D triggers in a one-to-one correspondence manner;
The output ends of the N first-stage D triggers are sequentially connected with the N AND gates in a one-to-one correspondence manner, and the output end of the other first-stage D trigger adjacent to each first-stage D trigger is connected to the AND gate corresponding to the first-stage D trigger after being subjected to non-processing;
the output ends of the N AND gates are correspondingly connected with the N second-stage D triggers one by one;
The output end of each second-stage D trigger is connected with the enabling signal input end of a tri-state gate, wherein phase clock signals corresponding to the tri-state gate, the second-stage D trigger, the AND gate and the first-stage D trigger are also connected to the tri-state gate;
the phase clock signal which enables the tri-state gate enabling signal to be 1 level is sent to the CLK_SEL pin as an output clock, the data pins D of the N second-stage D flip-flops are all grounded, and the tri-state gate is a unidirectional tri-state gate.
In the above embodiment, the clock selection circuit adopts a two-stage D flip-flop, and an and gate and a tri-state gate, and the whole circuit has a simple structure and is practical.
The connection structure and operation of the clock selection circuit are described below by way of a specific embodiment.
If the 4-way phase clock signal is set, that is, the N value takes 4, the multiphase clock of the ring oscillator of the analog-to-digital converter can be used, as shown in fig. 3, if the multiphase clock of the ring oscillator of the analog-to-digital converter cannot be used, the required multiphase clock can be set on the chip of the analog-to-digital converter.
As shown in fig. 1, the specific connection relationship of the clock selection circuit is:
the conversion clock signal CLK_CNV is respectively connected to the RN reset pins of the 4 first-stage D flip-flops, the data pins D of the 4 first-stage D flip-flops and the RN reset pins of the 4 second-stage D flip-flops;
The first phase clock signal CK0 is connected with a first-stage D trigger and a first three-state gate T0, the second phase clock signal CK1 is connected with a second first-stage D trigger and a second three-state gate T1, the third phase clock signal CK2 is connected with a third first-stage D trigger and a third three-state gate T2, and the fourth phase clock signal CK3 is connected with a fourth first-stage D trigger and a fourth three-state gate T3;
the output end signal Q0 of the first-stage D trigger is connected with a second AND gate, is connected with the first AND gate after being subjected to non-processing, the output end signal Q1 of the second first-stage D trigger is connected with a third AND gate after being subjected to non-processing, the output end signal Q2 of the third first-stage D trigger is connected with a fourth AND gate, is connected with the third AND gate after being subjected to non-processing, and the output end signal Q3 of the fourth first-stage D trigger is connected with the first AND gate and is connected with the fourth AND gate after being subjected to non-processing;
The output end signal P0 of the first AND gate is connected with a fourth second-stage D trigger, the output end signal P1 of the second AND gate is connected with the first second-stage D trigger, the output end signal P2 of the third AND gate is connected with the second-stage D trigger, and the output end signal P3 of the fourth AND gate is connected with the third second-stage D trigger;
The output end signal S0 of the first second-stage trigger is connected with the first three-state gate phase T0, the output end signal S1 of the second-stage trigger is connected with the second three-state gate phase T1, the output end signal S2 of the third second-stage trigger is connected with the third three-state gate phase T2, and the output end signal S3 of the fourth second-stage trigger is connected with the fourth three-state gate phase T3;
four tri-state gates are connected to clk_sel.
The specific operation process is that CK0-CK3 is a 4-phase output clock of OSC inside an analog-digital converter ADC, the phase difference between adjacent clocks is t clk/4, when clk_cnv is 0 level, the output signals Q0-Q3 of 4 first stage D flip-flops are reset to 0 level, the output signals P0-P3 of four and gates are also 0 level, the output signals S0-S3 of 4 second stage D flip-flops are reset to 0 level, when clk_cnv becomes high level, the rising edge of CK2 nearest to the rising edge of clk_cnv triggers the third first stage D flip-flop connected to CK2 to make Q2 become 1 level, and then makes the output signal P3 of the fourth and gate generate a high level, and then makes the enable signal S2 become 1 level, so that CK2 is selected as the output clock to be sent to the clk_sel pin, the first rising edge of clk_sel is between 0 and clk of rising edge of clk_cnv, and the clock skew of clk_cnv is greatly reduced compared with the conventional ADC, and the clock skew of clk_cnv is greatly reduced in the analog-digital to 1/noise ratio.
The number of equipment and the scale of processing described herein are intended to simplify the description of the present invention. Applications, modifications and variations of the present invention will be readily apparent to those skilled in the art.
Although embodiments of the present invention have been disclosed above, it is not limited to the details and embodiments shown and described, it is well suited to various fields of use for which the invention would be readily apparent to those skilled in the art, and accordingly, the invention is not limited to the specific details and illustrations shown and described herein, without departing from the general concepts defined in the claims and their equivalents.
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| CN108429549A (en) * | 2017-02-15 | 2018-08-21 | 华为技术有限公司 | Homologous timing adaptive method, device and chip |
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| DE10215087B4 (en) * | 2002-04-05 | 2004-08-19 | Infineon Technologies Ag | Method and device for phase detection |
| EP3190758B1 (en) * | 2003-12-17 | 2023-06-07 | Rambus Inc. | High speed signaling system with adaptive transmit pre-emphasis, reflection cancellation and offset cancellation |
| US7701374B2 (en) * | 2008-02-26 | 2010-04-20 | Conexant Systems, Inc. | Method and apparatus for automatic optimal sampling phase detection |
| US8836553B2 (en) * | 2012-10-16 | 2014-09-16 | Broadcom Corporation | DSP reciever with high speed low BER ADC |
| DE102013101933A1 (en) * | 2013-02-27 | 2014-08-28 | Technische Universität Dresden | Method and arrangement for generating a clock signal by means of a phase locked loop |
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