CN118508955A

CN118508955A - Delay calibration circuit for time-to-digital converter

Info

Publication number: CN118508955A
Application number: CN202410531835.3A
Authority: CN
Inventors: 王思凡; 潘少辉; 冯海刚; 胡胜发
Original assignee: Guangzhou Ankai Microelectronics Co ltd; Shenzhen International Graduate School of Tsinghua University
Current assignee: Guangzhou Ankai Microelectronics Co ltd; Shenzhen International Graduate School of Tsinghua University
Priority date: 2024-04-29
Filing date: 2024-04-29
Publication date: 2024-08-16

Abstract

The present application relates to a method for time delay calibration circuitry for a digitizer. The delay calibration circuit comprises a phase frequency detector, a charge pump, a filter capacitor, a bias voltage generating unit and a voltage-controlled delay chain; voltage controlled delay chain for receiving the start signal and outputting a feedback signal after time delay; the phase frequency detector is used for receiving the initial signal and the feedback signal, converting the phase difference between the initial signal and the feedback signal into a voltage pulse signal and outputting the voltage pulse signal to the charge pump; the charge pump is used for outputting a current signal with a corresponding pulse width to the filter capacitor under the control of the voltage pulse signal; the filter capacitor is used for converting the current signal into delay control voltage and applying the delay control voltage to the input end of the bias voltage generating unit; the bias voltage generating unit is used for generating bias voltage under the action of the delay control voltage and controlling the delay time of the voltage-controlled delay chain by using the bias voltage. The delay calibration circuit is easy to implement and has high accuracy.

Description

Delay calibration circuit for time-to-digital converter

Technical Field

The present application relates to the field of time-to-digital converters, and more particularly, to a delay calibration circuit for a time-to-digital converter.

Background

A time-to-digital converter is a circuit for converting a time signal into a digital signal, which is widely used in phase-locked loop systems. The time-to-digital converter applied to the charge pump type phase-locked loop to realize the quick locking function generally has a certain requirement on the working range, the working range of the time-to-digital converter generally needs to cover one reference period of the phase-locked loop system, and the delay chain type time-to-digital converter structure is more one type of time-to-digital converter currently.

However, the switched capacitor array and the digital calibration algorithm are currently adopted to calibrate the delay gain of the delay chain type time-to-digital converter, however, the circuit with the structure needs complex digital logic circuit to assist calibration, and the calibration precision is low and is not easy to realize.

Disclosure of Invention

In view of the foregoing, it is desirable to provide a delay calibration circuit for a time-to-digital converter that is easy to implement and highly accurate.

The application provides a delay calibration circuit. The delay calibration circuit is used for rapidly locking a phase-locked loop and comprises a phase frequency detector, a charge pump, a filter capacitor, a bias voltage generating unit and a voltage-controlled delay chain; the voltage-controlled delay chain is used for receiving the initial signal and outputting a delayed feedback signal; wherein the voltage-controlled delay chain and the sampling circuit together form a target time-to-digital converter for quantizing the time interval between the start signal and the end signal into a digital signal; the phase frequency detector is used for receiving the initial signal and the feedback signal, converting the phase difference between the initial signal and the feedback signal into a voltage pulse signal and outputting the voltage pulse signal to the charge pump; the charge pump is used for outputting a current signal with corresponding pulse width to the filter capacitor under the control of the voltage pulse signal; the filter capacitor is used for converting the current signal into a delay control voltage and applying the delay control voltage to the input end of the bias voltage generating unit; the bias voltage generating unit is used for generating bias voltage under the action of the delay control voltage and controlling the delay time of the voltage-controlled delay chain by using the bias voltage.

In one embodiment, the phase frequency detector comprises a first trigger, a second trigger and a third trigger; the phase frequency detector also receives an externally input enabling signal; under the action of the start signal, the feedback signal and the enable signal, the first trigger and the second trigger output the voltage pulse signal, and the third trigger is used for blocking the start signal in the initial stage; wherein the initial stage is a stage before the rising edge of the feedback signal first arrives.

In one embodiment, when the enable signal transitions from low to high and the feedback signal is low, the third flip-flop outputs low before the rising edge of the feedback signal first arrives, so that the first flip-flop is in a reset state to block the start signal in the initial stage; when the rising edge of the feedback signal comes for the first time, the third trigger outputs a high level, so that the first trigger is changed from a reset state to a sampling state; and the second trigger changes from the sampling state to the triggering state and outputs the voltage pulse signal; when the rising edge of the initial signal arrives in the non-initial stage, the first trigger is changed from a sampling state to a triggering state; and the first trigger outputs the voltage pulse signal.

In one embodiment, after the first and second flip-flops output the voltage pulse signal, the first and second flip-flops change from the triggered state to the reset state.

In one embodiment, the phase frequency detector further comprises a first inverter, a second inverter, a third inverter, a first and gate, a first or gate, a second or gate, and a buffer; the input end of the third inverter inputs the enabling signal, and the output end of the third inverter is connected with the reset end of the third trigger and the input end of the second OR gate; the clock end of the third trigger inputs the feedback signal, and the output end of the third trigger is connected with the input end of the second inverter; the output end of the second inverter is connected with the input end of the first OR gate; the input end of the first OR gate is also connected with the input end of the second OR gate, and the output end of the first OR gate is connected with the reset end of the first trigger; the clock end of the first trigger inputs the initial signal, and the output end of the first trigger is connected with the first inverter so as to output the voltage pulse signal through the output end of the first inverter; the input end of the first AND gate is connected with the output end of the first inverter and the output end of the second trigger, and the output end of the first AND gate is connected with the input ends of the first OR gate and the second OR gate; the output end of the second OR gate is connected with the reset end of the second trigger; the clock end of the second trigger inputs the feedback signal, and the output end of the second trigger is also connected with the buffer so as to output the voltage pulse signal through the output end of the buffer.

In one embodiment, the first, second and third flip-flops are D flip-flops.

In one embodiment, the voltage controlled delay chain includes a plurality of cascaded delay cells; the output end of the bias voltage generating unit is connected with each delay unit; the bias voltage generating unit is used for adjusting the current of each delay unit by using the bias voltage so as to control the delay time of the voltage-controlled delay chain.

In one embodiment, the bias voltage generating unit includes a precharge tube; the precharge tube is used for adjusting the control voltage of the input end of the bias voltage generating unit to be the power supply voltage so as to enable the delay time of each delay unit to be the minimum value under the condition that the externally input enabling signal is low level and the delay calibration circuit is in an open loop state.

In one embodiment, the precharge tube is specifically configured to charge the filter capacitor under the effect of the enable signal when the delay calibration circuit is not in an operating state, so as to adjust the voltage at the input terminal of the bias voltage generating unit to be the power supply voltage.

In one embodiment, the bias voltage generating unit further includes a plurality of switching transistors; the input end of each switch tube is connected with the enabling signal; and each switching tube is used for controlling the bias voltage generating unit to stop working when the enabling signal is at a low level.

In one embodiment, the bias voltage generating unit further comprises a control tube and a current mirror circuit; the control tube is connected with the current mirror circuit; the control tube is used for controlling the current mirror circuit to output the bias voltage to the delay unit according to the voltage of the input end of the bias voltage generating unit.

In one embodiment, the precharge tube, each switching tube, and the control tube are transistors; the switching tube comprises a first switching tube, a second switching tube and a third switching tube; the grid electrode of the pre-charging tube is connected with the enabling signal, the grid electrode of the pre-charging tube is connected with the power supply voltage, and the drain electrode of the pre-charging tube is connected with the input end of the bias voltage generating unit; the grid electrode of the control tube is connected with the input end of the bias voltage generating unit, the drain electrode of the control tube is connected with the current mirror circuit, and the source electrode of the control tube is connected with the drain electrode of the first switching tube; the drains of the second switching tube and the third switching tube are connected with the current mirror circuit; the grid electrodes of the first switching tube, the second switching tube and the third switching tube are all connected with the enabling signal, and the source electrodes are all grounded; the current mirror circuit is also connected to each delay cell.

In one embodiment, each delay cell is a current starvation circuit structure.

In the delay calibration circuit for the time-to-digital converter, the delay calibration circuit is used for rapidly locking a phase-locked loop, and comprises a phase frequency detector, a charge pump, a filter capacitor, a bias voltage generating unit and a voltage-controlled delay chain; the voltage-controlled delay chain is used for receiving the initial signal and outputting a delayed feedback signal; the voltage-controlled delay chain and the sampling circuit together form a target time digital converter for quantizing the time interval between the starting signal and the ending signal into a digital signal; the phase frequency detector is used for receiving the initial signal and the feedback signal, converting the phase difference between the initial signal and the feedback signal into a voltage pulse signal and outputting the voltage pulse signal to the charge pump; the charge pump is used for outputting a current signal with a corresponding pulse width to the filter capacitor under the control of the voltage pulse signal; the filter capacitor is used for converting the current signal into a delay control voltage and applying the delay control voltage to the input end of the bias voltage generating unit; the bias voltage generating unit is used for generating bias voltage under the action of the delay control voltage and controlling the delay time of the voltage-controlled delay chain by using the bias voltage. The delay calibration circuit utilizes a voltage-controlled delay chain in the target time-to-digital converter, so that the real-time delay calibration of the time-to-digital converter is realized by adopting an analog delay locking loop, complex digital calibration logic is not needed, the implementation is convenient, the calibration precision of the analog circuit is higher, the quantization error of the time-to-digital converter is smaller, and the high precision is realized.

Drawings

In order to more clearly illustrate the embodiments of the application or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of a delay calibration circuit in one embodiment;

FIG. 2 is a schematic diagram of an RF PLL system in one embodiment;

fig. 3 is a schematic structural diagram of a phase frequency detector in one embodiment;

FIG. 4 is a schematic diagram of another delay calibration circuit in one embodiment;

FIG. 5 is a schematic diagram of a delay unit in one embodiment;

FIG. 6 is a schematic diagram of a bias voltage generating unit according to an embodiment;

FIG. 7 is a diagram illustrating a convergence result of the output voltage VC of the charge pump according to one embodiment;

FIG. 8 is a diagram illustrating a convergence result of the quantized output of the time-to-digital converter according to one embodiment;

FIG. 9 is a diagram of simulation results of the resolution of the time-to-digital converter before and after calibration in one embodiment.

Detailed Description

In order that the above objects, features and advantages of the application will be readily understood, a more particular description of the application will be rendered by reference to the appended drawings. It will be understood that numerous specific details are set forth in the following description in order to provide a thorough understanding of the present application, but that the present application may be practiced in many other ways other than those described herein, and that persons skilled in the art will be able to make similar modifications without departing from the spirit of the present application, so that the present application is not limited to the specific embodiments disclosed below.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

It will be understood that the terms first, second, etc. as used herein may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another element. For example, a first resistance may be referred to as a second resistance, and similarly, a second resistance may be referred to as a first resistance, without departing from the scope of the application. Both the first resistor and the second resistor are resistors, but they are not the same resistor.

It is to be understood that in the following embodiments, "connected" is understood to mean "electrically connected", "communicatively connected", etc., if the connected circuits, modules, units, etc., have electrical or data transfer between them.

It is understood that "at least one" means one or more and "a plurality" means two or more. "at least part of an element" means part or all of the element.

As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," and/or the like, specify the presence of stated features, integers, steps, operations, elements, components, or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof. Also, the term "and/or" as used in this specification includes any and all combinations of the associated listed items.

The time-to-digital converter is a circuit for converting a time signal into a digital signal, and can perform a function of quantifying a phase difference between a reference signal and a feedback signal, so that the time-to-digital converter is widely used in a phase-locked loop system. In a charge pump type phase-locked loop system, the time-to-digital converter and the auxiliary charge pump can form a fast locking path on the basis of a traditional loop, so that the establishment process of the whole loop is accelerated.

The time-to-digital converter applied to the charge pump type phase-locked loop for realizing the quick locking function generally has low requirements on resolution accuracy, but has certain requirements on a working range, and generally needs to cover one reference period of the phase-locked loop system, so that a counter type time-to-digital converter structure or a delay chain type time-to-digital converter structure is adopted more. The counter type time-digital converter has simple structure working principle, but requires additional high-frequency clock signals for counting, thereby increasing the complexity of design and limiting the use occasions; the delay chain type time-to-digital converter has a simple structure and is easy to realize, but has poor linearity and is easily influenced by deviations of temperature, power supply voltage, process angle and the like. The delay gain of the delay chain type time-to-digital converter is calibrated by adopting a switched capacitor array and a digital calibration algorithm at present, however, the circuit with the structure needs complex digital logic circuit to assist in calibration, the calibration precision is low and is not easy to realize, and in addition, the calibration precision and the calibration range are limited by the scale of a minimum capacitor unit and a capacitor array.

In view of this, the embodiments of the present application provide a delay calibration circuit for a time-to-digital converter based on a delay locked loop (Delay Locked Loop, DLL) for a fast lock application scenario in a phase locked loop system, which improves the linearity of the delay chain type time-to-digital converter circuit, and is easy to implement and high in accuracy.

In one embodiment, as shown in fig. 1, a schematic diagram of a delay calibration circuit according to an embodiment of the present application is shown. The delay calibration circuit is implemented by a delay locked loop, which is used in a fast lock phase locked loop. Specifically, the delay calibration circuit 100 includes a phase frequency detector 101, a charge pump 102, a filter capacitor C1, a bias voltage generating unit 103, and a voltage controlled delay chain 104.

The voltage-controlled delay chain 104 is configured to receive the start signal and output a delayed feedback signal; wherein the voltage controlled delay chain 104 further cooperates with the sampling circuit to form a target time-to-digital converter for quantizing a time interval between the start signal and the end signal to a digital signal; the phase frequency detector 101 is configured to receive the start signal and the feedback signal, convert a phase difference between the start signal and the feedback signal into a voltage pulse signal, and output the voltage pulse signal to the charge pump 102; the charge pump 102 is configured to output a current signal with a corresponding pulse width to the filter capacitor C1 under control of the voltage pulse signal; the filter capacitor C1 is configured to convert the current signal into a delay control voltage, and apply the delay control voltage to the input terminal of the bias voltage generating unit 103; the bias voltage generating unit 103 is configured to generate a bias voltage under the delay control voltage, and control the delay time of the voltage-controlled delay chain 104 using the bias voltage.

The delay calibration circuit 100 can be used in a target time-to-digital converter, and the voltage-controlled delay chain 104 used to construct the delay calibration circuit 100 is also multiplexed in the target time-to-digital converter. Optionally, the target time digitizer is a delay chain type time digitizer. Further, the target time-to-digital converter with delay calibration circuit 100 can be applied to a radio frequency phase-locked loop system, and an exemplary schematic diagram of a radio frequency phase-locked loop system is shown in fig. 2, and the target time-to-digital converter with delay calibration circuit 100 provided in the embodiment of the application can be applied to the radio frequency phase-locked loop system shown in fig. 2, and cooperates with an auxiliary charge pump 102 in the radio frequency phase-locked loop system to achieve the function of accelerating loop locking.

The delay calibration circuit 100 provided by the embodiment of the application is realized based on a delay lock loop, and mainly comprises a phase frequency detector 101, a charge pump 102, a bias voltage generating unit 103 and a voltage-controlled delay chain 104, wherein the phase frequency detector acquires a start signal and a feedback signal output by the voltage-controlled delay chain 104 for delay calibration, can realize real-time calibration of the delay range of the delay chain of the time-to-digital converter under different temperatures, power supply voltages and process angle deviations, and ensures that the dynamic range of the time-to-digital converter is within 1 reference period.

It should be noted that the radio frequency phase-locked loop system includes a phase-frequency detector connected to the buffer and the time-to-digital converter, and the embodiment of the present application also includes a phase-frequency detector, and the configuration of the phase-frequency detector 101 in the embodiment of the present application is different from that of the radio frequency phase-locked loop system. The phase frequency detector may generally output a voltage pulse signal, and the voltage pulse signal may specifically include a pull-UP signal (UP signal) and a pull-down signal (DN signal).

The voltage controlled delay chain 104 and the sampling circuit together form a target time-to-digital converter. In operation of the target time-to-digital converter, the voltage controlled delay chain 104 receives a start signal and the sampling circuit receives an end signal. Referring to fig. 2, the start signal may be a pull-up signal in a voltage pulse signal output by a phase frequency detector in a radio frequency phase locked loop system; the end signal received by the sampling circuit may be a pull-down signal in a voltage pulse signal output by a phase frequency detector in a radio frequency phase locked loop system.

Optionally, a logic circuit is further connected before the voltage-controlled delay chain 104, and a start signal and an end signal are obtained after a pull-down signal and a pull-up signal in a voltage pulse signal output by the phase frequency detector in the radio frequency phase-locked loop system are respectively subjected to digital logic operation by the logic circuit. A start signal is provided to an input port of the voltage controlled delay chain 104 and an end signal is provided to a clock port of the sampling circuit. The target time-to-digital converter may quantize a time interval between the start signal and the end signal into a digital signal, and in particular, may convert a pulse width between the start signal and the end signal into a multi-bit digital control code to output the digital signal. Optionally, the digital signal is output via a sampling circuit.

The voltage-controlled delay chain 104 delays the start signal to obtain a feedback signal, and outputs the delayed feedback signal to the phase frequency detector 101 in the delay calibration circuit 100. And the phase frequency detector 101 receives a start signal in addition to the feedback signal to generate a voltage pulse signal based thereon.

The charge pump 102 outputs a current signal with a corresponding pulse width to the filter capacitor C1 under the control of the voltage pulse signal, and controls the filter capacitor C1 to charge and discharge, and then the filter capacitor C1 converts the current signal into a delay control voltage and applies the delay control voltage to the input terminal of the bias voltage generating unit 103. Illustratively, the charge pump 102 charges a capacitor when the phase frequency detector 101 in the delay calibration circuit 100 outputs a pull-up signal, and the capacitor discharges when the phase frequency detector 101 in the delay calibration circuit 100 outputs a pull-down signal.

The bias voltage generating unit 103 is connected to the voltage-controlled delay chain 104, and optionally, the bias voltage generating unit 103 adjusts the current of the voltage-controlled delay chain 104 by using the bias voltage, so as to control the delay time of the voltage-controlled delay chain 104, thereby realizing delay calibration of the target time digitizer.

The delay calibration circuit 100 provided by the embodiment of the application comprises a phase frequency detector 101, a charge pump 102, a filter capacitor C1, a bias voltage generating unit 103 and a voltage-controlled delay chain 104; the voltage-controlled delay chain 104 is used for receiving the initial signal and outputting a delayed feedback signal; wherein the voltage controlled delay chain 104 further cooperates with the sampling circuit to form a target time-to-digital converter for quantizing a time interval between the start signal and the end signal to a digital signal; a phase frequency detector 101 for receiving the start signal and the feedback signal, converting a phase difference between the start signal and the feedback signal into a voltage pulse signal, and outputting the voltage pulse signal to the charge pump 102; the charge pump 102 is configured to output a current signal with a corresponding pulse width to the filter capacitor C1 under control of the voltage pulse signal; a filter capacitor C1 for converting the current signal into a delay control voltage and applying the delay control voltage to an input terminal of the bias voltage generating unit 103; the bias voltage generating unit 103 is configured to generate a bias voltage under the delay control voltage, and control the delay time of the voltage-controlled delay chain 104 by using the bias voltage. The delay calibration circuit 100 utilizes the voltage-controlled delay chain 104 in the target time-to-digital converter, thereby realizing the real-time delay calibration of the time-to-digital converter by adopting an analog delay locked loop, and the delay calibration circuit does not need complex digital calibration logic, is convenient to realize, has higher calibration precision of the analog circuit, smaller quantization error of the time-to-digital converter and high precision.

The phase frequency detector with the traditional edge triggering structure consists of two D triggers and a reset delay path, and a phase lead signal and a phase lag signal with certain pulse width are generated through rising edge triggering of a starting signal and a feedback signal; in the delay calibration application, as the input of the delay locked loop phase frequency detector is a reference signal A which is not delayed and a feedback signal A which is delayed respectively, when the rising edge of an initial reference signal is not blocked, the phase frequency detector can generate an advance signal according to the phase relation of A and A to control the delay time of a delay chain to be shortened, and the zero frequency locking problem occurs; the embodiment of the application provides a reference blocking phase frequency detector, which is newly added with a D trigger for blocking an initial starting signal and digital logic for generating a reset signal on the basis of a traditional edge triggering structure, so that false triggering of the initial starting signal can be avoided, and the zero frequency locking problem caused by false triggering of the initial starting signal is solved.

The structure of the phase frequency detector 101 in the delay calibration circuit 100 is exemplarily described below.

In one embodiment, the phase frequency detector 101 includes a first flip-flop, a second flip-flop, and a third flip-flop; the phase frequency detector 101 also receives an externally input enable signal; under the action of the starting signal, the feedback signal and the enabling signal, the first trigger and the second trigger output voltage pulse signals, and the third trigger is used for blocking the starting signal of the initial stage; the initial stage is a stage before the rising edge of the feedback signal first arrives.

When the enabling signal jumps from low level to high level and the feedback signal is low level, the third trigger outputs low level before the rising edge of the feedback signal arrives for the first time, so that the first trigger is in a reset state to block the initial signal of the initial stage; when the rising edge of the feedback signal comes for the first time, the third trigger outputs a high level, so that the first trigger is changed from a reset state to a sampling state; and the second trigger changes from the sampling state to the triggering state and outputs a voltage pulse signal; when the rising edge of the initial signal of the non-initial stage arrives, the first trigger is changed from the sampling state to the triggering state; and the first flip-flop outputs the voltage pulse signal.

The structure of the traditional edge triggered phase frequency detector 101 mainly comprises two D triggers and a reset delay link, and can realize phase detection function within the range of-2 pi to 2 pi; if the structure is directly used in the delay locked loop, zero frequency locking may occur, so that the phase frequency detector 101 does not lock the delayed rising edge a-with the next rising edge a+1 without delay, but tries to lock the delayed rising edge a-with the rising edge a without delay. This zero frequency lock is similar to the periodic slip phenomenon that often occurs in phase locked loop systems, and locks onto either the wrong rising or falling edge. The phase-locked loop system finally realizes the locking of frequency and phase, and the cycle slip phenomenon does not influence the final locking result, but only prolongs the locking time; however, in the delay locked loop, if the zero frequency locking phenomenon occurs, the phase frequency detector 101 will always generate a phase advance signal, so as to force the delay chain to continuously shorten the delay time, and further make the delay of the delay chain always keep the minimum value, which seriously affects the actual circuit function.

The phase frequency detector 101 in the embodiment of the application can block the initial signal in the initial stage, and avoid the problem of zero frequency locking caused by false triggering of the initial signal in the initial stage.

And when the rising edge of the feedback signal comes for the first time in the following period, the third trigger outputs a high level, so that the first trigger is changed from a reset state to a sampling state; and the second trigger changes from the sampling state to the triggering state and outputs a voltage pulse signal; when the rising edge of the initial signal of the non-initial stage arrives, the first trigger is changed from the sampling state to the triggering state; and, the first flip-flop outputs the voltage pulse signal, so the start signal is not blocked any more in the subsequent stage.

In one embodiment, after the first and second flip-flops output the voltage pulse signals, the first and second flip-flops change from a triggered state to a reset state so that the loop is accurately delay calibrated next time.

In one embodiment, a schematic structural diagram of a phase frequency detector according to an embodiment of the present application is shown in fig. 3. The phase frequency detector 101 includes, in addition to the first flip-flop DFF1, the second flip-flop DFF2, AND the third flip-flop DFF3, a first inverter INV1, a second inverter INV2, a third inverter INV3, a first AND gate AND1, a first OR gate OR1, a second OR gate OR2, AND a buffer BUF1. The input end of the third inverter inputs an enabling signal, and the output end of the third inverter is connected with the reset end of the third trigger and the input end of the second OR gate; the clock end of the third trigger inputs a feedback signal, and the output end of the third trigger is connected with the input end of the second inverter; the output end of the second inverter is connected with the input end of the first OR gate; the input end of the first OR gate is also connected with the input end of the second OR gate, and the output end of the first OR gate is connected with the reset end of the first trigger; the clock end of the first trigger inputs an initial signal, and the output end of the first trigger is connected with the first inverter so as to output a voltage pulse signal through the output end of the first inverter; the input end of the first AND gate is connected with the output end of the first inverter and the output end of the second trigger, and the output end of the first AND gate is connected with the input ends of the first OR gate and the second OR gate; the output end of the second OR gate is connected with the reset end of the second trigger; the clock end of the second trigger inputs a feedback signal, and the output end of the second trigger is also connected with the buffer so as to output a voltage pulse signal through the output end of the buffer.

That is, for the phase frequency detector 101, it mainly includes three D flip-flops DFF1, DFF2, DFF3 and a simple combination digital logic circuit, wherein DFF1 and DFF2 are used to generate a pull-UP signal UP and a pull-down signal DN, respectively, and DFF3 is used to block an initial start signal. The DFF1 clock end is connected with an initial signal, the reset end is connected with the output end of the OR gate OR1, AND the output end Q is connected with the input end of the inverter INV1 AND the input end of the AND gate AND 1; the DFF2 clock end is connected with a feedback signal, the reset end is connected with the output end of the OR gate OR2, AND the output end Q is connected with the input end of the buffer BUF1 AND the input end of the AND gate AND 1; the DFF3 clock is connected with the feedback signal, the reset is connected with the output end of the inverter INV3, and the output end Q is connected with the input end of the inverter INV 2. The output end of the INV1 outputs a pull-UP signal UP, and the output end of the BUF1 outputs a pull-down signal DN; the AND1 output is connected to the OR1 AND OR2 inputs. The INV2 output end is connected with the OR1 input end, and the INV3 output end is connected with the DFF3 reset end and the OR2 input end. The PFDEN signal is an enable signal of the phase frequency detector 101, when PFDEN is at a low level, the phase frequency detector 101 is closed, and at the moment, the reset ends of the three D flip-flops are all at a high level; when PFDEN is at high level, DFF2 and DFF3 enter the trigger state first, when the rising edge of the feedback signal arrives, DFF3 outputs high level, DFF1 enters the trigger state, and phase frequency detector 101 starts to identify the phase difference. When both the DFF1 AND the DFF2 are triggered, the AND1 generates a high level AND respectively controls the DFF1 AND the DFF2 to reset after passing through the OR1 AND the OR2, AND the D trigger reenters the triggering state AND waits for triggering.

It will be appreciated that the phase frequency detector 101 may be other structures that perform the above functions and are not fully illustrated herein.

Optionally, the first trigger, the second trigger and the third trigger are all D triggers.

Alternatively, as described above, the voltage pulse signal output by the phase frequency detector 101 includes an UP signal and a DN signal, where the voltage pulse signal output by the first flip-flop may be the DN signal, and the voltage pulse signal output by the second flip-flop may be the DN signal.

Taking an example of a feedback signal leading the start signal, the reference blocking phase frequency detector 101 provided in the embodiment of the present application functions as follows: when the enable signal PFDEN is at a low level, the D flip-flops DFF1, DFF2, DFF3 are all in a reset state, and the output terminal Q remains at a low level; when the enable signal PFDEN transitions to a high level, the phase frequency detector 101 enters an operating state, the output Q of the DFF3 remains low level until the feedback signal fFB arrives, and the output Q is maintained high level through the inverter INV2 and the OR gate OR1, so that the DFF1 is still in a reset state, and the DFF1 cannot be triggered when the rising edge of the start signal fREF arrives, so that the initial start signal is blocked.

Specifically, when the rising edge of the feedback signal fFB arrives, the DFF2 triggers and outputs a high level, the pull-down signal DN is generated after the feedback signal passes through the buffer BUF1, the DFF3 also triggers and outputs a high level, the feedback signal passes through the INV2 and the OR1 and generates a low level, the DFF1 is not in a reset state, and the feedback signal is triggered after the rising edge of the initial signal fREF arrives; when the rising edge of the second starting signal arrives, the DFF1 triggers AND outputs a high level, AND a pull-UP signal UP is generated after the DFF1 passes through the inverter INV1, AND at the moment, both input ends of the AND1 are high level, so that the DFF1 AND the DFF2 are reset by outputting the high level signal, AND one round of frequency discrimination AND phase discrimination operation is completed. Since DFF3 is not reset by the high level of the AND1 output, the subsequent process DFF2 output continues to be high AND the start signal is not blocked any more.

In one embodiment, please refer to fig. 4, which illustrates a schematic diagram of another delay calibration circuit according to an embodiment of the present application. Wherein the voltage controlled delay chain 104 comprises a plurality of cascaded delay units 1041; the output end of the bias voltage generating unit 103 is connected with each delay unit 1041; the bias voltage generating unit 103 is configured to adjust the current of each delay unit 1041 by using the bias voltage to control the delay time of the voltage-controlled delay chain 104. Alternatively, as shown in fig. 4, the sampling circuit in the target time-to-digital converter is composed of a plurality of cascaded D flip-flops.

Optionally, the sampling circuit outputs the quantized digital signal as a 9-bit digital signal Q <8:0>.

In one embodiment, each delay unit 1041 is a current starved circuit structure.

Exemplary, fig. 5 shows a schematic structural diagram of a delay unit according to an embodiment of the present application. Here, the delay unit 1041 is constituted by MOS transistors of M11 to M16. The source of M11 may be connected to the power voltage VDD, the source of M16 may be grounded, and VCP and VCN are both connected to the bias voltage generating unit 103, so as to be controlled by the voltage generating unit to implement current regulation. VI is the input voltage and VO is the output voltage.

Here, the delay unit 1041 current is adjusted by controlling the gate terminal voltage VCP of the pull-up transistor M11 and the gate terminal voltage VCN of the pull-down transistor M16, thereby precisely controlling the delay time in real time.

Referring to fig. 5, the embodiment of the application adopts the dual voltage-controlled delay unit 1041, wherein compared with the single voltage-controlled structure, the adopted dual voltage-controlled delay unit 1041 has better delay symmetry, wider regulation range and less damage to the signal waveform.

In addition to the zero frequency locking problem, when the delay time of the delay chain is too long, the delay locking loop may also have a frequency multiplication locking problem, and at this time, the phase frequency detector 101 will attempt to lock the delayed rising edge a-and the rising edge a+2 together, so as to always generate a phase lag signal, force the delay chain to continuously prolong the delay time, and further make the delay chain delay always keep at a maximum value.

In the related art, the voltage-to-current unit mostly adopts a conventional current mirror structure to generate bias voltage to control the delay chain current, when the initial delay chain delay exceeds one period due to factors such as process deviation, temperature variation, power supply voltage fluctuation, and the like, the phase frequency detector misses the initial signal A+1, and compares the feedback signal A-with the initial signal A+2, so that the actual delay chain delay time is 2 reference periods. The bias voltage generating unit 103 provided by the embodiment of the application additionally introduces a pre-charging tube to charge the output capacitor of the charge pump 102 in advance, so that the delay chain is in a minimum delay state by outputting the bias voltage when a loop is opened, the delay time is smaller than a reference period, and the problem of frequency multiplication locking is avoided; meanwhile, a switching tube is introduced, so that large static power consumption can not be generated due to the precharge tube when the loop does not work.

The structure of the bias voltage generating unit 103 is exemplarily described below.

In one embodiment, the bias voltage generating unit 103 includes a precharge tube; and a precharge tube for adjusting the control voltage of the input terminal of the bias voltage generating unit 103 to the power supply voltage so that the delay time of each delay unit 1041 is minimized in the case where the externally inputted enable signal is low and the delay calibration circuit 100 is in an open loop state.

The precharge tube is specifically configured to charge the filter capacitor C1 under the effect of the enable signal when the delay calibration circuit 100 is not in the operating state, so as to adjust the voltage at the input terminal of the bias voltage generating unit 103 to be the power supply voltage.

In the embodiment of the present application, in order to avoid the problem of frequency multiplication locking, when the loop is not opened, that is, in the on-off state, the provided bias voltage generating unit 103 charges the filter capacitor C1 through the precharge tube, the voltage at the input end of the bias voltage generating unit 103 connected to the precharge tube is charged to the power supply voltage VDD, and accordingly, the delay unit 1041 can be in the minimum delay state, so as to ensure the flexibility of performing delay calibration by the delay calibration circuit 100.

In one embodiment, the bias voltage generating unit 103 further includes a plurality of switching transistors; the input end of each switch tube is connected with an enabling signal; each switching tube is used for controlling the bias voltage generating unit 103 to stop working when the enabling signal is at a low level.

Optionally, the enable signal connected to the input of each switching tube is the same enable signal as the external enable signal connected to the reference blocking phase detector 101.

When the enable signal is at a high level, the bias voltage generating unit 103 works normally, the enable signal jumps to a low level, the bias voltage generating unit 103 stops working, and at the moment, static power consumption overhead is avoided, and power consumption is saved.

In one embodiment, the bias voltage generating unit 103 further includes a control tube and a current mirror circuit; the control tube is connected with the current mirror circuit; and a control tube for controlling the current mirror circuit to output the bias voltage to the delay unit 1041 according to the voltage of the input terminal of the bias voltage generating unit 103.

The control tube is connected to the input terminal of the bias voltage generating unit 103, and is also connected to a current mirror circuit, which is connected to the delay unit 1041. When the input voltage changes, the control tube acts on the current mirror circuit, which correspondingly outputs a bias voltage to the delay unit 1041.

Alternatively, the current mirror circuit may be composed of a plurality of MOS transistors. As long as the function of the current mirror can be achieved, this is not entirely exemplified here.

Optionally, each switching tube, the precharge tube and the control tube may be MOS tubes.

Referring to fig. 6, a schematic diagram of a bias voltage generating unit according to an embodiment of the application is shown. Wherein, the precharge tube M1, each switch tube and the control tube M4 are transistors; the switching tube comprises a first switching tube M8, a second switching tube M9 and a third switching tube M10; the grid of the precharge tube is connected with an enable signal EN, the grid of the precharge tube is connected with a power supply voltage VDD, and the drain of the precharge tube is connected with the input end VC of the bias voltage generating unit 103; the grid electrode of the control tube is connected with the input end of the bias voltage generating unit 103, the drain electrode of the control tube is connected with the current mirror circuit, and the source electrode of the control tube is connected with the drain electrode of the first switching tube; the drains of the second switching tube and the third switching tube are connected with the current mirror circuit; the gates of the first switching tube, the second switching tube and the third switching tube are all connected with an enabling signal, and the sources of the first switching tube, the second switching tube and the third switching tube are all grounded; the current mirror circuit is also connected to each delay unit 1041. It should be noted that, for ease of understanding, fig. 6 also shows a connection relationship between the bias voltage generating unit 103 and the delay unit 1041. The current mirror circuit may be composed of transistors M2 to M7, for example.

The drain of M2 in the current mirror circuit is connected to the gate of M11 of delay unit 1041, providing bias voltage VCP. The drain of M7 in the current mirror circuit is connected to the gate of M16 in the delay unit 1041, providing the bias voltage VCN.

For the bias voltage generating unit 103, the transistors M2-M7 are used to generate bias voltages VCP and VCN, wherein the current flowing through M2 is controlled by the gate terminal voltage VC of M4. When the VC voltage decreases, the current flowing through M4 decreases, and the M2 drain voltage increases. Since M2 is diode-connected, and the gate terminal of M2 is connected to the gate terminal of M3, the current flowing through M3 will also decrease, and the voltage at the drain terminal of M3 will decrease accordingly. Thus, as the VC voltage decreases, the bias voltages VCP and VCN will increase and decrease, respectively, and accordingly, the delay time of the voltage controlled delay chain 104 will increase for the voltage controlled delay chain 104.

It should be noted that the size of the transistors M11-M16 in the delay unit 1041 needs to be properly designed to ensure that the input signal will not have waveform distortion after being delayed.

The pre-charging tube M1 can charge the capacitor C1 in advance in a state that the loop is closed, and charging the VC voltage to VDD can ensure that the delay range of the voltage-controlled delay chain 104 is at a minimum value in an initial state, so as to avoid the problem of frequency multiplication locking of the loop.

Please refer to fig. 7, which illustrates the convergence result of the charge pump output voltage VC under different processes, temperatures, power supply voltages (under different PVT); and figure 8 shows the convergence result of the quantized output of the time-to-digital converter at different PVT. The calibration process is completed within 10 reference clock cycles, and the voltage VC is stably maintained at a fixed level, so that the dynamic range of the time-to-digital converter is ensured to be 1 reference cycle. After the calibration stage is completed, the time-to-digital converter can correctly output the quantization result to the subsequent auxiliary charge pump, and the auxiliary current is controlled to further realize the effect of accelerating locking of the phase-locked loop.

In addition, fig. 9 is a simulation comparison result of the resolutions of the time-to-digital converter before and after calibration under different PVT, where S1 is a simulation result of the resolution of the time-to-digital converter under different PVT without the delay calibration circuit 100, and S2 is a simulation result of the resolution of the time-to-digital converter under different PVT with the delay calibration circuit 100. It can be seen that the delay calibration circuit 100 based on the delay locked loop provided by the embodiment of the application can significantly reduce the influence of factors such as process deviation on the resolution of the time-to-digital converter, significantly improve the robustness of the circuit, and better assist in realizing the function of accelerating the locking of the phase locked loop.

The delay calibration circuit 100 provided by the embodiment of the application can calibrate the delay range of the voltage-controlled delay chain 104 in real time, and ensure that the working range of the time-to-digital converter is always maintained in a reference period of a phase-locked loop system, thereby reducing the influence of factors such as process deviation, power supply voltage fluctuation, temperature change and the like on indexes such as dynamic range, resolution and the like of the time-to-digital converter, improving the robustness of the time-to-digital converter, improving the linearity of the delay chain type time-to-digital converter circuit, and realizing the real-time calibration function of the delay range of the delay chain under different temperatures, power supply voltages and process angles. The delay chain delay can be calibrated in real time, the dynamic range and the resolution of the delay chain delay can not be changed along with the fluctuation of the ambient temperature or the power supply voltage, the loop calibration speed is high, the locking can be completed within 10 reference periods, and the delay chain delay device has the characteristics of real-time delay calibration and high working speed; the phase frequency detector 101 and the bias voltage generating unit 103 in the loop can avoid the problems of zero frequency locking, frequency multiplication locking and the like of the loop, can normally realize the calibration function under different process deviations, and have higher reliability and robustness.

In one embodiment, the present application also provides a phase locked loop comprising a delay calibration circuit as described in any of the embodiments above. For other limitations of the phase locked loop, see the description above, and will not be repeated.

The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.

The foregoing examples illustrate only a few embodiments of the application and are described in detail herein without thereby limiting the scope of the application. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the application, which are all within the scope of the application. Accordingly, the scope of the application should be assessed as that of the appended claims.

Claims

1. The delay calibration circuit is characterized by being used in a fast locking phase-locked loop and comprises a phase frequency detector, a charge pump, a filter capacitor, a bias voltage generating unit and a voltage-controlled delay chain;

The voltage-controlled delay chain is used for receiving the initial signal and outputting a delayed feedback signal; wherein the voltage controlled delay chain and the sampling circuit together form a target time-to-digital converter for quantizing a time interval between the start signal and the end signal into a digital signal;

The phase frequency detector is used for receiving the initial signal and the feedback signal, converting a phase difference between the initial signal and the feedback signal into a voltage pulse signal, and outputting the voltage pulse signal to the charge pump;

the charge pump is used for outputting a current signal with a corresponding pulse width to the filter capacitor under the control of the voltage pulse signal;

the filter capacitor is used for converting the current signal into a delay control voltage and applying the delay control voltage to the input end of the bias voltage generating unit;

the bias voltage generating unit is used for generating bias voltage under the action of the delay control voltage and controlling the delay time of the voltage-controlled delay chain by using the bias voltage.

2. The delay calibration circuit of claim 1, wherein the phase frequency detector comprises a first flip-flop, a second flip-flop, and a third flip-flop; the phase frequency detector also receives an externally input enabling signal;

Under the action of the start signal, the feedback signal and the enable signal, the first trigger and the second trigger output the voltage pulse signal, and the third trigger is used for blocking the start signal in an initial stage; wherein the initial stage is a stage before a rising edge of the feedback signal first arrives.

3. The delay calibration circuit of claim 2, wherein,

When the enabling signal jumps from low level to high level and the feedback signal is low level, the third trigger outputs low level before rising edge of the feedback signal comes for the first time, so that the first trigger is in reset state to block the initial signal in initial stage;

When the rising edge of the feedback signal comes for the first time, the third trigger outputs a high level, so that the first trigger is changed from a reset state to a sampling state; and the second trigger changes from a sampling state to a triggering state and outputs the voltage pulse signal;

when the rising edge of the starting signal in the non-initial stage arrives, the first trigger is changed from a sampling state to a triggering state; and the first trigger outputs the voltage pulse signal.

4. A delay calibration circuit as recited in claim 3, wherein,

After the first and second flip-flops output the voltage pulse signal, the first and second flip-flops change from the trigger state to the reset state.

5. The delay calibration circuit of claim 2, wherein the phase frequency detector further comprises a first inverter, a second inverter, a third inverter, a first and gate, a first or gate, a second or gate, and a buffer;

The enabling signal is input to the input end of the third inverter, and the output end of the third inverter is connected with the reset end of the third trigger and the input end of the second OR gate;

the clock end of the third trigger inputs the feedback signal, and the output end of the third trigger is connected with the input end of the second inverter;

The output end of the second inverter is connected with the input end of the first OR gate;

the input end of the first OR gate is also connected with the input end of the second OR gate, and the output end of the first OR gate is connected with the reset end of the first trigger;

The clock end of the first trigger inputs the initial signal, and the output end of the first trigger is connected with the first inverter so as to output the voltage pulse signal through the output end of the first inverter;

The input end of the first AND gate is connected with the output end of the first inverter and the output end of the second trigger, and the output end of the first AND gate is connected with the input ends of the first OR gate and the second OR gate;

The output end of the second OR gate is connected with the reset end of the second trigger;

the clock end of the second trigger inputs the feedback signal, and the output end of the second trigger is also connected with the buffer so as to output the voltage pulse signal through the output end of the buffer.

6. The delay calibration circuit of claim 2, wherein the first flip-flop, the second flip-flop, and the third flip-flop are D flip-flops.

7. The delay calibration circuit of claim 1, wherein the voltage controlled delay chain comprises a plurality of cascaded delay cells; the output end of the bias voltage generating unit is connected with each delay unit;

The bias voltage generating unit is used for adjusting the current of each delay unit by using the bias voltage so as to control the delay time of the voltage-controlled delay chain.

8. The delay calibration circuit of claim 7, wherein the bias voltage generating unit comprises a precharge tube;

The precharge tube is used for adjusting the control voltage of the input end of the bias voltage generating unit to be a power supply voltage under the condition that an externally input enabling signal is low level and the delay calibration circuit is in an open loop state so as to enable the delay time of each delay unit to be the minimum value.

9. The delay calibration circuit of claim 8, wherein,

The precharge tube is specifically configured to charge the filter capacitor under the effect of the enable signal when the delay calibration circuit is not in a working state, so as to adjust the voltage at the input end of the bias voltage generating unit to be the power supply voltage.

10. The delay calibration circuit of claim 8, wherein the bias voltage generating unit further comprises a plurality of switching tubes; the input end of each switching tube is connected with the enabling signal;

And each switching tube is used for controlling the bias voltage generating unit to stop working when the enabling signal is at a low level.

11. The delay calibration circuit of claim 10, wherein the bias voltage generating unit further comprises a control tube and a current mirror circuit; the control tube is connected with the current mirror circuit;

The control tube is used for controlling the current mirror circuit to output the bias voltage to the delay unit according to the voltage of the input end of the bias voltage generating unit.

12. The delay calibration circuit of claim 11, wherein the precharge tube, each of the switching tubes, and the control tube are transistors; the switching tube comprises a first switching tube, a second switching tube and a third switching tube;

The grid electrode of the pre-charging tube is connected with the enabling signal, the grid electrode of the pre-charging tube is connected with the power supply voltage, and the drain electrode of the pre-charging tube is connected with the input end of the bias voltage generating unit;

the grid electrode of the control tube is connected with the input end of the bias voltage generating unit, the drain electrode of the control tube is connected with the current mirror circuit, and the source electrode of the control tube is connected with the drain electrode of the first switching tube;

The drains of the second switching tube and the third switching tube are connected with the current mirror circuit; the grid electrodes of the first switching tube, the second switching tube and the third switching tube are all connected with the enabling signal, and the source electrodes are all grounded;

the current mirror circuit is also connected with each delay unit.

13. The delay calibration circuit of claim 7, wherein each of the delay cells is a current starved circuit configuration.