CN118507514B - Preparation method of longitudinal beta gallium oxide NPN transistor - Google Patents

Abstract

The invention provides a preparation method of a longitudinal beta gallium oxide NPN transistor. The invention adopts a longitudinal device structure, an emitter and a base electrode are led out from the top of the device, and a collector electrode is led out from the bottom of the device; the field p-type doping layer formed by spontaneous polarization of the ferroelectric layer is adopted, so that the problem that the p-type doping of gallium oxide is difficult to realize at the present stage is avoided; the ferroelectric layer is used as a p-type doping implementation and a leading-out electrode of the base electrode in the device structure, and the leading-out electrode of the base electrode adopts a through hole process. The longitudinal beta gallium oxide NPN transistor prepared by the invention has excellent on-state performance at room temperature of 2.5V, saturation current of 8A/mm, on-resistance of 134.2 omega mm and three-terminal breakdown voltage of 985V.

Description

A method for preparing a vertical β-gallium oxide NPN transistor

Technical Field

The invention relates to the technical field of wide bandgap longitudinal power devices, in particular to a method for preparing a longitudinal beta gallium oxide NPN transistor.

Background Art

As the bottleneck of semiconductor silicon, a traditional material, becomes increasingly prominent, wide bandgap semiconductors are beginning to gain attention and are gradually being applied to high-power fields. Gallium oxide, as one of the representatives of ultra-wide bandgap semiconductors, has a very high critical breakdown field strength and is the preferred material for the next generation of ultra-high power, extreme environment-resistant (high voltage, high temperature, strong radiation, etc.) power electronic devices after gallium nitride and silicon carbide. Compared with silicon-based devices, the use of gallium oxide power devices will bring advantages such as energy saving, smaller size, lighter weight, and faster speed, which can enhance energy conservation and emission reduction and accelerate the promotion of green and sustainable development.

Chinese Patent CN103594358A: discloses a method for manufacturing an NPN transistor, which comprises preparing an N-type substrate; forming a P-type epitaxial layer on the substrate; forming an insulating medium on the epitaxial layer, and forming an opening on the insulating medium in at least a region forming an emitter region or a collector region; after cleaning the surface of the epitaxial layer, applying an aqueous solution containing tungsten diffused in the epitaxial layer to the surface of the semiconductor layer, so that the surface of the epitaxial layer exposed from the opening is hydrophilic; applying a liquid source containing impurities forming the emitter region or the collector region to the epitaxial layer, so that the tungsten and the impurities are thermally diffused into the epitaxial layer.

Chinese patent CN101866856A: A method for manufacturing an NPN transistor is proposed. The NPN transistor includes: a semiconductor substrate; an N-type buried layer region located in the semiconductor substrate; a collector located in the N-buried layer region; a base located on the N-buried layer region and the collector; a second oxide layer located on the surface of the base, wherein the second oxide layer has a contact hole that penetrates the thickness thereof; an emitter that fills the contact hole and covers the surface of the second oxide layer around the contact hole; a shallowly doped metal contact located in the base on both sides of the emitter; sidewalls located on both sides of the emitter and the second oxide layer; and a deep doped region located in the base on both sides of the emitter and the sidewalls, wherein the deep doped region is deeper in the base than the shallowly doped region.

Chinese patent CN109244179A: relates to a method for preparing a photoelectric NPN transistor based on a diamond/SiC heterostructure, the preparation method comprising: growing a homoepitaxial material on the upper surface of a SiC substrate to form a collector region; growing a heteroepitaxial material on the upper surface of the collector region and etching to form a base region; growing a diamond material on the upper surface of the base region and etching to form an emitter region; growing a first metal material on the upper surface of the collector region to form a collector electrode; and growing a second metal material on the upper surface of the emitter region to form an emitter electrode.

The β-gallium oxide substrate manufacturing technology of the above patent and the prior art is relatively mature, and n-type doping is uniformly achieved, but its p-type doping is difficult to achieve, and it is difficult to realize when preparing a device structure containing a pn junction.

Summary of the invention

In order to solve at least one technical problem in the above background technology, the present invention provides a method for preparing a vertical β-gallium oxide NPN transistor, wherein the vertical structure includes: from bottom to top, a collector, an n+ substrate β-gallium oxide, an n-epitaxial β-gallium oxide, a ferroelectric layer, an n+ doped β-gallium oxide, an insulating medium, a base, and an emitter, and the operation steps are as follows:

Step 1: deposit a layer of collector metal on the n+ substrate β-gallium oxide;

Step 2: depositing a layer of n-epitaxial β-gallium oxide on the n+ substrate β-gallium oxide by organic chemical vapor deposition process; the CVD materials are Si and gallium oxide single crystal, at 800-850°C and 1-1.5MPa;

Step 3: depositing a barrier layer on the n-epitaxial β-gallium oxide, etching a ferroelectric layer through hole, etching to form a ferroelectric layer area, and depositing a ferroelectric layer; etching is performed using a wet chemical solution, the solution is a mixture of sulfuric acid and hydrogen peroxide, the ratio of sulfuric acid is 1:1, the ratio of hydrogen peroxide solution is 30-35%, and the ratio of sulfuric acid to hydrogen peroxide is 1:2-3;

Step 4: remove the original barrier layer, and deposit a layer of n+ doped β-gallium oxide on the n-epitaxial β-gallium oxide by organic chemical vapor deposition process; the CVD materials are Si and gallium oxide single crystal, at 800-850°C and 1-1.5MPa;

Step 5: Deposit a layer of emitter metal on the n+ doped β-gallium oxide.

Step 6: forming a barrier layer on the emitter metal, etching an insulating dielectric through hole, etching to form an insulating dielectric region, and depositing an insulating dielectric; etching is performed using a wet chemical solution, the solution is a mixture of sulfuric acid and hydrogen peroxide, the ratio of sulfuric acid is 1:1, the ratio of hydrogen peroxide solution is 30-35%, and the ratio of sulfuric acid to hydrogen peroxide is 1:2-3;

Step 7: Remove the original barrier layer, re-form the barrier layer, etch the base metal through hole, etch to form the base metal area, and deposit the active metal. Etching is done by wet chemical solution etching, the solution is a mixture of sulfuric acid and hydrogen peroxide, the ratio of sulfuric acid is 1:1, the ratio of hydrogen peroxide solution is 30-35%, and the ratio of sulfuric acid to hydrogen peroxide is 1:2-3.

In some embodiments, the collector thickness is 1-3 μm, the n+ substrate β-gallium oxide thickness is 0.5-2 μm, the n-epitaxial β-gallium oxide thickness is 5-15 μm, the ferroelectric layer thickness is 50-150 nm, the n+ doped β-gallium oxide thickness is 0.5-2 μm, the insulating medium thickness is 4-6 nm, the emitter metal thickness is 400-600 nm, and the base thickness is 5-15 nm.

In some embodiments, the doping concentration of the n+ substrate β-gallium oxide is 1×10 ¹⁸ cm ⁻³ , the doping concentration of the n-epitaxial β-gallium oxide is 6×10 ¹⁶ cm ⁻³ , and the doping concentration of the n+ doped β-gallium oxide is 1×10 ¹⁸ cm ⁻³ .

In some embodiments, the ferroelectric layer material is one or more of Pb(Zr, Ti)O ₃ , BaTiO ₃ , (Bi, Na)TiO ₃ , and PVDF.

In some embodiments, the collector, emitter, and base are made of the same metal material, which is one of Au, Ni, Cu, or an alloy.

In some embodiments, the doping concentration of the n+ substrate β-gallium oxide and the n+ doped β-gallium oxide is to form an ohmic contact between the collector and the emitter to reduce the contact resistance; the n-epitaxial β-gallium oxide is to control the voltage-resistant region within the range of the ferroelectric layer and the n-epitaxial β-gallium oxide when the device is turned off to avoid affecting the characteristics of the highly doped β-gallium oxide.

In some embodiments, the p-type doping of the gallium oxide substrate is controlled by the field formed by the electric polarization of the ferroelectric layer, thereby avoiding the problem that the p-type doping of β-gallium oxide is difficult to achieve at present. The device structure is mainly homoepitaxial, thus avoiding the device reliability problem caused by mismatch.

In some embodiments, the ferroelectric layer is doped with p-type β-gallium oxide, and at the same time, a through-hole process is used to pass through the emitter and n+ doped β-gallium oxide to directly contact the ferroelectric layer to form a p-type doped potential lead.

In some embodiments, the insulating medium is prepared by:

A1: Weigh 3-6 parts of 7-aminobenzofuran, 7-14 parts of 1,4-diacryloylpiperazine, 2-4 parts of ethylenediamine, and 150-200 parts of butyl acrylate, stir at 50-60°C for 40-100 minutes, then add 1000-2000 parts of silica sol with a _SiO2 mass content of 20%-30%, and disperse at a high speed of 1000-2000 rpm to obtain an insulating gel;

A2: Coat the surface of the ferroelectric layer with insulating gel, then put it into a plasma surface treatment apparatus for polymerization to obtain an insulating medium.

In some embodiments, the process parameters of the plasma surface treatment instrument PlasmaAPC500 are RF power 300-350 W, treatment time 50-100 seconds, argon gas flow rate 20-40 sccm, working pressure 200-300 mTorr, and generator frequency of about 20-40 kHz.

Preparation mechanism of the insulating medium in the present invention:

7-Aminobenzofuran, 1,4-diacryloylpiperazine, and butyl acrylate undergo an amino-acryl addition reaction, and then are mixed with silica sol and subjected to plasma treatment to undergo a polymerization reaction, thereby forming an insulating medium; this helps to enhance the adhesion between the insulating medium and the ferroelectric layer, thereby improving the stability of the sensor in long-term use; and removes organic pollutants and oxide layers to provide a clean surface environment for high-quality polymerization reactions.

The present invention provides a method for preparing a vertical β-gallium oxide NPN transistor. Compared with the prior art, the present invention has the following significant effects:

1. The present invention adopts a vertical device structure, with the emitter and base being led out at the top of the device and the collector being led out at the bottom of the device;

2. The present invention adopts a field p-type doping layer formed by spontaneous polarization of the ferroelectric layer, which avoids the problem that p-type doping of gallium oxide is difficult to achieve at present;

3. The ferroelectric layer of the present invention acts as both a p-type doping implementation and a base lead electrode inside the device structure;

4. The base lead electrode of the present invention adopts a through-hole process;

5. The vertical β-gallium oxide NPN transistor prepared by the present invention has a saturation current of 8A/mm², an on-resistance of 134.2Ω.mm, and a three-terminal breakdown voltage of 985V at room temperature of 2.5V, and has excellent on-state performance.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a structural diagram of a vertical β-gallium oxide NPN transistor.

DETAILED DESCRIPTION

In order to further explain the technical means and effects adopted by the present invention to achieve the predetermined invention purpose, the specific implementation methods, structures, and features of the present invention are described in detail below in conjunction with the accompanying drawings and preferred embodiments.

Wherein embodiment test method:

1. Use AgilentB1500A semiconductor device analyzer to measure the saturation current and on-resistance of the transistor at room temperature and 2.5V;

2. The Keysight B1505A power device analyzer was used to measure the three-terminal breakdown voltage.

Example 1

A method for preparing a vertical β-gallium oxide NPN transistor, wherein the vertical structure comprises: from bottom to top, a collector, an n+ substrate β-gallium oxide, an n-epitaxial β-gallium oxide, a ferroelectric layer, an n+ doped β-gallium oxide, an insulating medium, a base, and an emitter, wherein the operation steps are as follows:

Step 1: deposit a layer of collector metal on the n+ substrate β-gallium oxide;

Step 2: depositing a layer of n-epitaxial β-gallium oxide on the n+ substrate β-gallium oxide by organic chemical vapor deposition process; the CVD materials are Si and gallium oxide single crystal, at 800°C and 1MPa;

Step 3: depositing a barrier layer on the n-epitaxial β-gallium oxide, etching a ferroelectric layer through hole, etching to form a ferroelectric layer area, and depositing a ferroelectric layer; etching is performed using a wet chemical solution, the solution is a mixture of sulfuric acid and hydrogen peroxide, the ratio of sulfuric acid is 1:1, the ratio of hydrogen peroxide solution is 30%, and the ratio of sulfuric acid to hydrogen peroxide is 1:2;

Step 4: remove the original barrier layer, and deposit a layer of n+ doped β-gallium oxide on the n-epitaxial β-gallium oxide by organic chemical vapor deposition process; the CVD materials are Si and gallium oxide single crystal, at 800°C and 1MPa;

Step 5: Depositing a layer of emitter metal on the n+ doped β-gallium oxide;

Step 6: forming a barrier layer on the emitter metal, etching an insulating dielectric through hole, etching to form an insulating dielectric region, and depositing an insulating dielectric; etching is performed using a wet chemical solution, the solution is a mixture of sulfuric acid and hydrogen peroxide, the ratio of sulfuric acid is 1:1, the ratio of hydrogen peroxide solution is 30%, and the ratio of sulfuric acid to hydrogen peroxide is 1:2;

Step 7: Remove the original barrier layer, re-form the barrier layer, etch the base metal through hole, etch to form the base metal area, and deposit the active metal. Etching is done by wet chemical solution etching, the solution is a mixture of sulfuric acid and hydrogen peroxide, the ratio of sulfuric acid is 1:1, the ratio of hydrogen peroxide solution is 30%, and the ratio of sulfuric acid and hydrogen peroxide is 1:2.

The collector thickness is 1 μm, the n+ substrate β-gallium oxide thickness is 0.5 μm, the n-epitaxial β-gallium oxide thickness is 5 μm, the ferroelectric layer thickness is 50 nm, the n+ doped β-gallium oxide thickness is 0.5 μm, the insulating medium thickness is 4 nm, the emitter metal thickness is 400 nm, and the base thickness is 5 nm.

The doping concentration of the n+ substrate β-gallium oxide is 1×10 ¹⁸ cm ⁻³ , the doping concentration of the n-epitaxial β-gallium oxide is 6×10 ¹⁶ cm ⁻³ , and the doping concentration of the n+ doped β-gallium oxide is 1×10 ¹⁸ cm ⁻³ .

The material of the ferroelectric layer is Pb(Zr, Ti)O ₃ .

The collector, emitter and base are made of the same metal material, Au.

The doping concentrations of the n+ substrate β-gallium oxide and the n+ doped β-gallium oxide are for forming ohmic contact between the collector and the emitter to reduce contact resistance; the n-epitaxial β-gallium oxide is for controlling the withstand voltage region within the range of the ferroelectric layer and the n-epitaxial β-gallium oxide when the device is turned off to avoid affecting the characteristics of the highly doped β-gallium oxide.

The p-type doping of the gallium oxide substrate is controlled by the field formed by the electric polarization of the ferroelectric layer, which avoids the problem that the p-type doping of β-gallium oxide is difficult to achieve at present. The device structure is mainly homoepitaxial, which avoids the device reliability problem caused by mismatch.

The ferroelectric layer is to be doped with p-type β-gallium oxide. At the same time, a through-hole process is adopted to pass through the emitter and n+ doped β-gallium oxide, which is in direct contact with the ferroelectric layer, and the formed p-type doping potential is led out.

The preparation method of the insulating medium is:

A1: Weigh 3g 7-aminobenzofuran, 7g 1,4-diacryloylpiperazine, 2g ethylenediamine, 150g butyl acrylate, stir at 50°C for 40 minutes, add 1000g silica sol with SiO ₂ mass content of 20%, and disperse at 1000 rpm to obtain an insulating gel;

A2: Coat the surface of the ferroelectric layer with insulating gel, then put it into a plasma surface treatment apparatus for polymerization to obtain an insulating medium.

The process parameters of the plasma surface treatment instrument PlasmaAPC500 are as follows: RF power 300 W, treatment time 50 seconds, argon gas flow rate 20 sccm, working pressure 200 mTorr, and generator frequency about 20 kHz.

Example 2

A method for preparing a vertical β-gallium oxide NPN transistor, wherein the vertical structure comprises: from bottom to top, a collector, an n+ substrate β-gallium oxide, an n-epitaxial β-gallium oxide, a ferroelectric layer, an n+ doped β-gallium oxide, an insulating medium, a base, and an emitter, wherein the operation steps are as follows:

Step 1: deposit a layer of collector metal on the n+ substrate β-gallium oxide;

Step 2: depositing a layer of n-epitaxial β-gallium oxide on the n+ substrate β-gallium oxide by organic chemical vapor deposition process; the CVD materials are Si and gallium oxide single crystal, at 810°C and 1.2MPa;

Step 3: depositing a barrier layer on the n-epitaxial β-gallium oxide, etching a ferroelectric layer through hole, etching to form a ferroelectric layer area, and depositing a ferroelectric layer; etching is performed using a wet chemical solution, the solution is a mixture of sulfuric acid and hydrogen peroxide, the ratio of sulfuric acid is 1:1, the ratio of hydrogen peroxide solution is 32%, and the ratio of sulfuric acid to hydrogen peroxide is 1:2;

Step 4: remove the original barrier layer, and deposit a layer of n+ doped β-gallium oxide on the n-epitaxial β-gallium oxide by organic chemical vapor deposition process; the CVD materials are Si and gallium oxide single crystal, at 810°C and 1.2MPa;

Step 5: Depositing a layer of emitter metal on the n+ doped β-gallium oxide;

Step 6: forming a barrier layer on the emitter metal, etching an insulating dielectric through hole, etching to form an insulating dielectric region, and depositing an insulating dielectric; etching is performed using a wet chemical solution, the solution is a mixture of sulfuric acid and hydrogen peroxide, the ratio of sulfuric acid is 1:1, the ratio of hydrogen peroxide solution is 32%, and the ratio of sulfuric acid to hydrogen peroxide is 1:2;

Step 7: Remove the original barrier layer, re-form the barrier layer, etch the base metal through hole, etch to form the base metal area, and deposit the active metal. Etching is done by wet chemical solution etching, the solution is a mixture of sulfuric acid and hydrogen peroxide, the ratio of sulfuric acid is 1:1, the ratio of hydrogen peroxide solution is 32%, and the ratio of sulfuric acid and hydrogen peroxide is 1:2.

The collector thickness is 2 μm, the n+ substrate β-gallium oxide thickness is 1 μm, the n-epitaxial β-gallium oxide thickness is 8 μm, the ferroelectric layer thickness is 80 nm, the n+ doped β-gallium oxide thickness is 1 μm, the insulating medium thickness is 5 nm, the emitter metal thickness is 450 nm, and the base thickness is 8 nm.

The doping concentration of the n+ substrate β-gallium oxide is 1×10 ¹⁸ cm ⁻³ , the doping concentration of the n-epitaxial β-gallium oxide is 6×10 ¹⁶ cm ⁻³ , and the doping concentration of the n+ doped β-gallium oxide is 1×10 ¹⁸ cm ⁻³ .

The material of the ferroelectric layer is BaTiO ₃ .

The collector, emitter and base are made of the same metal material, Ni.

The doping concentrations of the n+ substrate β-gallium oxide and the n+ doped β-gallium oxide are for forming ohmic contact between the collector and the emitter to reduce contact resistance; the n-epitaxial β-gallium oxide is for controlling the withstand voltage region within the range of the ferroelectric layer and the n-epitaxial β-gallium oxide when the device is turned off to avoid affecting the characteristics of the highly doped β-gallium oxide.

The p-type doping of the gallium oxide substrate is controlled by the field formed by the electric polarization of the ferroelectric layer, which avoids the problem that the p-type doping of β-gallium oxide is difficult to achieve at present. The device structure is mainly homoepitaxial, which avoids the device reliability problem caused by mismatch.

The ferroelectric layer is to be doped with p-type β-gallium oxide. At the same time, a through-hole process is adopted to pass through the emitter and n+ doped β-gallium oxide, which is in direct contact with the ferroelectric layer, and the formed p-type doping potential is led out.

The preparation method of the insulating medium is:

A1: Weigh 4g 7-aminobenzofuran, 9g 1,4-diacryloylpiperazine, 3g ethylenediamine, and 160g butyl acrylate, stir at 55°C for 60 minutes, add 1200g silica sol with a SiO ₂ mass content of 25%, and disperse at a high speed of 1400 rpm to obtain an insulating gel;

A2: Coat the surface of the ferroelectric layer with insulating gel, then put it into a plasma surface treatment apparatus for polymerization to obtain an insulating medium.

The process parameters of the plasma surface treatment instrument PlasmaAPC500 are as follows: RF power 320 W, treatment time 70 seconds, argon gas flow rate 25 sccm, working pressure 250 mTorr, and generator frequency about 25 kHz.

Example 3

A method for preparing a vertical β-gallium oxide NPN transistor, wherein the vertical structure comprises: from bottom to top, a collector, an n+ substrate β-gallium oxide, an n-epitaxial β-gallium oxide, a ferroelectric layer, an n+ doped β-gallium oxide, an insulating medium, a base, and an emitter, wherein the operation steps are as follows:

Step 1: deposit a layer of collector metal on the n+ substrate β-gallium oxide;

Step 2: depositing a layer of n-epitaxial β-gallium oxide on the n+ substrate β-gallium oxide by organic chemical vapor deposition process; the CVD materials are Si and gallium oxide single crystal, at 840°C and 1.4MPa;

Step 3: depositing a barrier layer on the n-epitaxial β-gallium oxide, etching a ferroelectric layer through hole, etching to form a ferroelectric layer area, and depositing a ferroelectric layer; etching is performed using a wet chemical solution, the solution is a mixture of sulfuric acid and hydrogen peroxide, the ratio of sulfuric acid is 1:1, the ratio of hydrogen peroxide solution is 34%, and the ratio of sulfuric acid to hydrogen peroxide is 1:3;

Step 4: remove the original barrier layer, and deposit a layer of n+ doped β-gallium oxide on the n-epitaxial β-gallium oxide by organic chemical vapor deposition process; the CVD materials are Si and gallium oxide single crystal, at 840°C and 1.4MPa;

Step 5: Depositing a layer of emitter metal on the n+ doped β-gallium oxide;

Step 6: forming a barrier layer on the emitter metal, etching an insulating dielectric through hole, etching to form an insulating dielectric region, and depositing an insulating dielectric; etching is performed using a wet chemical solution, the solution is a mixture of sulfuric acid and hydrogen peroxide, the ratio of sulfuric acid is 1:1, the ratio of hydrogen peroxide solution is 34%, and the ratio of sulfuric acid to hydrogen peroxide is 1:3;

Step 7: Remove the original barrier layer, re-form the barrier layer, etch the base metal through hole, etch to form the base metal area, and deposit the active metal. Etching is done by wet chemical solution etching, the solution is a mixture of sulfuric acid and hydrogen peroxide, the ratio of sulfuric acid is 1:1, the ratio of hydrogen peroxide solution is 34%, and the ratio of sulfuric acid and hydrogen peroxide is 1:3.

The collector thickness is 2 μm, the n+ substrate β-gallium oxide thickness is 1.5 μm, the n-epitaxial β-gallium oxide thickness is 13 μm, the ferroelectric layer thickness is 130 nm, the n+ doped β-gallium oxide thickness is 1.5 μm, the insulating medium thickness is 5 nm, the emitter metal thickness is 550 nm, and the base thickness is 13 nm.

The doping concentration of the n+ substrate β-gallium oxide is 1×10 ¹⁸ cm ⁻³ , the doping concentration of the n-epitaxial β-gallium oxide is 6×10 ¹⁶ cm ⁻³ , and the doping concentration of the n+ doped β-gallium oxide is 1×10 ¹⁸ cm ⁻³ .

The material of the ferroelectric layer is (Bi, Na)TiO ₃ .

The collector, emitter and base are made of the same metal material, Ni.

The doping concentrations of the n+ substrate β-gallium oxide and the n+ doped β-gallium oxide are for forming ohmic contact between the collector and the emitter to reduce contact resistance; the n-epitaxial β-gallium oxide is for controlling the withstand voltage region within the range of the ferroelectric layer and the n-epitaxial β-gallium oxide when the device is turned off to avoid affecting the characteristics of the highly doped β-gallium oxide.

The p-type doping of the gallium oxide substrate is controlled by the field formed by the electric polarization of the ferroelectric layer, which avoids the problem that the p-type doping of β-gallium oxide is difficult to achieve at present. The device structure is mainly homoepitaxial, which avoids the device reliability problem caused by mismatch.

The ferroelectric layer is to be doped with p-type β-gallium oxide. At the same time, a through-hole process is adopted to pass through the emitter and n+ doped β-gallium oxide, which is in direct contact with the ferroelectric layer, and the formed p-type doping potential is led out.

The preparation method of the insulating medium is:

A1: Weigh 5g 7-aminobenzofuran, 12g 1,4-diacryloylpiperazine, 3g ethylenediamine, and 180g butyl acrylate, stir at 55°C for 80 minutes, then add 1800g silica sol with a SiO ₂ mass content of 25%, and disperse at a high speed of 1800 rpm to obtain an insulating gel;

A2: Coat the surface of the ferroelectric layer with insulating gel, then put it into a plasma surface treatment apparatus for polymerization to obtain an insulating medium.

The process parameters of the plasma surface treatment instrument PlasmaAPC500 are as follows: RF power 340 W, treatment time 90 seconds, argon gas flow rate 35 sccm, working pressure 280 mTorr, and generator frequency about 35 kHz.

Example 4

A method for preparing a vertical β-gallium oxide NPN transistor, wherein the vertical structure comprises: from bottom to top, a collector, an n+ substrate β-gallium oxide, an n-epitaxial β-gallium oxide, a ferroelectric layer, an n+ doped β-gallium oxide, an insulating medium, a base, and an emitter, wherein the operation steps are as follows:

Step 1: deposit a layer of collector metal on the n+ substrate β-gallium oxide;

Step 2: depositing a layer of n-epitaxial β-gallium oxide on the n+ substrate β-gallium oxide by organic chemical vapor deposition process; the CVD materials are Si and gallium oxide single crystal, at 850°C and 1.5MPa;

Step 3: depositing a barrier layer on the n-epitaxial β-gallium oxide, etching a ferroelectric layer through hole, etching to form a ferroelectric layer area, and depositing a ferroelectric layer; etching is performed using a wet chemical solution, the solution is a mixture of sulfuric acid and hydrogen peroxide, the ratio of sulfuric acid is 1:1, the ratio of hydrogen peroxide solution is 35%, and the ratio of sulfuric acid to hydrogen peroxide is 1:3;

Step 4: remove the original barrier layer, and deposit a layer of n+ doped β-gallium oxide on the n-epitaxial β-gallium oxide by organic chemical vapor deposition process; the CVD materials are Si and gallium oxide single crystal, at 850°C and 1.5MPa;

Step 5: Depositing a layer of emitter metal on the n+ doped β-gallium oxide;

Step 6: forming a barrier layer on the emitter metal, etching an insulating dielectric through hole, etching to form an insulating dielectric region, and depositing an insulating dielectric; etching is performed using a wet chemical solution, the solution is a mixture of sulfuric acid and hydrogen peroxide, the ratio of sulfuric acid is 1:1, the ratio of hydrogen peroxide solution is 35%, and the ratio of sulfuric acid to hydrogen peroxide is 1:3;

Step 7: Remove the original barrier layer, re-form the barrier layer, etch the base metal through hole, etch to form the base metal area, and deposit the active metal. Etching is done by wet chemical solution etching, the solution is a mixture of sulfuric acid and hydrogen peroxide, the ratio of sulfuric acid is 1:1, the ratio of hydrogen peroxide solution is 35%, and the ratio of sulfuric acid to hydrogen peroxide is 1:3.

The collector thickness is 3 μm, the n+ substrate β-gallium oxide thickness is 2 μm, the n-epitaxial β-gallium oxide thickness is 15 μm, the ferroelectric layer thickness is 150 nm, the n+ doped β-gallium oxide thickness is 2 μm, the insulating medium thickness is 6 nm, the emitter metal thickness is 600 nm, and the base thickness is 15 nm.

The doping concentration of the n+ substrate β-gallium oxide is 1×10 ¹⁸ cm ⁻³ , the doping concentration of the n-epitaxial β-gallium oxide is 6×10 ¹⁶ cm ⁻³ , and the doping concentration of the n+ doped β-gallium oxide is 1×10 ¹⁸ cm ⁻³ .

The material of the ferroelectric layer is PVDF.

The collector, emitter and base are made of the same metal material, Cu.

The doping concentrations of the n+ substrate β-gallium oxide and the n+ doped β-gallium oxide are for forming ohmic contact between the collector and the emitter to reduce contact resistance; the n-epitaxial β-gallium oxide is for controlling the withstand voltage region within the range of the ferroelectric layer and the n-epitaxial β-gallium oxide when the device is turned off to avoid affecting the characteristics of the highly doped β-gallium oxide.

The p-type doping of the gallium oxide substrate is controlled by the field formed by the electric polarization of the ferroelectric layer, which avoids the problem that the p-type doping of β-gallium oxide is difficult to achieve at present. The device structure is mainly homoepitaxial, which avoids the device reliability problem caused by mismatch.

The ferroelectric layer is to be doped with p-type β-gallium oxide. At the same time, a through-hole process is adopted to pass through the emitter and n+ doped β-gallium oxide, which is in direct contact with the ferroelectric layer, and the formed p-type doping potential is led out.

The preparation method of the insulating medium is:

A1: Weigh 6 g 7-aminobenzofuran, 14 g 1,4-diacryloylpiperazine, 4 g ethylenediamine, and 200 g butyl acrylate, stir at 60°C for 100 minutes, add 2000 g silica sol with a SiO ₂ mass content of 30%, and disperse at a high speed of 2000 rpm to obtain an insulating gel;

A2: Coat the surface of the ferroelectric layer with insulating gel, then put it into a plasma surface treatment apparatus for polymerization to obtain an insulating medium.

The process parameters of the plasma surface treatment instrument PlasmaAPC500 are as follows: RF power 350 W, treatment time 100 seconds, argon gas flow rate 40 sccm, working pressure 300 mTorr, and generator frequency about 40 kHz.

Comparative Example 1

The other steps were the same as in Example 1 except that 7-aminobenzofuran was not added.

Comparative Example 2

The other steps were the same as in Example 1 except that 1,4-diacryloylpiperazine was not added.

Comparative Example 3

The other steps were the same as in Example 1 except that butyl acrylate was not added.

Test results:

Through the data analysis of the above embodiments and comparative examples, the vertical β-gallium oxide NPN transistor prepared by the present invention has a saturation current of 8A/mm², an on-resistance of 134.2Ω.mm, and a three-terminal breakdown voltage of 985V at room temperature and 2.5V, and has excellent on-state performance.

The above description is only a preferred embodiment of the present invention and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technical personnel in this field can make some changes or modify the technical contents disclosed above into equivalent embodiments without departing from the scope of the technical solution of the present invention. However, any brief modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention are still within the scope of the technical solution of the present invention.

Claims (10)

1. A preparation method of a longitudinal beta gallium oxide NPN transistor, the longitudinal structure of which comprises: the collector, the n+ substrate beta gallium oxide, the n-epitaxial beta gallium oxide, the ferroelectric layer, the n+ doped beta gallium oxide, the insulating medium, the base and the emitter from bottom to top, the operation steps are as follows:

step 1: depositing a layer of collector metal on the n+ substrate beta gallium oxide;

step 2: depositing a layer of n-epitaxial beta gallium oxide on the n+ substrate beta gallium oxide by adopting an organic chemical vapor deposition process; the CVD material is Si and gallium oxide monocrystal, and the temperature is 800-850 ℃ and the pressure is 1-1.5 MPa;

Step 3: depositing a barrier layer on the n-epitaxial beta gallium oxide, etching the ferroelectric layer through hole, etching to form a ferroelectric layer area, and depositing a ferroelectric layer; the etching adopts wet chemical solution etching, the solution is mixed solution of sulfuric acid and hydrogen peroxide, the sulfuric acid ratio is 1:1, the hydrogen peroxide solution ratio is 30-35%, and the sulfuric acid and hydrogen peroxide ratio is 1:2-3;

Step 4: removing the original barrier layer, and depositing a layer of n+ doped beta gallium oxide on the n-epitaxial beta gallium oxide by adopting an organic chemical vapor deposition process; the CVD material is Si and gallium oxide monocrystal, and the temperature is 800-850 ℃ and the pressure is 1-1.5 MPa;

step 5: depositing a layer of emitter metal on the n+ doped beta gallium oxide;

Step 6: forming a barrier layer on the emitter metal, etching the insulating medium through hole, etching to form an insulating medium area, and depositing an insulating medium; the etching adopts wet chemical solution etching, the solution is mixed solution of sulfuric acid and hydrogen peroxide, the sulfuric acid ratio is 1:1, the hydrogen peroxide solution ratio is 30-35%, and the sulfuric acid and hydrogen peroxide ratio is 1:2-3;

Step 7: removing the original barrier layer, reforming the barrier layer, etching the base metal through hole, etching to form a base metal region, depositing active metal, etching by adopting wet chemical solution, wherein the solution is sulfuric acid and hydrogen peroxide mixed solution, the sulfuric acid ratio is 1:1, the hydrogen peroxide solution ratio is 30-35%, and the sulfuric acid and hydrogen peroxide ratio is 1:2-3.

2. The method for manufacturing a longitudinal beta gallium oxide NPN transistor according to claim 1, wherein: the thickness of the collector electrode is 1-3 mu m, the thickness of the n+ substrate beta gallium oxide is 0.5-2 mu m, the thickness of the n-epitaxial beta gallium oxide is 5-15 mu m, the thickness of the ferroelectric layer is 50-150nm, the thickness of the n+ doped beta gallium oxide is 0.5-2 mu m, the thickness of the insulating medium is 4-6nm, the thickness of the emitter electrode metal is 400-600nm, and the thickness of the base electrode is 5-15nm.

3. The method for manufacturing a longitudinal beta gallium oxide NPN transistor according to claim 1, wherein: the doping concentration of the n+ substrate beta gallium oxide is 1X10 ¹⁸cm^-3, the doping concentration of the n-epitaxial beta gallium oxide is 6X10 ¹⁶cm^-3, and the doping concentration of the n+ doped beta gallium oxide is 1X10 ¹⁸cm^-3.

4. The method for manufacturing a longitudinal beta gallium oxide NPN transistor according to claim 1, wherein: the ferroelectric layer material is one or more of Pb (Zr, ti) O ₃、BaTiO₃、(Bi,Na)TiO₃ and PVDF.

5. The method for manufacturing a longitudinal beta gallium oxide NPN transistor according to claim 1, wherein: the collector, the emitter and the base are made of the same metal material and are one or alloy of Au, ni and Cu.

6. The method for manufacturing a longitudinal beta gallium oxide NPN transistor according to claim 1, wherein: the doping concentration of the n+ substrate beta gallium oxide and the n+ doped beta gallium oxide form ohmic contact of a collector and an emitter, so that contact resistance is reduced; the n-epitaxial beta gallium oxide controls the voltage-resistant area of the device in the range of the ferroelectric layer and the n-epitaxial beta gallium oxide when the device is turned off.

7. The method for manufacturing a vertical beta gallium oxide NPN transistor as defined in claim 6, wherein: the substrate beta gallium oxide adopts a gallium oxide substrate, p-type doping of the substrate beta gallium oxide is controlled through a field formed by electric polarization of a ferroelectric layer, and a device structure is mainly homoepitaxy.

8. The method for manufacturing a longitudinal beta gallium oxide NPN transistor according to claim 1, wherein: the ferroelectric layer is to be formed with p-type beta gallium oxide doping, and the through holes penetrating through the emitter and the n+ doped beta gallium oxide are in direct contact with the ferroelectric layer.

9. The method for manufacturing a longitudinal beta gallium oxide NPN transistor according to claim 1, wherein: the preparation method of the insulating medium comprises the following steps:

A1: weighing 3-6 parts of 7-aminobenzofuran, 7-14 parts of 1, 4-diacryloyl piperazine, 2-4 parts of ethylenediamine, 150-200 parts of butyl acrylate, stirring at 50-60 ℃ for 40-100 minutes, adding 1000-2000 parts of silica sol with the mass content of 20% -30% of SiO ₂, and dispersing at a high speed of 1000-2000 revolutions per minute to obtain insulating gel;

a2: and coating the surface of the ferroelectric layer with insulating gel, and then placing the ferroelectric layer into a plasma surface treatment instrument for polymerization to obtain an insulating medium.

10. The method for manufacturing a longitudinal beta gallium oxide NPN transistor as defined in claim 9, wherein: the process parameters of the plasma surface treatment instrument PLASMAAPC are that the radio frequency power is 300-350W, the treatment time is 50-100 seconds, the argon flow is 20-40sccm, the working pressure is 200-300mTorr, and the generator frequency is about 20-40kHz.