CN118507500A - Image pickup apparatus - Google Patents

Abstract

The image pickup device includes a pixel region including a plurality of pixels and a signal line. The pixel includes a semiconductor substrate, a photoelectric conversion portion, a 1 st transistor, a wiring layer, and a capacitor element, respectively. The photoelectric conversion portion includes a 1 st electrode, a 2 nd electrode, and a photoelectric conversion layer between the 1 st and 2 nd electrodes. The 1 st transistor includes 1 st and 2 nd impurity regions. The wiring layer is between the semiconductor substrate and the 2 nd electrode, and includes a part of the signal line. The capacitor element is disposed between the wiring layer and the semiconductor substrate in a normal direction of the semiconductor substrate, and includes a3 rd electrode, a 4 th electrode, and a dielectric layer. One of the 1 st and 2 nd impurity regions functions as a source region and the other as a drain region of the 1 st transistor. The 1 st impurity region is electrically connected to the 2 nd electrode; the 4 th electrode is electrically connected to either of the 1 st and 2 nd impurity regions; at least one of the 3 rd and 4 th electrodes covers the 1 st impurity region when viewed in a normal direction of the semiconductor substrate.

Description

Camera device

This application is a divisional application of the Chinese patent application with the application date of October 26, 2018, application number 201811256952.4, and name “Camera Device”.

Technical Field

The present disclosure relates to an imaging device, and particularly to an imaging device including a photoelectric conversion unit supported by a semiconductor substrate.

Background Art

An imaging device having a structure in which a photoelectric conversion layer is arranged above a semiconductor substrate on which a CCD (Charge Coupled Device) circuit or a CMOS (Complementary MOS) circuit is formed has been proposed. An imaging device having a photoelectric conversion layer above a semiconductor substrate is also called a stacked imaging device. For example, Japanese Patent Publication No. 2012-151771 discloses a solid-state imaging element having such a stacked structure.

The stacked imaging device accumulates the charge generated by photoelectric conversion in the charge accumulation region, and reads out the accumulated charge through a readout circuit including a CCD circuit or a CMOS circuit. The photoelectric conversion layer is usually arranged on an insulating layer covering a semiconductor substrate on which the readout circuit is formed. The photoelectric conversion layer on the insulating layer is electrically connected to the readout circuit via a connection portion provided in the insulating layer.

Summary of the invention

An imaging device according to a non-limiting exemplary embodiment of the present disclosure includes: a pixel region including a plurality of pixels; and a signal line arranged across two or more of the plurality of pixels and extending from the inside of the pixel region to the outside of the pixel region. The plurality of pixels each include a semiconductor substrate, a photoelectric conversion unit, a first transistor, a wiring layer, and a capacitor. The photoelectric conversion unit is supported by the semiconductor substrate and includes a first electrode, a second electrode arranged closer to the semiconductor substrate than the first electrode, and a photoelectric conversion layer arranged between the first electrode and the second electrode. The first transistor includes a first impurity region arranged in the semiconductor substrate and a second impurity region arranged in the semiconductor substrate. The wiring layer is arranged between the semiconductor substrate and the second electrode and includes a portion of the signal line. The capacitor is arranged between the wiring layer and the semiconductor substrate in the normal direction of the semiconductor substrate and includes a third electrode, a fourth electrode arranged between the third electrode and the semiconductor substrate, and a dielectric layer arranged between the third electrode and the fourth electrode.

The imaging device is configured such that one of the first impurity region and the second impurity region functions as a source region of the first transistor, and the other of the first impurity region and the second impurity region functions as a drain region of the first transistor;

The first impurity region is electrically connected to the second electrode;

The fourth electrode is electrically connected to one of the first impurity region and the second impurity region;

When viewed along a normal direction of the semiconductor substrate, at least one electrode selected from the group consisting of the third electrode and the fourth electrode covers the first impurity region.

The inclusive or specific technical solutions may also be implemented by components, devices, systems, integrated circuits or methods. In addition, the inclusive or specific technical solutions may also be implemented by any combination of components, devices, apparatuses, systems, integrated circuits and methods.

Additional effects and advantages of the disclosed embodiments will become apparent from the specification and drawings. The effects and/or advantages are provided by various embodiments or features disclosed in the specification and drawings, respectively, and it is not necessary to obtain all of them in order to obtain one or more of them.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram showing an exemplary circuit configuration of an imaging device according to an embodiment of the present disclosure.

FIG. 2 is a diagram showing an example of a circuit configuration of a pixel.

FIG. 3 is a schematic cross-sectional view of one of a plurality of pixels included in the imaging device.

FIG. 4 is a schematic plan view showing an example of the layout of each element in a pixel.

FIG. 5 is a diagram for explaining the relationship between pixels and various signal lines connected to the pixels.

6 is a plan view showing an example of the arrangement relationship among the wiring layer, the upper electrode, and the impurity region when the photoelectric conversion part is removed from the pixel and the semiconductor substrate is viewed from the normal direction.

FIG. 7 is a plan view schematically showing an example of the arrangement of the connection portion with respect to the first capacitor element.

FIG. 8 is a plan view showing an example of a chip having a pixel region including a plurality of pixels.

FIG. 9 is a schematic cross-sectional view for explaining a manufacturing process of a pixel including a MIM structure having no opening in an interlayer insulating layer.

FIG. 10 is a schematic cross-sectional view for explaining another manufacturing process of a pixel including an MIM structure having no opening in an interlayer insulating layer.

FIG. 11 is a schematic cross-sectional view for explaining a manufacturing process of a pixel to which an MIM structure having an opening is applied as a first capacitor.

FIG. 12 is a schematic cross-sectional view for explaining another manufacturing process of a pixel to which an MIM structure having an opening is applied as a first capacitor.

FIG. 13 is a plan view showing a modified example of the imaging device.

FIG. 14 is a schematic cross-sectional view showing a modification of the imaging device.

FIG. 15 is a schematic cross-sectional view of a pixel of an imaging device according to another embodiment of the present disclosure.

FIG. 16 is a diagram showing an exemplary circuit configuration of the pixel shown in FIG. 15 .

DETAILED DESCRIPTION

Before describing the embodiments of the present disclosure in detail, an overview of one technical solution of the present disclosure will be described. An overview of one technical solution of the present disclosure is as follows.

[Project 1]

The imaging device of item 1 of the present disclosure comprises: a pixel region including a plurality of pixels; and a signal line arranged across two or more of the plurality of pixels and extending from the inside of the pixel region to the outside of the pixel region. The plurality of pixels respectively include a semiconductor substrate, a photoelectric conversion unit, a first transistor, a wiring layer, and a capacitor.

The photoelectric conversion section is supported by the semiconductor substrate and includes a first electrode, a second electrode disposed closer to the semiconductor substrate than the first electrode, and a photoelectric conversion layer disposed between the first electrode and the second electrode.

The first transistor includes a first impurity region disposed in the semiconductor substrate and a second impurity region disposed in the semiconductor substrate.

The wiring layer is arranged between the semiconductor substrate and the second electrode, and includes a part of the signal line.

The capacitor is disposed between the wiring layer and the semiconductor substrate in a normal direction of the semiconductor substrate and includes a third electrode, a fourth electrode disposed between the third electrode and the semiconductor substrate, and a dielectric layer disposed between the third electrode and the fourth electrode.

The imaging device is configured such that one of the first impurity region and the second impurity region functions as a source region of the first transistor, and the other of the first impurity region and the second impurity region functions as a drain region of the first transistor;

The first impurity region is electrically connected to the second electrode;

The fourth electrode is electrically connected to one of the first impurity region and the second impurity region;

When viewed along a normal direction of the semiconductor substrate, at least one selected from the group consisting of the third electrode and the fourth electrode covers the first impurity region.

According to the structure of item 1, the third electrode and/or the fourth electrode can function as a light shielding layer. At least one of the third electrode and the fourth electrode covers the first impurity region, thereby suppressing the incidence of light on the first impurity region and suppressing the generation of spurious signals.

In addition, according to the structure of Item 1, since the capacitor element is arranged closer to the semiconductor substrate than the wiring layer including a portion of the signal line extending to the outside of the pixel area, it is possible to more effectively suppress the incidence of light obliquely incident on the pixel from entering the first impurity region.

[Project 2]

In the imaging device described in item 1, each of the plurality of pixels may further include a second transistor including a gate electrode electrically connected to the second electrode.

[Item 3]

In the imaging device described in item 1 or 2, when viewed along the normal direction, the at least one electrode selected from the group consisting of the third electrode and the fourth electrode may cover at least a portion of the second impurity region.

According to the structure of item 3, the second impurity region is covered by at least one of the third electrode and the fourth electrode, so that the incidence of light on the second impurity region can be suppressed. By suppressing the incidence of light on the second impurity region, the potential of the charge storage region can be prevented from indirectly changing due to the generation of charges in the second impurity region.

[Item 4]

The imaging device described in Item 2 may further include a connection portion electrically connecting the second electrode to the first impurity region and electrically connecting the second electrode to the gate electrode of the second transistor.

[Item 5]

In the imaging device described in Item 4, at least one selected from the group consisting of the third electrode and the fourth electrode may include an opening.

According to the structure of item 5, even when an interlayer insulating layer is provided between the photoelectric conversion unit and the semiconductor substrate and a capacitor is arranged in the interlayer insulating layer, it is possible to suppress the protrusion of the interlayer insulating layer on the pixel region relative to the portion on the peripheral region. That is, the step of the interlayer insulating layer between the pixel region and the peripheral region can be reduced, and the degradation of image quality due to, for example, shadows can be suppressed.

[Item 6]

In the imaging device described in Item 5, the connecting portion may penetrate the opening.

According to the structure of item 6, a larger electrode area can be secured for the capacitor element.

[Item 7]

In the imaging device described in any one of items 4 to 6, the fourth electrode may have a first surface opposite to the third electrode and a second surface opposite to the first surface, and is electrically connected to the second impurity region; and at least a portion of the connection portion is opposite to the second surface and extends in a plane perpendicular to the normal direction.

According to the configuration of item 7, a capacitance can be formed between a part of the connection portion and a part of the fourth electrode.

[Item 8]

In the imaging device described in Item 7, the fourth electrode may be electrically connected to the second impurity region on the second surface.

According to the structure of item 8, the electrical coupling between the fourth electrode and other electrodes and/or wirings can be suppressed, and the mixing of noise can be further reduced.

[Item 9]

The imaging device described in Item 7 or 8 may further include a feedback circuit for providing negative feedback to the output of the second transistor; the feedback circuit includes a third transistor including a source and a drain; and one of the source and the drain is connected to the second impurity region.

According to the structure of item 9, the kTC noise can be eliminated using the feedback circuit.

[Item 10]

In the imaging device described in any one of items 4 to 6, the fourth electrode may include a first surface facing the third electrode and a second surface opposite to the first surface, and may be electrically connected to the connection portion.

[Item 11]

In the imaging device described in Item 10, the fourth electrode may be connected to the connection portion on the second surface.

According to the structure of item 11, the electrical coupling between the fourth electrode and other electrodes and/or wirings can be suppressed, and the mixing of noise can be further reduced.

[Item 12]

The imaging device described in Item 10 or 11 may further include a feedback circuit for negatively feeding back an output of the second transistor; and the second impurity region may be electrically connected to an output line of the feedback circuit.

According to the structure of item 12, the kTC noise can be eliminated using the feedback circuit.

[Item 13]

In the imaging device described in any one of items 7 to 12, the dielectric layer may cover a portion of the surface of the fourth electrode other than the second surface; and the third electrode may cover a side surface of the fourth electrode connecting the first surface and the second surface.

According to the structure of item 13, the electrical coupling between the fourth electrode and other electrodes and/or wirings can be suppressed, and the mixing of noise can be further reduced.

[Item 14]

In the imaging device described in any one of items 1 to 13, the signal line may be a control line for driving the two or more pixels, a power line for supplying voltage to the two or more pixels, or an output line for reading signals from the two or more pixels.

[Item 15]

In the imaging device described in any one of items 1 to 14, when viewed along the normal direction, the at least one electrode selected from the group consisting of the third electrode and the fourth electrode may cover the entire first impurity region.

In the present disclosure, all or part of a circuit, unit, device, component or part, or all or part of a functional block of a block diagram may also be performed by one or more electronic circuits including a semiconductor device, a semiconductor integrated circuit (IC), or an LSI (large scale integration). LSI or IC may be integrated into one chip, or may be composed of a combination of multiple chips. For example, functional blocks other than storage elements may be integrated into one chip. Here, it is called LSI or IC, but the name changes depending on the degree of integration, and it may also be called system LSI, VLSI (very large scale integration) or ULSI (ultra large scale integration). A field programmable gate array (FPGA) programmed after the manufacture of LSI, or a reconfigurable logic device capable of reconfiguring the bonding relationship within LSI or setting the circuit division within LSI may also be used for the same purpose.

Furthermore, all or part of the functions or operations of a circuit, unit, device, component or part can be performed by software processing. In this case, the software is recorded in one or more non-temporary recording media such as ROMs, optical disks, hard disk drives, etc. When the software is executed by a processor, the functions determined by the software are executed by the processor and peripheral devices. The system or device may also have one or more non-temporary recording media with software recorded, a processor, and necessary hardware devices such as interfaces.

Hereinafter, the embodiments of the present disclosure are described in detail. In addition, the embodiments described below all represent inclusive or specific examples. The numerical values, shapes, materials, constituent elements, configurations of constituent elements and connection forms, steps, the order of steps, etc. shown in the following embodiments are examples and are not intended to limit the present disclosure. The various technical solutions described in this specification can be combined with each other as long as there is no contradiction. In addition, among the constituent elements of the following embodiments, the constituent elements that are not recorded in the independent claims representing the highest concept are described as arbitrary constituent elements. In each figure, constituent elements having substantially the same function are represented by common reference numerals, and there are cases where repeated descriptions are omitted or simplified.

As described later with reference to the accompanying drawings, an imaging device of a typical embodiment of the present disclosure has a plurality of pixels, each of which includes a semiconductor substrate having a plurality of impurity regions and a photoelectric conversion unit supported by the semiconductor substrate. An interlayer insulating layer having a connection portion inside is located between the semiconductor substrate and the photoelectric conversion unit. The impurity region of the semiconductor substrate is electrically connected to the photoelectric conversion unit via the connection portion, and includes a first impurity region that functions as one of the source region and the drain region of the reset transistor, and a second impurity region that functions as the other of the source region and the drain region. The first impurity region constitutes at least a part of the charge storage region, and a signal corresponding to the amount of charge stored in the charge storage region, such as a voltage signal, is read out as an image signal.

The pixels are provided in an interlayer insulating layer sandwiched by a semiconductor substrate and a photoelectric conversion unit: a capacitor including an electrode at least a portion of which overlaps with a first impurity region and/or a second impurity region when viewed from above; and a wiring layer located between the photoelectric conversion unit and the capacitor, including a portion of a signal line extending to the outside of a pixel region composed of a plurality of pixels. The electrode of the capacitor functions as a light shielding layer, thereby suppressing the occurrence of a false signal caused by the incidence of light to the first or second impurity region, and obtaining an image with reduced noise. In particular, since the capacitor is arranged closer to the semiconductor substrate than the wiring layer including a portion of the signal line extending to the outside of the pixel region, it is possible to more effectively suppress the incidence of light incident from an oblique direction relative to the pixel to the first impurity region.

(Implementation Method 1)

FIG1 shows an overview of an exemplary circuit structure of an imaging device according to an embodiment of the present disclosure. The imaging device 100 shown in FIG1 has a plurality of pixels 10 and peripheral circuits. A pixel region is formed by arranging the pixels 10, for example, two-dimensionally. Here, an example is shown in which four pixels 10 are arranged in a matrix of two rows and two columns. It goes without saying that the number and arrangement of the pixels 10 are not limited to this example. The arrangement of the pixels 10 may also be one-dimensional. In this case, the imaging device 100 can be used as a linear sensor.

The pixels 10 are connected to the power supply wiring 22, respectively, and when in operation, a predetermined power supply voltage is supplied to each pixel 10 via the power supply wiring 22. In addition, the storage control line 17 is connected to each pixel 10. As described in detail later, each pixel 10 includes a photoelectric conversion unit that performs photoelectric conversion on incident light, and a signal detection circuit that detects a signal generated by the photoelectric conversion unit. In a typical embodiment, the storage control line 17 applies a predetermined voltage to the photoelectric conversion unit of each pixel 10 in common.

In the configuration illustrated in FIG1 , the peripheral circuit of the imaging device 100 includes a vertical scanning circuit 16, a plurality of load circuits 19, a plurality of column signal processing circuits 20, a plurality of inverting amplifiers 24, and a horizontal signal readout circuit 21. The load circuit 19, the column signal processing circuit 20, and the inverting amplifier 24 are arranged for each column of the two-dimensionally arranged pixels 10. In addition, the vertical scanning circuit 16 is also referred to as a row scanning circuit, and the column signal processing circuit 20 is also referred to as a row signal accumulation circuit. The horizontal signal readout circuit 21 is also referred to as a column scanning circuit.

The vertical scanning circuit 16 is connected to an address signal line 30 and a reset signal line 26. The vertical scanning circuit 16 selects a plurality of pixels 10 arranged in each row in units of rows by applying a predetermined voltage to the address signal line 30. By selecting a plurality of pixels 10 in units of rows, the signal voltage of the selected pixel 10 is read out and the signal charge is reset as described later.

In the example shown in the figure, a feedback control line 28 and a sensitivity adjustment line 32 are also connected to the vertical scanning circuit 16. In the example described later, a predetermined voltage is applied to the feedback control line 28 by the vertical scanning circuit 16 to form a feedback loop that negatively feeds back the output of the pixel 10. In addition, the vertical scanning circuit 16 can supply a predetermined voltage to the plurality of pixels 10 via the sensitivity adjustment line 32.

The imaging device 100 has vertical signal lines 18 provided for each column of a plurality of pixels 10. A load circuit 19 is electrically connected to each vertical signal line 18. The pixels 10 are electrically connected to a column signal processing circuit 20 via the corresponding vertical signal line 18. The column signal processing circuit 20 performs noise suppression signal processing represented by correlated double sampling and analog-to-digital conversion. A horizontal signal readout circuit 21 is electrically connected to the column signal processing circuit 20 provided corresponding to each column of the pixels 10. The horizontal signal readout circuit 21 sequentially reads signals from the plurality of column signal processing circuits 20 to a horizontal common signal line 23.

In the structure illustrated in FIG. 1 , an inverting amplifier 24 is provided corresponding to each column of a plurality of pixels 10. The negative input terminal of the inverting amplifier 24 is connected to the corresponding vertical signal line 18, and a predetermined voltage Vref is supplied to the positive input terminal of the inverting amplifier 24. Vref is, for example, a positive voltage of about IV or 1V. The output terminal of the inverting amplifier 24 is connected to the pixel 10 connected to the negative input terminal of the inverting amplifier 24 via one of the plurality of feedback lines 25 provided corresponding to the plurality of columns of the pixel 10. The inverting amplifier 24 constitutes a part of a feedback circuit that negatively feeds back the output from the pixel 10. The inverting amplifier 24 may also be referred to as a feedback amplifier. The details of the operation of the inverting amplifier 24 will be described later.

Fig. 2 shows an example of a circuit configuration of the pixel 10. The pixel 10A shown in Fig. 2 includes a photoelectric conversion unit 15 and a signal detection circuit 200. In the configuration shown in Fig. 2, the imaging device 100 includes a feedback circuit 202 for performing negative feedback on the output of the signal detection circuit 200.

The photoelectric conversion unit 15 includes a first electrode 15a, a photoelectric conversion layer 15b, and a second electrode 15c as a pixel electrode. The first electrode 15a of the photoelectric conversion unit 15 is connected to the accumulation control line 17, and the second electrode 15c of the photoelectric conversion unit 15 is connected to the charge accumulation node 44. By controlling the potential of the first electrode 15a via the accumulation control line 17, the positive and negative charges generated by the photoelectric conversion, typically the charges of one polarity of the hole-electron pair, can be collected by the second electrode 15c. In the case of using holes, for example, as signal charges, it is sufficient to make the potential of the first electrode 15a higher than that of the second electrode 15c. The following is an example of using holes as signal charges. For example, a voltage of about 10V is applied to the first electrode 15a via the accumulation control line 17. As a result, the signal charge is accumulated in the charge accumulation node 44. Electrons can also be used as signal charges.

The signal detection circuit 200 includes a signal detection transistor 34 and a first capacitor element 41 that amplifies and outputs a signal generated by the photoelectric conversion unit 15. In the illustrated example, the signal detection circuit 200 also includes a reset transistor 36, a feedback transistor 38, a second capacitor element 42 having a capacitance value smaller than the first capacitor element 41, and an address transistor 40. The reset transistor 36 is equivalent to the first transistor in the present disclosure, and the signal detection transistor 34 is equivalent to the second transistor in the present disclosure. In this way, in the present embodiment, the pixel 10A has more than one capacitor element in each pixel. As described in detail later, if the first capacitor element 41 has a relatively large capacitance value, for example, kTC noise can be effectively reduced. Below, an example of using an N-channel metal oxide semiconductor field effect transistor (MOSFET) as a transistor such as the signal detection transistor 34 is described.

The gate of the signal detection transistor 34 is connected to the charge storage node 44. In other words, the gate of the signal detection transistor 34 is connected to the second electrode 15c. The drain of the signal detection transistor 34 is connected to the power supply wiring 22 as a source follower power supply, and the source is connected to the vertical signal line 18. The signal detection transistor 34 and the load circuit 19 not shown in FIG. 2 constitute a source follower circuit.

In this example, an address transistor 40 is connected between the source of the signal detection transistor 34 and the vertical signal line 18. The gate of the address transistor 40 is connected to the address signal line 30. When the signal charge is accumulated in the charge accumulation node 44, a voltage corresponding to the amount of the accumulated signal charge is applied to the gate of the signal detection transistor 34. The signal detection transistor 34 amplifies the voltage. By turning on the address transistor 40, the voltage amplified by the signal detection transistor 34 is selectively read out as a signal voltage.

In the structure illustrated in FIG. 2 , one of the electrodes of the first capacitor 41 is connected to the sensitivity adjustment line 32. Typically, when the imaging device 100 is in operation, the potential of the sensitivity adjustment line 32 is fixed to a certain potential such as 0 V. The sensitivity adjustment line 32 can be used to control the potential of the charge storage node 44. The other of the electrodes of the first capacitor 41 is connected to one of the electrodes of the second capacitor 42. Hereinafter, the node including the connection point between the first capacitor 41 and the second capacitor 42 is sometimes referred to as a reset drain node 46.

The other of the electrodes of the second capacitor 42 is connected to the charge storage node 44. That is, the electrode of the second capacitor 42 that is not connected to the reset drain node 46 is electrically connected to the second electrode 15c of the photoelectric conversion unit 15. In this example, the reset transistor 36 is connected to the second capacitor 42 in parallel.

In the structure illustrated in FIG2 , the pixel 10A includes a feedback transistor 38. As shown in the figure, one of the source and drain of the feedback transistor 38 is connected to the reset drain node 46. The other of the source and drain of the feedback transistor 38 is connected to the feedback line 25. The gate of the feedback transistor 38 is connected to the feedback control line 28.

(Device Structure of Pixel 10A)

Next, an example of a device structure of the pixel 10A will be described with reference to FIGS. 3 to 12 .

Fig. 3 schematically shows a cross section of a pixel 10A included in the imaging device 100. Fig. 4 schematically shows an example of a layout of each element in the pixel 10A. Fig. 3 corresponds to a cross-sectional view taken along line III-III shown in Fig. 4 .

The imaging device 100 includes a semiconductor substrate 2. As the semiconductor substrate 2, for example, a silicon substrate can be used. The semiconductor substrate 2 is not limited to a substrate whose entirety is a semiconductor. The semiconductor substrate 2 may also be an insulating substrate having a semiconductor layer provided on the surface. Here, a p-type silicon substrate is exemplified as the semiconductor substrate 2.

Each pixel 10A includes a portion of a semiconductor substrate 2 and a photoelectric conversion unit 15. Each pixel 10A is electrically isolated from other pixels 10A by a component isolation region 2t formed on the semiconductor substrate 2. As shown in FIG. 3 , between the semiconductor substrate 2 and the photoelectric conversion unit 15, an interlayer insulating layer 4 covering the semiconductor substrate 2 is typically arranged. In this example, the interlayer insulating layer 4 has a structure in which insulating layers 4a, 4b, 4c, 4d, and 4e are stacked. The insulating layers 4a, 4b, 4c, 4d, and 4e are insulating layers formed of, for example, silicon dioxide. In this example, the photoelectric conversion unit 15 is located on the insulating layer 4e farthest from the semiconductor substrate 2.

Impurity regions 2a, 2b, and 2c are formed on the semiconductor substrate 2. Impurity regions 2a, 2b, and 2c are typically N-type diffusion regions. A gate insulating layer 36g and a gate electrode 36e of a reset transistor 36 are provided in a region between the impurity regions 2a and 2b on the semiconductor substrate 2. In addition, a gate insulating layer 38g and a gate electrode 38e of a feedback transistor 38 are provided in a region between the impurity regions 2b and 2c on the semiconductor substrate 2. The impurity region 2a functions as one of the drain region and the source region of the reset transistor 36, and the impurity region 2b functions as the other of the drain region and the source region of the reset transistor 36. In this example, the reset transistor 36 and the feedback transistor 38 are electrically connected to each other by sharing the impurity region 2b. The impurity region 2a corresponds to the first impurity region in the present disclosure, and the impurity region 2b corresponds to the second impurity region in the present disclosure.

The impurity region 2c of the semiconductor substrate 2 functions as one of the drain region and the source region of the feedback transistor 38. The impurity region 2c is connected to a feedback line 25 spanning a plurality of pixels 10A via a plug disposed in the interlayer insulating layer 4. As will be described in detail later with reference to the drawings, the feedback line 25 is a signal line extending outside the pixel region.

In the structure illustrated in FIG3 , the portion of the feedback line 25 located in the pixel 10A of interest is a portion of the wiring layer 52 located between the second electrode 15c of the photoelectric conversion unit 15 and the semiconductor substrate 2. In addition, in this example, the wiring layer 52 also includes the portion of the vertical signal line 18 located in the pixel 10A of interest. That is, in this example, in the pixel 10A, the vertical signal line 18 also belongs to the same layer as the feedback line 25. The vertical signal line 18 is also a signal line extending outside the pixel region, similarly to the feedback line 25.

FIG. 5 shows the relationship between the pixel 10A and the various signal lines connected to the pixel 10A. As described above, a plurality of pixels 10A form a pixel region 240. For simplicity, four of the plurality of pixels 10A are taken out and represented in FIG. 5, but in reality, the pixel region 240 may be arranged in a matrix, for example, 300,000 pixels 10A may be arranged if it is a VGA standard, and about 36 million pixels 10A may be arranged if it is 8K. Here, the pixel region 240 may be defined as a region having a repeated structure of a plurality of units each having a signal detection transistor 34. The above-mentioned peripheral circuit is arranged in the peripheral region outside the pixel region 240.

As shown in the figure, the power wiring 22, the feedback line 25 and the vertical signal line 18 extend in the up-down direction in FIG. 5, that is, in the column direction of the plurality of pixels 10A. Each of the feedback lines 25 and each of the vertical signal lines 18 provided in each column of the plurality of pixels 10A has a connection with each of the two pixels 10A arranged along the column direction. On the other hand, the reset signal line 26, the feedback control line 28 and the address signal line 30 typically extend in the row direction of the plurality of pixels 10A. These signal lines are connected to each of the two pixels 10A arranged along the row direction. Similarly, the sensitivity adjustment line 32 also extends in the column direction or the row direction of the plurality of pixels 10A, and they are each connected to each of the two pixels 10A arranged along the column direction, or to each of the two pixels 10A arranged along the row direction.

The vertical signal line 18, the power supply wiring 22, the feedback line 25, the reset signal line 26, the feedback control line 28, the address signal line 30, and the sensitivity adjustment line 32 are all signal lines arranged in a manner that crosses the plurality of pixels 10A. The wiring layer 52 described above includes a portion of at least one of these signal lines. The wiring layer 52 may also include a portion of the feedback control line 28 or a portion of the address signal line 30 as a control line for driving more than two pixels, instead of a portion of the feedback line 25 and a portion of the vertical signal line 18 as an output line for reading signals from more than two pixels. The feedback control line 28, the feedback line 25, the reset signal line 26, the address signal line 30, and the sensitivity adjustment line 32 are respectively equivalent to the control lines in the present disclosure. The power supply wiring 22 is equivalent to the power supply line in the present disclosure. The vertical signal line 18 is equivalent to the output line in the present disclosure.

Referring to FIG. 3 again, a gate insulating layer 34g and a gate electrode 34e of the signal detection transistor 34 are also provided on the main surface of the semiconductor substrate 2. Referring to FIG. 4, it can be seen that the drain region and the source region of the signal detection transistor 34 are located near the front side and the back side of the paper surface of FIG. 3, respectively. In addition, in this example, the group of the reset transistor 36 and the feedback transistor 38 and the group of the signal detection transistor 34 and the address transistor 40 are separated by the element separation region 2t. The element separation region 2t can be formed, for example, by performing acceptor ion implantation based on predetermined implantation conditions.

Each pixel 10A has a connection portion 50 electrically connecting the impurity region 2a of the semiconductor substrate 2 and the second electrode 15c of the photoelectric conversion unit 15 in the interlayer insulating layer 4. The impurity region 2a functions as at least a part of a charge storage region for storing signal charges generated by the photoelectric conversion unit 15.

The connection portion 50 includes, in a part thereof, a polysilicon plug 210 having one end connected to the impurity region 2a of the semiconductor substrate 2, a polysilicon plug 212 having one end connected to the gate electrode 34e of the signal detection transistor 34, and a wiring 50a connecting the polysilicon plugs 210 and 212 to each other, and electrically connects the impurity region 2a and the gate electrode 34e to each other. That is, the impurity region 2a functioning as the drain region or the source region of the reset transistor 36 and the gate electrode 34e of the signal detection transistor 34 are electrically connected to the second electrode 15c of the photoelectric conversion portion 15 via the connection portion 50. The wiring 50a may be a part of a polysilicon layer that is given conductivity by doping with impurities.

The portion of the connection portion 50 between the wiring 50a and the second electrode 15c is typically formed of a metal such as copper. Therefore, the wiring layer 52 may also be a layer including wiring formed of a metal such as copper. The number of wiring layers arranged in the interlayer insulating layer 4 and the number of insulating layers in the interlayer insulating layer 4 are not limited to the number of layers illustrated in FIG. 3 and can be set arbitrarily.

The photoelectric conversion part 15 supported by the semiconductor substrate 2 includes a first electrode 15a, a photoelectric conversion layer 15b, and a second electrode 15c. The photoelectric conversion part 15 typically has a structure in which a photoelectric conversion layer 15b is sandwiched between the first electrode 15a and the second electrode 15c.

The first electrode 15a of the photoelectric conversion unit 15 is provided on the side where light from the subject arrives, in other words, on the light receiving surface 15h side of the photoelectric conversion layer 15b. The first electrode 15a is formed of a transparent conductive material such as indium tin oxide (ITO). The first electrode 15a may be formed directly on the photoelectric conversion layer 15b, or another layer may be arranged between the first electrode 15a and the photoelectric conversion layer 15b.

The photoelectric conversion layer 15b is formed of an organic material or an inorganic material such as amorphous silicon. The photoelectric conversion layer 15b may include a layer composed of an organic material and a layer composed of an inorganic material.

The second electrode 15c is located closer to the semiconductor substrate 2 than the first electrode 15a and the photoelectric conversion layer 15b, and is electrically separated from the second electrode 15c of other adjacent pixels 10A by being spatially separated. The second electrode 15c collects the charge generated by photoelectric conversion in the photoelectric conversion layer 15b. The second electrode 15c is formed of a metal such as aluminum or copper, a metal nitride, or polysilicon that is given conductivity by doping with impurities.

The first electrode 15a and the photoelectric conversion layer 15b are typically formed across a plurality of pixels 10A. However, at least one of the first electrode 15a and the photoelectric conversion layer 15b may be spatially separated from each other between the plurality of pixels 10A, similarly to the second electrode 15c.

In the present embodiment, the first capacitor 41 is located between the semiconductor substrate 2 and a wiring layer including at least a portion of the signal line connected to two or more pixels, among the wiring layers arranged in the interlayer insulating layer 4. In the structure illustrated in FIG3 , the first capacitor 41 is located between the semiconductor substrate 2 and a wiring layer 52 including a portion of the vertical signal line 18 and a portion of the feedback line 25. In other words, in the present embodiment, the first capacitor 41 is located closer to the semiconductor substrate 2 than the wiring layer including a portion of the signal line connected to two or more pixels.

The first capacitor element 41 has an upper electrode 41a, a lower electrode 41c, and a dielectric layer 41b disposed between the upper electrode 41a and the lower electrode 41c. In this example, in the cross-sectional view, the upper electrode 41a is located between the wiring layer 52 and the semiconductor substrate 2, and the lower electrode 41c is located between the upper electrode 41a and the semiconductor substrate 2. In addition, the terms "upper" and "lower" in this specification are used to indicate the relative configuration between components, and are not intended to limit the posture of the camera device disclosed in the present invention. The same applies to the terms "above" and "below" in this specification. The upper electrode 41a is equivalent to the third electrode in the present disclosure, and the lower electrode 41c is equivalent to the fourth electrode in the present disclosure.

The upper electrode 41a and/or the lower electrode 41c of the first capacitor 41 may be a part of a wiring layer located between the second electrode 15c of the photoelectric conversion unit 15 and the gate electrode 34e of the signal detection transistor 34. The upper electrode 41a is connected to the sensitivity adjustment line 32 not shown in FIG3. The lower electrode 41c is developed in a plane perpendicular to the normal direction of the semiconductor substrate 2 and is connected to the impurity region 2b via a through hole, a plug, etc. in the interlayer insulating layer 4.

In the structure illustrated in FIG. 3 , at least a portion of the upper electrode 41a of the first capacitor 41 is located above the impurity region 2a. Thus, in the present embodiment, when viewed along the normal direction of the semiconductor substrate 2, for example, the upper electrode 41a has a shape that covers a portion or the entirety of the impurity region 2a constituting at least a portion of the charge storage region. The upper electrode 41a and the lower electrode 41c may be, for example, metal electrodes or metal nitride electrodes. That is, the first capacitor 41 may have a "MIM (Metal-Insulator-Metal) structure" in which a dielectric is sandwiched between two electrodes formed of a metal or a metal compound. By adopting, for example, a MIM structure, the upper electrode 41a and/or the lower electrode 41c function as a light shielding layer, and the light incident on the pixel 10A may be suppressed from entering the impurity region 2a.

As already described, each pixel 10A collects the signal charge generated by the light incident on the photoelectric conversion layer 15b via the first electrode 15a of the photoelectric conversion unit 15 using the second electrode 15c, and accumulates the collected signal charge in the charge accumulation region. However, a part of the irradiated light may not be absorbed by the photoelectric conversion layer 15b and pass through the photoelectric conversion layer 15b. In addition, as described above, there may be a gap between two adjacent second electrodes 15c. Therefore, the light incident on the photoelectric conversion unit 15 and passing through the gap between the second electrodes 15c is repeatedly reflected randomly between the photoelectric conversion unit 15 and the semiconductor substrate 2, for example, sometimes reaching the impurity region 2a. In addition, in this specification, for the convenience of explanation, the light that passes through the photoelectric conversion unit 15 and reaches the impurity region of the semiconductor substrate 2 is sometimes referred to as "stray light".

If such light is incident on the impurity region 2a, charges are generated in the impurity region 2a by photoelectric conversion. As described with reference to FIG. 3 , the gate electrode 34e of the signal detection transistor 34 is connected to the impurity region 2a through the connection portion 50, and the signal detection transistor 34 amplifies and outputs a signal corresponding to the amount of charge accumulated in the impurity region 2a. Therefore, the excess charge generated in the impurity region 2a due to stray light becomes the cause of the generation of a false signal. In other words, the incident light on the impurity region 2a results in the addition of noise to the original signal, resulting in a decrease in image quality.

6 shows an example of the arrangement relationship among the wiring layer 52 , the upper electrode 41 a , and the impurity region 2 a when the photoelectric conversion part 15 is removed from the pixel 10A and the pixels are viewed from the normal direction of the semiconductor substrate 2 .

6 , the wiring layer 52 includes a portion of the vertical signal line 18 and a portion of the feedback line 25 extending in the column direction, and a wiring 52a connected to the connection portion 50. The wiring 52a is a portion of the wiring layer 52 located at the same layer as the vertical signal line 18 and the feedback line 25, and constitutes a portion of the connection portion 50.

In this example, the impurity region 2a constituting a part of the charge storage region is located at a position overlapping with the wiring 52a in a plan view. In particular, in this example, the entire impurity region 2a is covered by the wiring 52a. The shapes of the wiring 52a, a part of the vertical signal line 18, and a part of the feedback line 25 shown in FIG. 6 are merely illustrative. A part of the vertical signal line 18 or a part of the feedback line 25 may have a shape that covers the entire impurity region 2a. In this way, the wiring layer 52 may cover the entire impurity region 2a.

As shown in FIG. 6 , according to the present embodiment, since at least a portion of the upper electrode 41a of the first capacitor 41 overlaps with the impurity region 2a in a plan view, the upper electrode 41a can be used as a light-shielding electrode, and the incidence of light on the impurity region 2a can be suppressed. Since the incidence of light on the impurity region 2a is suppressed, the occurrence of false signals can be prevented. The suppression of stray light contributes to improving the reliability of the imaging device 100.

In the example shown in FIG. 3 , at least a portion of the lower electrode 41c is also located above the impurity region 2a. That is, the lower electrode 41c may also have a shape that covers the entire impurity region 2a when viewed along the normal direction of the semiconductor substrate 2. Since the lower electrode 41c has a shape that covers a portion or the entire impurity region 2a when viewed from above, the lower electrode 41c functions as a light shielding layer, and the incidence of light on the impurity region 2a can be suppressed. In addition, in this example, at least a portion of the upper electrode 41a and at least a portion of the lower electrode 41c both cover the impurity region 2a when viewed from above. However, it is not necessary for both the upper electrode 41a and the lower electrode 41c to cover the impurity region 2a when viewed from above. As long as at least one of the upper electrode 41a and the lower electrode 41c has a shape that covers the impurity region 2a when viewed from the normal direction of the semiconductor substrate 2, the effect of preventing the occurrence of false signals can be expected.

In addition, in the example shown in FIG. 3 , the first capacitor element 41 is arranged between the wiring layer 52 including a portion of the vertical signal line 18 and the semiconductor substrate 2. In other words, in this example, the first capacitor element 41 is located closer to the semiconductor substrate 2 than the wiring layer including a portion of the signal line spanning more than two pixels. Therefore, the light shielding effect at a position closer to the semiconductor substrate 2 can be obtained, and a high light shielding effect can be exerted for stray light that travels obliquely with respect to the normal direction of the semiconductor substrate 2. Therefore, it is possible to more effectively prevent the degradation of image quality caused by parasitic sensitivity caused by stray light.

Examples of materials used to form the upper electrode 41a are Ti, TiN, Ta, TaN, and Mo. The lower electrode 41c may be formed of the same material in a shape in which at least a portion overlaps with the impurity region 2a when viewed from above, and the lower electrode 41c may be used as a light-shielding electrode. The upper electrode 41a and the lower electrode 41c may have a thickness in the range of about 10 nm to about 100 nm. The thickness of the upper electrode 41a and the lower electrode 41c may also be in the range of about 30 nm to about 100 nm. The thickness of the upper electrode 41a and the lower electrode 41c may be appropriately set according to the materials that constitute them. For example, by forming a TaN electrode with a thickness of about 100 nm as the upper electrode 41a, sufficient light-shielding properties can be achieved in the upper electrode 41a. The same is true for the lower electrode 41c.

Furthermore, in the structure illustrated in FIG3 , the upper electrode 41a has a shape that also covers the impurity region 2b when viewed along the normal direction of the semiconductor substrate 2. With such a structure, it is possible to suppress the light that has entered the photoelectric conversion unit 15 and passed through the gap between the second electrodes 15c from entering the impurity region 2b. That is, it is possible to suppress the generation of charges caused by photoelectric conversion in the impurity region 2b.

Since the impurity region 2b constitutes a part of the reset drain node 46, if charges are generated in the impurity region 2b by photoelectric conversion, the potential of the reset drain node 46 changes. Referring to FIG. 2 , it can be seen that the charge storage node 44 is electrically coupled to the reset drain node 46 via the second capacitor 42. Therefore, if the potential of the reset drain node 46 changes due to the generation of charges, the potential of the charge storage node 44 may change along with the change in the potential of the reset drain node 46. That is, noise may be mixed due to the incidence of light on the impurity region 2b.

As shown in FIG. 3 , by making the shape of the upper electrode 41a such that it covers the impurity region 2b when viewed from above, the mixing of noise caused by the incidence of light on the impurity region 2b can be suppressed. If the shape of the lower electrode 41c is made to cover the impurity region 2b when viewed from above instead of the upper electrode 41a, the same effect can be obtained. Alternatively, as shown in FIG. 3 , both the upper electrode 41a and the lower electrode 41c can be made to cover the impurity region 2b when viewed from above. In addition, FIG. 3 shows a structure in which the upper electrode 41a has a larger area than the lower electrode 41c when viewed from the normal direction of the semiconductor substrate 2. However, it is not necessary for the area of the upper electrode 41a to be larger than the lower electrode 41c when viewed from the normal direction of the semiconductor substrate 2. The area of the upper electrode 41a may be smaller than the area of the lower electrode 41c.

In the structure illustrated in FIG3 , a through hole 220 electrically connected to the impurity region 2b is formed on the lower surface 41d of the lower electrode 41c. In addition, the dielectric layer 41b covers the surface of the lower electrode 41c other than the lower surface 41d. The upper electrode 41a covers the upper surface 41e of the lower electrode 41c and the side surface connecting the upper surface 41e and the lower surface 41d.

When the imaging device 100 is in operation, a predetermined voltage is supplied to the upper electrode 41a via the sensitivity adjustment line 32 (not shown in FIG. 3 ). Typically, the potential of the upper electrode 41a is fixed to a certain value by being supplied with the predetermined voltage. By fixing the potential of the upper electrode 41a to a certain value, for example, the upper electrode 41a can function as a shielding electrode, and the effect of reducing the mixing of noise caused by electrical coupling into the lower electrode 41c can be obtained. In addition, by adjusting the voltage supplied to the upper electrode 41a via the sensitivity adjustment line 32, the sensitivity of the imaging device 100 can also be adjusted.

As in this example, by providing a contact for electrical connection with the impurity region 2b on the lower surface 41d side of the lower electrode 41c and covering the upper portion of the lower electrode 41c with the upper electrode 41a, electrical coupling between the lower electrode 41c and other electrodes and/or wiring can be suppressed. For example, a wiring layer such as the wiring layer 52 may be arranged between the upper electrode 41a and the photoelectric conversion part 15 as shown in FIG3 . By covering the upper portion of the lower electrode 41c with the upper electrode 41a to sandwich the upper electrode 41a as shown in FIG3 , electrical coupling between the lower electrode 41c and the wiring layer above the upper electrode 41a, such as the wiring layer 52, can be suppressed.

Furthermore, in this example, not only the upper surface 41e of the lower electrode 41c, but also the side surface connecting the upper surface 41e and the lower surface 41d is covered by the upper electrode 41a, so the electrostatic shielding effect on the lower electrode 41c is improved, and the electrical coupling between the lower electrode 41c and other electrodes and/or wiring can be more effectively suppressed. By connecting the through hole 220 to the lower surface 41d of the lower electrode 41c, the complexity of the wiring is also avoided.

In addition, the terms "upper surface" and "lower surface" in this specification are used to distinguish the main surfaces of the layer-shaped or plate-shaped components in the pixel, and are not used with the intention of limiting the posture of the camera device disclosed in this specification. In this specification, the "upper surface" refers to the main surface of the two main surfaces of the layer of interest that is closer to the photoelectric conversion unit 15 than the semiconductor substrate 2. The "lower surface" refers to the main surface of the two main surfaces of the layer of interest that is closer to the semiconductor substrate 2 than the photoelectric conversion unit 15, that is, it refers to the main surface on the opposite side of the "upper surface".

By configuring the first capacitor 41 in the interlayer insulating layer 4, physical interference with the gate electrode of the transistor such as the reset transistor 36 can be avoided. Therefore, compared with the case where the first capacitor 41 is configured on the main surface of the semiconductor substrate 2, the degree of freedom in the design of the electrode shape of the upper electrode 41a and the lower electrode 41c is improved, and it is easy to ensure a larger electrode area. Furthermore, the range of selection of the material in the upper electrode 41a, the dielectric layer 41b and the lower electrode 41c is expanded, and it is easy to form the first capacitor 41 with a larger capacitance value in the pixel. As described later, by increasing the capacitance value of the first capacitor 41, a higher noise reduction effect can be obtained in noise elimination using negative feedback.

On the other hand, about the second capacitor element 42, as described later, from the viewpoint of obtaining higher noise reduction effect in the noise elimination utilizing negative feedback, it is advantageous that the capacitance value is smaller. In the structure illustrated in Fig. 3, the second capacitor element 42 is composed of a part of the lower electrode 41c, a part of the wiring 50a and the part sandwiched between them in the insulating layer 4b. The wiring 50a of the connecting portion 50, for example, has a part extending in a plane perpendicular to the normal direction of the semiconductor substrate 2 and opposed to the lower electrode 41c of the first capacitor element 41. According to the shape and configuration of such electrodes and wiring, a capacitance can be formed between a part of the lower electrode 41c and a part of the wiring 50a, and this capacitance is utilized as the second capacitor element 42.

As described above, by adopting a design in which the first capacitor element 41 is located in the interlayer insulating layer 4, the range of choice of materials in the dielectric layer 41b is expanded. For example, the dielectric layer 41b can be formed using a material different from the material constituting the interlayer insulating layer 4. For example, the dielectric layer 41b can be formed from a metal oxide or a metal nitride. Examples of materials used to form the dielectric layer 41b include oxides or nitrides containing one or more selected from the group consisting of Zr, Al, La, Ba, Ta, Ti, Bi, Sr, Si, Y and Hf. The material used to form the dielectric layer 41b can be either a binary compound, a ternary compound or a quaternary compound.

For example, atomic layer deposition (ALD) can be applied to the formation of the dielectric layer 41b. According to ALD, different atoms can be stacked one atom at a time. Specifically, raw material compound molecules as precursors are introduced into a vacuum container in which a substrate is arranged. The introduced precursor is adsorbed on the surface of the substrate in the vacuum container. Then, a film of one layer of atoms is formed by leaving only the desired atoms in the precursor by chemical reaction.

Here, a film of Hf oxide is used as the dielectric layer 41b of the first capacitor element 41. In the formation of the film of Hf oxide, tetrakis(ethylmethylamino)hafnium is used as a precursor, and plasma discharge is performed after the introduction of the precursor. By performing plasma discharge in an oxygen environment, the oxidation of Hf is promoted. By repeatedly performing the above-mentioned process, _HfO2 is stacked layer by layer. For example, by repeatedly introducing a gaseous precursor and plasma discharge 250 times, a film with a thickness of 22nm is formed as the dielectric layer 41b. The dielectric layer 41b may also include more than two films formed by different materials. By forming the dielectric layer 41b into a stacked film of more than two layers, a dielectric layer that takes advantage of the materials constituting each layer can be obtained.

In the structure illustrated in FIG3 , the first capacitor element 41 has, for example, an opening 230 in the center thereof. That is, in this example, openings are provided on the upper electrode 41a, the dielectric layer 41b, and the lower electrode 41c. For example, regarding the dielectric layer 41b, by using photolithography introduced in a common semiconductor process, a film of an oxide such as Hf can be left in a desired region to form the dielectric layer 41b having an opening.

In addition, by exposing dielectric layer 41b to plasma or radicals for ashing, dielectric layer 41b is sometimes damaged in the process of removing resist. In addition, dielectric layer 41b is sometimes exposed to the resist stripping solution for the removal of resist residue. If dielectric layer 41b is damaged, the leakage current between upper electrode 41a and lower electrode 41c may increase. In the structure illustrated in Fig. 3, due to forming electrical coupling between lower electrode 41c of the first capacitor element 41 and wiring 50a of connecting portion 50, if leakage current occurs between upper electrode 41a and lower electrode 41c of the first capacitor element 41, the noise caused by leakage current may be mixed in the output signal.

For example, by providing a protective layer on the upper surface of the dielectric layer 41b, damage to the dielectric layer 41b caused by the removal of the resist can be suppressed. As a material for forming the protective layer, it is sufficient to select a metal such as Cu, Al, or a material having a relatively high conductivity such as polysilicon. By using a material having a relatively high conductivity as the material of the protective layer, it is possible to avoid a decrease in the capacitance value in the first capacitor 41 caused by sandwiching the protective layer between the upper electrode 41a and the lower electrode 41c.

As described above, the connection portion 50 is a structure that connects the impurity region 2a in the semiconductor substrate 2 to the second electrode 15c of the photoelectric conversion portion 15. Here, the connection portion 50 penetrates the first capacitor 41 at the position of the opening 230 of the first capacitor 41 provided in the interlayer insulating layer 4, and electrically connects the impurity region 2a and the second electrode 15c to each other.

(Effect of Providing the Opening 230 in the First Capacitor Element 41)

FIG. 7 shows an example of the configuration of the connecting portion 50 relative to the first capacitor element 41. In the structure illustrated in FIG. 7, the first capacitor element 41 of each pixel 10A surrounds the connecting portion 50. In this example, the outer shapes of the upper electrode 41a and the opening 230 when viewed from the normal direction of the semiconductor substrate 2 are both rectangular. It goes without saying that the outer shapes of the upper electrode 41a and the opening 230 when viewed from above are not limited to the shapes shown in FIG. 7, and any shape can be adopted. In addition, the shape of the upper electrode 41a and the shape of the lower electrode 41c do not need to be consistent when viewed from above. As long as the upper electrode 41a includes a portion that is opposite to at least a portion of the lower electrode 41c. The shape of the dielectric layer 41b when viewed from the normal direction of the semiconductor substrate 2 can also be set arbitrarily. The dielectric layer 41b can be either a continuous single layer or a plurality of portions arranged at different locations in the same layer.

As illustrated in FIG. 7 , the connection portion 50 may have a configuration such that the first capacitor element 41 is penetrated at the position of the opening 230 provided on the first capacitor element 41. By configuring the connection portion 50 in the opening 230, it is easy to expand the electrode area of the first capacitor element 41 and obtain a larger capacitance value compared to the case where the connection portion 50 is configured between the first capacitor elements 41 of mutually adjacent pixels 10A. This is because, if the connection portion 50 is configured between adjacent pixels 10A and the impurity region 2a of the semiconductor substrate 2 is connected to the photoelectric conversion portion 15, it is necessary to expand the interval between the adjacent first capacitor elements 41, and it is difficult to expand the electrode area of the first capacitor element 41.

The first capacitor element 41 may also have more than two openings. However, in the case where the pixel 10A has a connection portion other than the connection portion 50, such as a through hole that connects a wiring layer located below the first capacitor element 41 to a wiring layer located above the first capacitor element 41, these connection portions may be arranged in an opening other than the opening 230 through which the connection portion 50 passes. By arranging the connection portion other than the connection portion 50 in an opening different from the opening 230, the electrical coupling between the connection portion 50 and the connection portion other than the connection portion 50 can be suppressed by a portion of the first capacitor element 41 sandwiched therebetween, and the mixing of noise into the charge storage region can be suppressed.

Furthermore, by providing the opening 230 in the first capacitor element 41 , it is possible to expect effects such as improvement in yield and suppression of shadows. This will be described below.

FIG8 shows an example of a chip 110 having a pixel region 240 including a plurality of pixels 10A. As described above, the pixel region 240 may include about 300,000 to 36 million pixels. In the example shown in FIG8 , the pixel region 240 is a region having a repeated structure with the pixel 10A as a unit. As shown in the figure, the chip 110 further has a peripheral region 242 in which no pixels 10A are arranged on the periphery of the pixel region 240 and on the outside. The peripheral region 242 may be a region on the semiconductor substrate 2 described above.

9 and 10 show a part of the manufacturing process of a pixel including an MIM structure without an opening in an interlayer insulating layer as a reference example. When a capacitor having an MIM structure is arranged in an interlayer insulating layer, as shown in FIG9 , for example, after forming an MIM structure 41r on an insulating layer 400, an insulating layer 402 covering the MIM structure 41r is formed. Here, no opening is provided in the MIM structure 41r.

The thickness of the MIM structure 41r, that is, the distance from the lower surface of the lower electrode of the MIM structure 41r to the upper surface of the upper electrode can be, for example, in the range of about 30 nm to about 150 nm. In correspondence with the MIM structure 41r being arranged on the region 410 where the pixel region 240 is to be formed, a step is generated on the upper surface of the insulating layer 402 between the region 420 and the region 410 which should be the peripheral region 242. The size of the step, that is, the difference in height between the portion on the upper surface of the insulating layer 402 located on the region 410 and the portion on the region 420, can be in the range of about 30 nm to about 150 nm, corresponding to the thickness of the MIM structure 41r.

After the formation of the insulating layer 402, the upper surface of the insulating layer 402 is flattened by chemical mechanical polishing (CMP), etch back, etc. However, when no opening is provided in the MIM structure, sometimes the step on the upper surface of the insulating layer 402 cannot be sufficiently reduced by the flattening process. If the step on the upper surface of the insulating layer 402 is relatively large, focus deviation occurs in the photolithography when forming a wiring pattern on the insulating layer 402, and the desired pattern cannot be formed, or even if the camera device is finally obtained, a shadow occurs in the acquired image. In other words, there is a case where the yield is reduced.

11 and 12 show a part of the manufacturing process of a pixel using the MIM structure 41q having the opening 230 as the first capacitor element 41. It is assumed here that the total area occupied by the MIM structure 41q in the entire pixel region 240 is equal to the total area occupied by the MIM structure 41r in the entire pixel region 240 in a plan view.

In the case where the opening 230 is provided in the first capacitor element 41, as schematically shown in FIG. 11, a plurality of protrusions 41p having shoulders 430 are formed in the portion on the region 410 of the upper surface of the insulating layer 4c covering the MIM structure 41q on the insulating layer 4b. Since the upper surface of the insulating layer 4c has a plurality of shoulders 430, in the process of flattening the insulating layer 4c, the removal rate of the portion on the upper surface of the insulating layer 4c located on the region 410 is increased compared with the flat portion on the region 420. As a result, as schematically shown in FIG. 12, the step on the upper surface of the insulating layer 4c is easily alleviated, and the occurrence of focus deviation, shadows, and other undesirable conditions in the subsequent photolithography can be suppressed. FIG. 12 schematically shows the state after the flattening process is performed, and for comparison, the position of the upper surface of the insulating layer 402 shown in FIG. 10 is indicated by a double-dashed line in the figure.

Thus, by providing the opening 230 in the first capacitor element 41, the step between the area to be the pixel area and the area to be the peripheral area on the upper surface of the insulating layer covering the first capacitor element 41 can be alleviated. In other words, the formation of the opening 230 to the first capacitor element 41 contributes to improving the flatness of the insulating layer covering the first capacitor element 41.

When the radius of a circle having an area equal to the opening area of the opening 230 in a top view is d, and the thickness of the first capacitor element 41, that is, the distance from the lower surface of the lower electrode 41c to the upper surface of the upper electrode 41a is h, (d/h) can be 1.4 or more. By providing the opening 230 on the first capacitor element 41, the flatness of the upper surface of the insulating layer covering the first capacitor element 41 is improved, so it is possible to more reliably form a wiring pattern above the insulating layer. Thus, the yield rate can be improved. In addition, by reducing the step of the interlayer insulating layer between the pixel area 240 and the peripheral area 242 of the camera device, the decline in image quality caused by shadows can be prevented.

(Noise cancellation using negative feedback)

Here, the outline of noise elimination using negative feedback is described with reference to FIG. 2. The exemplary noise elimination operation of which the outline is described below is performed, for example, before and after the start of photography, following a so-called electronic shutter that resets the signal charge in the charge accumulation region. The noise elimination operation is typically performed after the pixel signal is read out after the end of the exposure period, and after the signal charge accumulated during the exposure period is reset.

The reset of the signal charge after the end of the exposure period is performed as follows: First, exposure is performed with the reset transistor 36, the feedback transistor 38, and the address transistor 40 turned off, and after the end of the exposure period, the address transistor 40 is turned on to read out the signal corresponding to the signal charge accumulated during the exposure period.

Then, the reset transistor 36 and the feedback transistor 38 are turned on by controlling the potential of the reset signal line 26 and the feedback control line 28. As a result, the charge storage node 44 and the feedback line 25 are connected via the reset transistor 36 and the feedback transistor 38, forming a feedback loop. The formation of the feedback loop is sequentially performed for each of the plurality of pixels 10A sharing the feedback line 25.

By forming a feedback loop, the output of the signal detection transistor 34 is negatively fed back. Here, the feedback circuit 202 can be said to be a negative feedback amplifier circuit including the signal detection transistor 34, the inverting amplifier 24 and the feedback transistor 38. The feedback transistor 38 is equivalent to the third transistor in the present disclosure. By negatively feeding back the output of the signal detection transistor 34, the potential of the charge accumulation node 44 converges to a potential such that the voltage of the vertical signal line 18 is equal to Vref. In other words, the potential of the charge accumulation node 44 is reset. It can also be said that the signal charge is reset.

In this example, the voltage Vref applied to the positive input terminal of the inverting amplifier 24 corresponds to the reference voltage during resetting. The specific value of the voltage Vref can be arbitrarily set within the range of the power supply voltage and the ground, that is, 0 V. The power supply voltage is 3.3 V, for example.

Next, the reset transistor 36 is turned off. KTC noise is generated by turning off the reset transistor 36. Therefore, the kTC noise accompanying the turning off of the reset transistor 36 is added to the voltage of the charge storage node 44 after reset. After the reset transistor 36 is turned off, the kTC noise is eliminated as follows.

As can be seen from FIG. 2 , the feedback loop is formed while the feedback transistor 38 is turned on. Therefore, if the gain of the feedback circuit 202 is A, the kTC noise generated by turning off the reset transistor 36 is reduced to a magnitude of 1/(1+A). In addition, in this example, the voltage of the vertical signal line 18 immediately before the reset transistor 36 is turned off, in other words, immediately before the noise elimination starts, is substantially equal to the voltage Vref applied to the positive input terminal of the inverting amplifier 24. By making the voltage of the vertical signal line 18 at the start of noise elimination close to the target voltage Vref after noise elimination, the kTC noise can be eliminated in a relatively short time.

Next, the feedback transistor 38 is turned off. As the feedback transistor 38 is turned off, kTC noise occurs. However, the magnitude of the kTC noise added to the voltage of the charge accumulation node 44 due to the closing of the feedback transistor 38 is (Cfd/C1) ^1/2 ×(C2/(C2+Cfd)) times as compared to the case where the first capacitor 41 and the second capacitor 42 are not provided in the pixel 10A and the feedback transistor 38 is directly connected to the charge accumulation node 44. In the above formula, Cfd, C1 and C2 respectively represent the capacitance value of the charge accumulation node 44, the capacitance value of the first capacitor 41 and the capacitance value of the second capacitor 42, and the "×" in the formula represents multiplication.

According to the above formula, the larger the capacitance value C1 of the first capacitor 41, the smaller the noise itself is, and the smaller the capacitance value C2 of the second capacitor 42, the greater the attenuation rate is. Therefore, by appropriately setting the capacitance value C1 of the first capacitor 41 and the capacitance value C2 of the second capacitor 42, the kTC noise generated by turning off the feedback transistor 38 can be sufficiently reduced.

After the feedback transistor 38 is turned off, the signal from which the kTC noise has been eliminated is read. The level of the signal obtained at this time is equivalent to the signal level in the dark. In addition, since the time required for reading the reset voltage is short, the signal after noise elimination can also be read while the address transistor 40 is kept turned on. By taking the difference between the signal read after exposure and before the start of reset and the signal read at this time, a signal from which fixed noise has been eliminated can be obtained. In this way, a signal from which kTC noise and fixed noise have been eliminated can be obtained.

In addition, in the state where the reset transistor 36 and the feedback transistor 38 are turned off, the first capacitor 41 is connected to the charge accumulation node 44 via the second capacitor 42. Here, it is assumed that the charge accumulation node 44 is directly connected to the first capacitor 41 without the second capacitor 42. In this case, the capacitance value of the entire accumulation area of the signal charge when the first capacitor 41 is directly connected is (Cfd+C1). That is, if the first capacitor 41 has a relatively large capacitance value C1, the capacitance value of the entire accumulation area of the signal charge is also a relatively large value, so a higher conversion gain cannot be obtained. That is, it is difficult to obtain a higher SN ratio.

On the other hand, if the first capacitor 41 is connected to the charge accumulation node 44 via the second capacitor 42 as illustrated in FIG. 2 , the capacitance value of the overall signal charge accumulation region in such a structure is expressed as (Cfd+(C1C2)/(C1+C2)). Here, when the second capacitor 42 has a relatively small capacitance value C2 and the first capacitor 41 has a relatively large capacitance value C1, the capacitance value of the overall signal charge accumulation region is approximately (Cfd+C2). That is, the increase in the capacitance value of the overall signal charge accumulation region is small. In this way, by connecting the first capacitor 41 to the charge accumulation node 44 via the second capacitor 42 having a relatively small capacitance value, the decrease in conversion gain can be suppressed.

(Variation Example)

As described with reference to FIG. 3 , in order to electrically separate the second electrode 15 c of each pixel 10A, it is typically spatially separated from the second electrode 15 c of other adjacent pixels 10A. Therefore, there is usually a gap between the mutually adjacent second electrodes 15 c. Therefore, light passing through these gaps may be repeatedly and randomly reflected in the pixel 10A and reach the impurity region 2 a or the impurity region 2 b of the semiconductor substrate 2.

For example, by using a light-shielding electrode as the upper electrode 41a and/or the lower electrode 41c of the first capacitor 41, the electrode area of the first capacitor 41 in a top view is enlarged compared to the area of the second electrode 15c of the photoelectric conversion unit 15, and the gap between the pixels 10A can be reduced to reduce stray light. In particular, since the upper electrodes 41a are respectively configured to be supplied with a predetermined voltage via the sensitivity adjustment line 32, the distance between the adjacent upper electrodes 41a can be sufficiently reduced compared to the distance between the adjacent second electrodes 15c. However, with such a structure, light may also pass through the gap formed between the adjacent upper electrodes 41a, so it is difficult to completely remove stray light.

Fig. 13 and Fig. 14 show a modification of the imaging device 100. Fig. 14 is a schematic cross-sectional view corresponding to Fig. 13. As shown in Fig. 14, for example, the shield electrode 14 may be arranged in the same layer as the second electrode 15c of the photoelectric conversion part 15.

FIG13 shows an example of the arrangement of the upper electrode 41a, the second electrode 15c, and the shielding electrode 14 when the photoelectric conversion layer 15b and the first electrode 15a are removed from the pixel 10A and viewed from the normal direction of the semiconductor substrate 2. In the example shown in the figure, the shielding electrode 14 is formed in a grid shape including a plurality of portions extending along the boundary between the pixels 10A when viewed from above, and covers the gap between two adjacent upper electrodes 41a. By covering the gap between two adjacent upper electrodes 41a with the shielding electrode 14, it is possible to further reduce the incidence of light on the gap between two adjacent upper electrodes 41a and further reduce stray light.

In addition, the shielding electrode 14 is configured to be supplied with a certain voltage when the camera device 100 is in operation. Therefore, a gap for electrical insulation is provided between the second electrode 15c and the shielding electrode 14. Most of the light passing through the gap between the second electrode 15c and the shielding electrode 14 can be shielded by the upper electrode 41a or the lower electrode 41c of the first capacitor 41. A plurality of strip-shaped electrodes extending in the row direction across a plurality of columns can also be formed as the upper electrode 41a. In this case, since a gap between the upper electrodes 41a does not occur between the pixels 10A adjacent to each other along the row direction, stray light can be further reduced.

In addition, by providing a shielding electrode maintained at a constant potential between pixels, it is possible to prevent the charges generated by the photoelectric conversion layer 15b of a certain pixel from being collected by the second electrode 15c of other pixels different from the pixel. For example, charges generated near the boundary of a pixel and moving toward other pixel electrodes different from the pixel electrode to which they should be directed, such as pixel electrodes in adjacent pixels, can be collected by the shielding electrode 14. Thus, undesired charge movement to adjacent pixels is suppressed, and the occurrence of color mixing is reduced.

(Implementation Method 2)

Fig. 15 schematically shows a cross section of a pixel of an imaging device according to another embodiment of the present disclosure. The main difference between the above-mentioned pixel 10A and the pixel 10B shown in Fig. 15 is that the pixel 10B does not have the second capacitor 42, and the lower electrode 41c of the first capacitor 41 is connected to the connection portion 50 through the through hole 320 without passing through the reset transistor 36.

In the structure illustrated in FIG. 15 , the through hole 320 is located between the lower electrode 41c and the wiring 50a of the connecting portion 50, and one end thereof is connected to the lower surface 41d of the lower electrode 41c. Providing contacts on the lower surface 41d side of the lower electrode 41c and covering these points with the upper electrode 41a above the lower electrode 41c is the same as the above-mentioned embodiment. The through hole 320 connected to the connecting portion 50 can function as a part of the charge accumulation region. That is, by providing the through hole 320 between the lower electrode 41c and the connecting portion 50, the effect of increasing the capacitance value of the charge accumulation region can be obtained.

In the structure in which the lower electrode 41c of the first capacitor 41 is connected to the connecting portion 50 by the through hole 320, the greater the capacitance value of the first capacitor 41, the greater the maximum amount of charge that can be accumulated in the entire charge accumulation region. If the maximum amount of charge that can be accumulated in the entire charge accumulation region is large, it is advantageous for photography under high illumination.

In addition, by connecting the upper electrode 41a to the connection portion 50 and connecting the lower electrode 41c to the sensitivity adjustment line 32 not shown in FIG. 15 , the first capacitor 41 can be connected to the connection portion 50 without passing through the reset transistor 36. However, by connecting the lower electrode 41c to the connection portion 50 and covering the lower electrode 41c with the upper electrode 41a as shown in the structure of FIG. 15 , the electrical coupling between the wiring layer such as the wiring layer 52 disposed above the upper electrode 41a and the lower electrode 41c is suppressed, so that the effect of reducing noise can be expected more than the case where the upper electrode 41a is connected to the connection portion 50. By making the shape of the upper electrode 41a cover the side surface connecting the upper surface 41e and the lower surface 41d of the lower electrode 41c, the effect of reducing coupling can be further improved.

Fig. 16 is a diagram showing an exemplary circuit configuration of the pixel 10B shown in Fig. 15. As shown in Fig. 16, one of the drain and source of the reset transistor 36 is connected to the charge storage node 44, and the other is connected to the feedback line 25 without passing through the feedback transistor 38 in Embodiment 1. In addition, the electrode of the first capacitor 41 that is not connected to the sensitivity adjustment line 32 is connected to the charge storage node 44.

(Noise cancellation using negative feedback)

Next, the noise elimination operation in the circuit configuration illustrated in FIG16 will be described. Here, the feedback circuit 302 shown in FIG16 is a negative feedback amplifier circuit including a signal detection transistor 34, an inverting amplifier 24, and a reset transistor 36. As can be seen from the following description, the reset transistor 36 in the example described here can be said to also have the function of the feedback transistor 38 in the first embodiment.

For example, after the exposure period ends, the reset transistor 36 is turned on. By turning on the reset transistor 36, the charge storage node 44 and the feedback line 25 are connected via the reset transistor 36, forming a feedback loop for feeding back the signal of the photoelectric conversion unit 15. Here, the signal of the photoelectric conversion unit 15 is negatively fed back.

By electrically connecting the charge storage node 44 to the feedback line 25, the potential of the charge storage node 44 converges to a potential equal to Vref of the vertical signal line 18. In other words, the potential of the charge storage node 44 is reset.

Then, the reset transistor 36 is turned off to perform noise elimination. At this time, the potential of the reset signal line 26 is gradually dropped from a high level to a low level so as to cross the threshold voltage of the reset transistor 36 .

If the potential of the reset signal line 26 is gradually decreased from a high level to a low level, the reset transistor 36 gradually changes from an on state to an off state. During the period when the reset transistor 36 is on, the state in which the feedback loop is formed continues. At this time, as the voltage applied to the reset signal line 26 decreases, the resistance of the reset transistor 36 increases. If the resistance of the reset transistor 36 increases, the operating frequency band of the reset transistor 36 becomes narrower, and the frequency domain of the feedback signal becomes narrower.

If the voltage applied to the reset signal line 26 reaches a low level, the reset transistor 36 is turned off. That is, the formation of the feedback loop is eliminated. By turning off the reset transistor 36 when the operating frequency band of the reset transistor 36 is lower than the operating frequency band of the signal detection transistor 34, the kTC noise remaining in the charge storage node 44 can be reduced.

In this example, the voltage of the vertical signal line 18 immediately before the voltage applied to the reset signal line 26 changes to a low level, that is, immediately before the noise elimination starts, is made substantially equal to the voltage Vref applied to the non-inverting input terminal of the inverting amplifier 24. In this way, by making the voltage of the vertical signal line 18 at the start of noise elimination close to the target voltage Vref after the noise elimination, even if the control is such that the voltage applied to the reset signal line 26 is gradually decreased, the kTC noise can be eliminated in a relatively short time.

Furthermore, the signal detection transistor 34, reset transistor 36, address transistor 40 and feedback transistor 38 may be either N-channel MOSFET or P-channel MOSFET, and it is not necessary to make all of them N-channel MOSFET or P-channel MOSFET.

Description of symbols

2Semiconductor substrate

2a, 2b, 2c impurity regions

4 interlayer insulation layers

10, 10A, 10B pixels

15 Photoelectric conversion unit

15a 1st electrode

15b Photoelectric conversion layer

15c Second electrode

24 Inverting Amplifier

25 Feedback line

32 Sensitivity adjustment line

34 Signal detection transistor

36 Reset transistor

38 Feedback transistor

40 Address transistor

41 1st capacitor element

41a Upper electrode

41b Dielectric layer

41c Lower electrode

41d Lower surface

41e Upper surface

42 2nd capacitor element

44 Charge storage node

50 Connection

52 wiring layers

100 Camera Device

230 Opening

240 pixel area

242 Surrounding Areas

Claims (15)

1. A camera device, characterized in that: have: a pixel region, comprising a plurality of pixels; and A signal line is arranged across two or more pixels among the plurality of pixels and extends from the inside of the pixel area to the outside of the pixel area; The above-mentioned multiple pixels respectively include: Semiconductor substrates; A photoelectric conversion unit is supported by the semiconductor substrate and includes a first electrode, a second electrode disposed closer to the semiconductor substrate than the first electrode, and a photoelectric conversion layer disposed between the first electrode and the second electrode; A first transistor including a first impurity region disposed in the semiconductor substrate and a second impurity region disposed in the semiconductor substrate; a wiring layer disposed between the semiconductor substrate and the second electrode and including a portion of the signal line; and a capacitor element disposed between the wiring layer and the semiconductor substrate in a normal direction of the semiconductor substrate, and including a third electrode, a fourth electrode disposed between the third electrode and the semiconductor substrate, and a dielectric layer disposed between the third electrode and the fourth electrode; When viewed along a normal direction of the semiconductor substrate, at least one electrode selected from the group consisting of the third electrode and the fourth electrode covers the first impurity region. 2. The imaging device according to claim 1, wherein: Each of the plurality of pixels further includes a second transistor including a gate electrode electrically connected to the second electrode. 3. The imaging device according to claim 1, wherein: When viewed along the normal direction, the at least one electrode selected from the group consisting of the third electrode and the fourth electrode covers at least a portion of the second impurity region. 4. The imaging device according to claim 2, wherein: The device further includes a connection portion that electrically connects the second electrode to the first impurity region and that electrically connects the second electrode to the gate electrode of the second transistor. 5. The imaging device according to claim 4, wherein: At least one selected from the group consisting of the third electrode and the fourth electrode includes an opening. 6. The imaging device according to claim 5, wherein: The connecting portion passes through the opening. 7. The imaging device according to claim 4, wherein: The fourth electrode has a first surface facing the third electrode and a second surface opposite to the first surface, and is electrically connected to the second impurity region; At least a portion of the connection portion faces the second surface and extends within a plane perpendicular to the normal direction. 8. The imaging device according to claim 7, wherein: The fourth electrode is electrically connected to the second impurity region on the second surface. 9. The imaging device according to claim 7, wherein: further comprising a feedback circuit for providing negative feedback to the output of the second transistor; The feedback circuit includes a third transistor including a source and a drain; One of the source and the drain is connected to the second impurity region. 10. The imaging device according to claim 4, wherein: The fourth electrode has a first surface facing the third electrode and a second surface opposite to the first surface, and is electrically connected to the connection portion. 11. The imaging device according to claim 10, wherein: The fourth electrode is connected to the connection portion on the second surface. 12. The imaging device according to claim 10, wherein: further comprising a feedback circuit for providing negative feedback to the output of the second transistor; The second impurity region is electrically connected to an output line of the feedback circuit. 13. The imaging device according to claim 7, wherein: The dielectric layer covers a portion of the surface of the fourth electrode other than the second surface; The third electrode covers a side surface of the fourth electrode connecting the first surface and the second surface. 14. The imaging device according to claim 1, wherein: The signal line is a control line for driving the two or more pixels, a power supply line for supplying a voltage to the two or more pixels, or an output line for reading a signal from the two or more pixels. 15. The camera device according to claim 1, wherein: When viewed along the normal direction, the at least one electrode selected from the group consisting of the third electrode and the fourth electrode covers the entire first impurity region.