CN118507441B - A multi-chip stacking packaging structure and a manufacturing method thereof - Google Patents
A multi-chip stacking packaging structure and a manufacturing method thereof Download PDFInfo
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- CN118507441B CN118507441B CN202410629245.4A CN202410629245A CN118507441B CN 118507441 B CN118507441 B CN 118507441B CN 202410629245 A CN202410629245 A CN 202410629245A CN 118507441 B CN118507441 B CN 118507441B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 10
- 230000017525 heat dissipation Effects 0.000 claims abstract description 20
- 239000002184 metal Substances 0.000 claims description 7
- 238000003466 welding Methods 0.000 claims description 4
- 238000013021 overheating Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 description 5
- 238000012536 packaging technology Methods 0.000 description 4
- 230000035939 shock Effects 0.000 description 3
- 230000003139 buffering effect Effects 0.000 description 2
- 238000010521 absorption reaction Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
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- F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
- F16—ENGINEERING ELEMENTS AND UNITS; GENERAL MEASURES FOR PRODUCING AND MAINTAINING EFFECTIVE FUNCTIONING OF MACHINES OR INSTALLATIONS; THERMAL INSULATION IN GENERAL
- F16F—SPRINGS; SHOCK-ABSORBERS; MEANS FOR DAMPING VIBRATION
- F16F15/00—Suppression of vibrations in systems; Means or arrangements for avoiding or reducing out-of-balance forces, e.g. due to motion
- F16F15/02—Suppression of vibrations of non-rotating, e.g. reciprocating systems; Suppression of vibrations of rotating systems by use of members not moving with the rotating systems
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- F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
- F16—ENGINEERING ELEMENTS AND UNITS; GENERAL MEASURES FOR PRODUCING AND MAINTAINING EFFECTIVE FUNCTIONING OF MACHINES OR INSTALLATIONS; THERMAL INSULATION IN GENERAL
- F16F—SPRINGS; SHOCK-ABSORBERS; MEANS FOR DAMPING VIBRATION
- F16F15/00—Suppression of vibrations in systems; Means or arrangements for avoiding or reducing out-of-balance forces, e.g. due to motion
- F16F15/02—Suppression of vibrations of non-rotating, e.g. reciprocating systems; Suppression of vibrations of rotating systems by use of members not moving with the rotating systems
- F16F15/04—Suppression of vibrations of non-rotating, e.g. reciprocating systems; Suppression of vibrations of rotating systems by use of members not moving with the rotating systems using elastic means
- F16F15/06—Suppression of vibrations of non-rotating, e.g. reciprocating systems; Suppression of vibrations of rotating systems by use of members not moving with the rotating systems using elastic means with metal springs
- F16F15/067—Suppression of vibrations of non-rotating, e.g. reciprocating systems; Suppression of vibrations of rotating systems by use of members not moving with the rotating systems using elastic means with metal springs using only wound springs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/46—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids
- H01L23/467—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids by flowing gases, e.g. air
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
- H01L25/16—Assemblies consisting of a plurality of semiconductor or other solid state devices the devices being of types provided for in two or more different subclasses of H10B, H10D, H10F, H10H, H10K or H10N, e.g. forming hybrid circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
- H01L25/18—Assemblies consisting of a plurality of semiconductor or other solid state devices the devices being of the types provided for in two or more different main groups of the same subclass of H10B, H10D, H10F, H10H, H10K or H10N
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, the devices being individual devices of subclass H10D or integrated devices of class H10
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Engineering & Computer Science (AREA)
- Aviation & Aerospace Engineering (AREA)
- Mechanical Engineering (AREA)
- Acoustics & Sound (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
本发明公开了一种多芯片堆叠封装结构及其制造方法，包括载板，所述载板上方安装有外壳，所述外壳顶部和侧面均设置有多处散热孔，以及九个制造步骤；本发明堆叠结构中芯片之间的布局设计，使得芯片在堆叠时有部分区域重叠，有效节省了堆叠空间，使得整体尺寸更为紧凑，适用于有限空间的设备设计；通过外壳顶部和侧面设置多处散热孔、导热缓冲座和弹性导热条的设计，实现了对芯片产生的热量有效导出和散热，保证芯片在正常工作温度范围内，提高系统稳定性和可靠性；通过芯片堆叠结构设计，使得芯片的正投影在堆叠时有部分位置重叠，在节省空间的同时为芯片提供足够的散热空间，确保达到散热需求，避免芯片过热对系统性能产生负面影响。
The present invention discloses a multi-chip stacking packaging structure and a manufacturing method thereof, comprising a carrier board, a shell installed above the carrier board, a plurality of heat dissipation holes arranged on the top and sides of the shell, and nine manufacturing steps; the layout design between the chips in the stacking structure of the present invention enables the chips to overlap in some areas when stacked, effectively saving the stacking space, making the overall size more compact, and being suitable for the design of equipment with limited space; by arranging a plurality of heat dissipation holes, a heat conductive buffer seat and an elastic heat conductive strip on the top and sides of the shell, the heat generated by the chip is effectively extracted and dissipated, ensuring that the chip is within the normal operating temperature range, and improving the stability and reliability of the system; by designing the chip stacking structure, the orthographic projections of the chips overlap in some positions when stacked, saving space while providing sufficient heat dissipation space for the chips, ensuring that the heat dissipation requirements are met, and avoiding the negative impact of chip overheating on system performance.
Description
Technical Field
The invention relates to the technical field of semiconductor chip stacking and packaging, in particular to a multi-chip stacking and packaging structure and a manufacturing method thereof.
Background
The chip stacking packaging technology is a packaging technology for vertically or horizontally stacking a plurality of chips, through the technology, chips with different functions can be integrated into one package, so that higher functional density and performance are realized, space can be saved, power consumption can be reduced, system performance and overall reliability can be improved by stacking packaging, and the chip stacking packaging technology is widely applied to integrated circuit design and manufacture in various fields.
Disclosure of Invention
The invention provides a multi-chip stacking packaging structure and a manufacturing method thereof, which aim to solve the technical problem that the prior chip stacking packaging technology cannot save space and well meet the heat dissipation requirement.
The technical scheme of the invention is realized as follows:
The utility model provides a multicore piece piles up packaging structure, includes the carrier plate, the shell is installed to the carrier plate top, shell top and side all are provided with a plurality of louvres, the heat conduction buffer seat is still installed to shell top inner wall, the chip crowd is installed through fixed column and miniature buffer spring to the shell inside, the chip crowd divide into upper chip crowd and lower floor's chip crowd, install through elasticity heat conduction strip interval between upper chip crowd and the lower floor's chip crowd, elasticity heat conduction strip upper portion top department is pegged graft in the heat conduction buffer seat, the space has one section buffer distance between elasticity heat conduction strip upper portion top department and the shell top, metal ball is connected to carrier plate below electricity.
The upper chip group comprises a chip a, a chip b and a chip c, and the lower chip group comprises a chip d and a chip e.
The chip b is fixedly connected to the top of the shell through a fixing column on the upper surface of the chip b.
The chip a and the chip c are fixedly connected to the top of the shell through fixing columns on the upper surface of the chip a and the chip c, and are connected with the bottom of the shell through miniature buffer springs on the lower surface of the chip a and the chip c.
And the chip d and the chip e are fixedly arranged at the bottom of the shell through miniature buffer springs on the lower surfaces of the chip d and the chip e.
The orthographic projection of the chip a overlaps with the orthographic projection of the chip d by one third.
The orthographic projection of the chip d overlaps with the orthographic projection of the chip b by one third.
The orthographic projection of the chip b overlaps with the orthographic projection of the chip e by one third.
The orthographic projection of the chip e overlaps with the orthographic projection of the chip c by one third.
A manufacturing method of a multi-chip stacked package structure comprises the following steps:
s1: preparing a prefabricated carrier plate, and presetting an electric connection point at the bottom of the carrier plate;
s2: welding a miniature buffer spring at the bottom of the shell, and mounting a chip d and a chip e on the miniature buffer spring;
S3: attaching the prefabricated elastic heat conducting strips to the upper surfaces of the chips d and e, and then installing one end of the chip a above the chip d through the elastic heat conducting strips, so that the other end of the chip a is built on the miniature buffer spring, and the orthographic projection of the chip a is overlapped with the orthographic projection of the chip d by one third;
S4: then one end of the chip c is arranged above the chip e through an elastic heat conducting strip, and the other end of the chip c is built on the miniature buffer spring, so that the orthographic projection of the chip c is overlapped with the orthographic projection of the chip e by one third;
S5: then, the chip b is arranged above the chip d and the chip e through the elastic heat conducting strip, so that the front projection of the chip b overlaps with the front projection of the chip d by one third, and simultaneously, the front projection of the chip b overlaps with the front projection of the chip e by one third;
S6: attaching the prefabricated elastic heat conducting strips to the upper surfaces of the chip a, the chip b and the chip c;
S7: a heat dissipation hole is arranged in the shell, and then a fixing column and a heat conduction buffer seat are welded below the inner wall of the top of the shell;
s8: fixing the other ends of the fixing columns on the upper surfaces of the chips a and c, inserting the top ends of the upper parts of the elastic heat conducting strips into the heat conducting buffer seat, and welding the bottom of the shell, the top of the shell and the other four surfaces into a whole;
s9: and mounting the shell with the mounted chip on a carrier plate, and mounting metal balls on electrical connection points preset at the bottom of the carrier plate.
Compared with the prior art, the invention has the beneficial effects that:
(1) Space is saved: the layout design among the chips in the stacking structure ensures that partial areas of the chips overlap when the chips are stacked, thereby effectively saving the stacking space, ensuring that the whole size is more compact and being suitable for the equipment design in a limited space.
(2) Good heat dissipation performance: through the design that shell top and side set up a plurality of louvres, heat conduction buffer seat and elasticity heat conduction strip, realized effectively leading out and radiating the heat that the chip produced, guarantee that the chip is in normal operating temperature scope, improve system stability and reliability.
(3) Shockproof buffering: the design of the miniature buffer spring and the fixed column is utilized, so that the stability of the stacking structure of the chip group is enhanced, meanwhile, the chip can be damped when the chip is vibrated, the chip and the whole structure are protected from being damaged, and the reliability and the durability of the system are improved.
(4) Optimizing the heat dissipation space: through chip stacking structure design for the orthographic projection of chip overlaps when stacking, provides sufficient heat dissipation space for the chip when saving space, guarantees to reach the heat dissipation demand, avoids the overheated negative impact that produces the system performance of chip.
Drawings
FIG. 1 is a cross-sectional view of a multi-chip package on package structure according to an embodiment of the present invention;
Fig. 2 is a front view of a chip d according to a first embodiment of a multi-chip stacked package structure of the present invention;
fig. 3 is a top view of a chip d according to a first embodiment of a multi-chip stacked package structure of the present invention;
fig. 4 is a left side view of a chip d according to a first embodiment of a multi-chip stacked package structure of the present invention;
FIG. 5 is a cross-sectional view of a second embodiment of a multi-chip stacked package structure according to the present invention;
fig. 6 is a schematic step diagram of a method for manufacturing a multi-chip stacked package structure according to the present invention.
1. A carrier plate; 2. a housing; 3. a heat radiation hole; 4. a heat conduction buffer seat; 5. fixing the column; 6. a miniature buffer spring; 7. a chip group; 8. an upper chip group; 9. a lower chip group; 10. an elastic heat conducting strip; 11. a metal ball; 12. a chip a; 13. a chip b; 14. a chip c; 15. a chip d; 16. and a chip e.
Detailed Description
Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples are not representative of all implementations consistent with the present disclosure. Rather, they are merely examples of apparatus consistent with some aspects of the disclosure as detailed in the accompanying claims.
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Example 1
Referring to fig. 1 to 4, a multi-chip stacked package structure, which comprises a carrier plate 1, set up the circuit connection chip in the carrier plate 1, shell 2 is installed to carrier plate 1 top, shell 2 is used for piling up the chip, shell 2 top and side all are provided with many places louvres 3, louvres 3 are used for the heat dissipation, heat conduction buffer seat 4 is still installed to shell 2 top inner wall, thereby heat conduction buffer seat 4 is arranged in leading-in shell 2 of heat transfer in the chip, thereby shell 2 is inside to be installed chip crowd 7 through fixed column 5 and miniature buffer spring 6, fixed column 5 is arranged in fixed chip crowd 7, miniature buffer spring 6 is used for the chip to take precautions against earthquakes, chip crowd 7 comprises polylith chip, chip crowd 7 divide into upper chip crowd 8 and lower floor's chip crowd 9, upper chip crowd 8 includes chip a12, chip b13 and chip c14, lower floor's chip crowd 9 includes chip d15 and chip e16, heat conduction strip 10 is carried out heat conduction between chip crowd 8 and lower floor's chip 9 and the heat conduction strip and is carried out heat conduction section 10 to the top between the heat conduction device, and the top is connected to the top in the chip section of the elastic strip is avoided to the heat conduction device 10 to the top in the chip section is stacked to the top of the chip section, the heat conduction device is carried out to the top10 to the top section is connected to the top of the chip section 10.
The chip b13 is fixedly connected to the top of the housing 2 through the fixing posts 5 on the upper surface thereof, so as to increase the stability of the whole chip group 7.
The chip a12 and the chip c14 are fixedly connected to the top of the shell 2 through fixing posts 5 on the upper surface of the chip a12 and the chip c14, and are connected with the bottom of the shell 2 through miniature buffer springs 6 on the lower surface of the chip a and the chip c; the chip d15 and the chip e16 are fixedly arranged at the bottom of the shell 2 through the miniature buffer springs 6 on the lower surfaces of the chip d15 and the chip e16, so that the stability of the stacking structure of the chip group 7 is enhanced, and the functions of shock resistance and buffer are achieved.
The front projection of the chip a12 overlaps with the front projection of the chip d15 by one third, the front projection of the chip d15 overlaps with the front projection of the chip b13 by one third, the front projection of the chip b13 overlaps with the front projection of the chip e16 by one third, and the front projection of the chip e16 overlaps with the front projection of the chip c14 by one third.
The working process of the invention is as follows:
The top and the side of the shell 2 are provided with a plurality of heat dissipation holes 3 for heat dissipation, heat transferred from the chip is guided into the shell 2 through the heat conduction buffer seat 4 and the elastic heat conduction strip 10 on the inner wall of the top of the shell 2, when the chip group 7 is vibrated, the shock absorption can be maximally realized under the protection of the heat conduction buffer seat 4 and the miniature buffer spring 6, the orthographic projection of the chip a12 overlaps with the orthographic projection of the chip d15 by one third, the orthographic projection of the chip d15 overlaps with the orthographic projection of the chip b13 by one third, the orthographic projection of the chip b13 overlaps with the orthographic projection of the chip e16 by one third, and the orthographic projection of the chip e16 overlaps with the orthographic projection of the chip c14 by one third.
The layout design among the chips in the stacking structure ensures that partial areas of the chips overlap when the chips are stacked, so that the stacking space is effectively saved, the overall size is more compact, and the method is suitable for the design of equipment in a limited space; through the design that the top and the side surfaces of the shell 2 are provided with a plurality of heat dissipation holes 3, a heat conduction buffer seat 4 and an elastic heat conduction strip 10, the heat generated by the chip is effectively conducted out and dissipated, the chip is ensured to be in a normal working temperature range, and the stability and the reliability of the system are improved; the design of the miniature buffer spring 6 and the fixed column 5 is utilized, so that the stability of the stacking structure of the chip group 7 is enhanced, meanwhile, the chip can be damped when the chip is vibrated, the chip and the whole structure are protected from being damaged, and the reliability and the durability of the system are improved; through chip stacking structure design for the orthographic projection of chip overlaps when stacking, provides sufficient heat dissipation space for the chip when saving space, guarantees to reach the heat dissipation demand, avoids the overheated negative impact that produces the system performance of chip.
Example two
Referring to fig. 5, in another multi-chip stacked package structure, the multi-chip stacked package structure comprises a carrier plate 1, circuit connection chips are arranged in the carrier plate 1, a housing 2 is installed above the carrier plate 1, the housing 2 is used for stacking chips, a plurality of heat dissipation holes 3 are formed in the top and the side surfaces of the housing 2, the heat dissipation holes 3 are used for dissipating heat, a heat conduction buffer seat 4 is further installed on the inner wall of the top of the housing 2, the heat conduction buffer seat 4 is used for guiding heat transferred from the chips into the housing 2 for dissipating heat, a chip group 7 is installed inside the housing 2 through a fixing column 5 and a miniature buffer spring 6, the fixing column 5 is used for fixing the chip group 7, the miniature buffer spring 6 is used for chip shock prevention, the chip group 7 is composed of a larger number of chips, the arrangement of elastic heat conduction strips 10 is different, the elastic heat conduction strips 10 are in contact with each chip, then the heat in the housing 2 is brought into the side surface of the housing 2, the heat conduction buffer seat 4 is additionally arranged on the side surface of the housing 2, the heat conduction buffer seat 4 is used for guiding heat transferred from the chips into the housing 2, the chip group 7 is mounted through the fixing column 5 and the chip group 7, and the chip group 7 is used as a shock-absorbing medium for preventing the chip from being transferred from being stacked under the chip, and the chip group is connected to the metal balls 11.
Example III
Referring to fig. 6, a method for manufacturing a multi-chip stacked package structure includes the following steps:
S1: preparing a prefabricated carrier plate 1, and presetting an electric connection point at the bottom of the carrier plate 1;
s2: welding the miniature buffer spring 6 at the bottom of the shell 2, and mounting the chip d15 and the chip e16 on the miniature buffer spring 6;
S3: attaching the prefabricated elastic heat conducting strip 10 to the upper surfaces of the chip d15 and the chip e16, and then installing one end of the chip a12 above the chip d15 through the elastic heat conducting strip 10, so that the other end of the chip a12 is built on the miniature buffer spring 6, and the orthographic projection of the chip a12 is overlapped with the orthographic projection of the chip d15 by one third;
s4: then one end of the chip c14 is arranged above the chip e16 through the elastic heat conducting strip 10, and the other end of the chip c14 is built on the miniature buffer spring 6, so that the orthographic projection of the chip c14 is overlapped with the orthographic projection of the chip e16 in a third position;
S5: then, the chip b13 is arranged above the chip d15 and the chip e16 through the elastic heat conducting strip 10, so that the front projection of the chip b13 overlaps with the front projection of the chip d15 by one third, and simultaneously, the front projection of the chip b13 overlaps with the front projection of the chip e16 by one third;
S6: attaching the prefabricated elastic heat conducting strips 10 to the upper surfaces of the chip a12, the chip b13 and the chip c 14;
s7: a heat dissipation hole 3 is arranged in the shell 2, and then a fixing column 5 and a heat conduction buffer seat 4 are welded below the inner wall of the top of the shell 2;
s8: the other ends of the fixing columns 5 are fixed on the upper surfaces of the chip a12 and the chip c14, meanwhile, the top ends of the upper parts of the elastic heat conducting strips 10 are inserted into the heat conducting buffer seat 4, and the bottom of the shell 2, the top of the shell 2 and the other four surfaces are welded into a whole;
S9: the shell 2 with the mounted chip is mounted on the carrier plate 1, and the metal balls 11 are mounted on electrical connection points preset at the bottom of the carrier plate 1.
The method is characterized in that the components such as the miniature buffer spring 6, the elastic heat conducting strip 10 and the like are gradually arranged on the shell 2 and the chip to form a multi-chip stacked packaging structure, so that the logic of the manufacturing process is clear, and the operation and the control are convenient; the chips are mounted step by step, and the stable connection and the buffering effect between the chips are realized by utilizing the design of the miniature buffer spring 6 and the elastic heat conducting strip 10, so that the stability of the whole stacking structure is enhanced; by adopting a special chip stacking mode and reasonably designing the position relationship among the chips, partial positions of orthographic projections of the chips are overlapped when the chips are stacked, so that the space is fully utilized, and the stacking space is saved; the prefabricated components and the step-by-step installation mode are utilized, so that the production efficiency is improved, and the manufacturing cost is reduced.
Claims (5)
1. A multi-chip stacked package structure is characterized in that: the heat conducting buffer seat (4) is further arranged on the inner wall of the top of the shell (2), the chip group (7) is arranged inside the shell (2) through the fixing column (5) and the miniature buffer spring (6), the chip group (7) is divided into an upper chip group (8) and a lower chip group (9), the upper chip group (8) and the lower chip group (9) are arranged at intervals through the elastic heat conducting strip (10), the top end of the upper part of the elastic heat conducting strip (10) is inserted into the heat conducting buffer seat (4), a buffer distance is reserved between the top end of the upper part of the elastic heat conducting strip (10) and the top of the shell (2), and the lower part of the carrier (1) is electrically connected with the metal ball (11); the upper chip group (8) comprises a chip a (12), a chip b (13) and a chip c (14), the lower chip group (9) comprises a chip d (15) and a chip e (16), and the orthographic projection of the chip a (12) overlaps with the orthographic projection of the chip d (15) by one third;
the orthographic projection of the chip d (15) overlaps with the orthographic projection of the chip b (13) by one third;
The orthographic projection of the chip b (13) overlaps with the orthographic projection of the chip e (16) by one third;
the front projection of the chip e (16) overlaps one third of the front projection of the chip c (14).
2. The multi-chip stack package structure of claim 1, wherein: the chip b (13) is fixedly connected to the top of the shell (2) through a fixing column (5) on the upper surface of the chip b.
3. The multi-chip stack package structure of claim 2, wherein: the chip a (12) and the chip c (14) are fixedly connected to the top of the shell (2) through fixing columns (5) on the upper surface of the chip a and the chip c, and are connected with the bottom of the shell (2) through miniature buffer springs (6) on the lower surface of the chip a and the chip c.
4. The multi-chip stack package structure of claim 2, wherein: the chip d (15) and the chip e (16) are fixedly arranged at the bottom of the shell (2) through miniature buffer springs (6) on the lower surfaces of the chip d and the chip e.
5. The manufacturing method of the multi-chip stacked packaging structure is characterized by comprising the following steps of:
S1: preparing a prefabricated carrier plate (1), and presetting an electric connection point at the bottom of the carrier plate (1);
s2: welding the miniature buffer spring (6) at the bottom of the shell (2), and mounting the chip d (15) and the chip e (16) on the miniature buffer spring (6);
S3: attaching the prefabricated elastic heat conducting strip (10) to the upper surfaces of the chip d (15) and the chip e (16), and then installing one end of the chip a (12) above the chip d (15) through the elastic heat conducting strip (10), so that the other end of the chip a (12) is built on the miniature buffer spring (6), and the orthographic projection of the chip a (12) is overlapped with the orthographic projection of the chip d (15) by one third;
S4: then one end of the chip c (14) is arranged above the chip e (16) through the elastic heat conducting strip (10), and the other end of the chip c (14) is built on the miniature buffer spring (6) so that the orthographic projection of the chip c (14) is overlapped with the orthographic projection of the chip e (16) by one third;
S5: then, the chip b (13) is arranged above the chip d (15) and the chip e (16) through the elastic heat conducting strip (10), so that the orthographic projection of the chip b (13) overlaps with the orthographic projection of the chip d (15) by one third, and meanwhile, the orthographic projection of the chip b (13) overlaps with the orthographic projection of the chip e (16) by one third;
S6: attaching the prefabricated elastic heat conducting strips (10) to the upper surfaces of the chip a (12), the chip b (13) and the chip c (14);
s7: a heat dissipation hole (3) is arranged in the shell (2), and then a fixing column (5) and a heat conduction buffer seat (4) are welded below the inner wall of the top of the shell (2);
S8: the other ends of the fixing columns (5) are fixed on the upper surfaces of the chips a (12) and c (14), the top ends of the upper parts of the elastic heat conducting strips (10) are inserted into the heat conducting buffer seat (4), and the bottom of the shell (2) is welded with the top of the shell (2) and the other four surfaces into a whole;
S9: the shell (2) with the mounted chip is mounted on the carrier plate (1), and the metal balls (11) are mounted on electrical connection points preset at the bottom of the carrier plate (1).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410629245.4A CN118507441B (en) | 2024-05-21 | 2024-05-21 | A multi-chip stacking packaging structure and a manufacturing method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410629245.4A CN118507441B (en) | 2024-05-21 | 2024-05-21 | A multi-chip stacking packaging structure and a manufacturing method thereof |
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| CN118507441A CN118507441A (en) | 2024-08-16 |
| CN118507441B true CN118507441B (en) | 2024-11-22 |
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| CN117038602A (en) * | 2023-08-07 | 2023-11-10 | 深圳市金誉半导体股份有限公司 | Semiconductor device stacking and packaging structure |
| CN117690898A (en) * | 2022-09-02 | 2024-03-12 | 长鑫存储技术有限公司 | Semiconductor structure and method for manufacturing semiconductor structure |
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| JPS61185958A (en) * | 1985-02-14 | 1986-08-19 | Nippon Telegr & Teleph Corp <Ntt> | Structure and method for mounting three-dimensional lsi |
| JP4868547B2 (en) * | 2006-06-08 | 2012-02-01 | インターナショナル・ビジネス・マシーンズ・コーポレーション | HEAT CONDUCTIVE MODULE, ITS MANUFACTURING METHOD, AND HIGHLY HEAT CONDUCTIVE AND FLEXIBLE SEAT |
| US8558374B2 (en) * | 2011-02-08 | 2013-10-15 | Endicott Interconnect Technologies, Inc. | Electronic package with thermal interposer and method of making same |
| JP6206359B2 (en) * | 2014-08-28 | 2017-10-04 | トヨタ自動車株式会社 | Semiconductor device |
| CN214705914U (en) * | 2021-05-13 | 2021-11-12 | 河南逸云国芯科技有限公司 | Semiconductor chip stacking and packaging device |
| CN217544598U (en) * | 2022-06-14 | 2022-10-04 | 广东全芯半导体有限公司 | Packaging structure for semiconductor chip |
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| CN117690898A (en) * | 2022-09-02 | 2024-03-12 | 长鑫存储技术有限公司 | Semiconductor structure and method for manufacturing semiconductor structure |
| CN117038602A (en) * | 2023-08-07 | 2023-11-10 | 深圳市金誉半导体股份有限公司 | Semiconductor device stacking and packaging structure |
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