CN118501673A - Chip integrated test board based on piezoceramics - Google Patents

Abstract

The invention discloses a chip integrated test board based on piezoelectric ceramics, comprising: a chip test integrated structure; the chip test integrated structure comprises a base and an upper cover, the base and the upper cover are provided with a volume cavity; a printed layer is provided on the inner side of the volume cavity, a transfer layer is provided on the printed layer, a plurality of piezoelectric ceramics are provided on the transfer layer; a T/R chip packaging component is provided on the transfer layer; the base and the upper cover are clamped, so that the T/R chip packaging component squeezes the piezoelectric ceramics on the transfer layer, and the pressure state of the T/R chip is tested. Through the positive piezoelectric effect generated by the piezoelectric ceramics under pressure, the pressure state of the T/R chip packaging component in the test can be collected, and then through the inverse piezoelectric effect of the local piezoelectric ceramics, the local mechanical size change can be brought about, and the local pressure state of the transfer layer can be changed, so as to adjust the pressure condition of the T/R chip packaging component, so that each contact feeding point is evenly compressed, and no test performance deviation will be generated due to inconsistent contact state.

Description

A chip integration test board based on piezoelectric ceramics

Technical Field

The invention relates to the field of antenna array element testing, and in particular to a chip integration testing board based on piezoelectric ceramics.

Background Art

Radar antenna arrays are developing in the direction of intelligent, lightweight and conformal technology, which has brought about the rapid growth of chip-based transceiver components. The consistency control of chips and packaged ceramic-based components in the production process and how to judge the qualification of the products after they are produced will undoubtedly lead to waste of time and loss of other components if they need to be assembled into finished products for testing. Therefore, a stable and non-destructive testing system is needed to test the performance indicators of the products in the unassembled state.

With the development of intelligent, lightweight and conformal chip array structures, the height and weight of the array have been greatly reduced. At the same time, the strength of the array structure has been greatly weakened, which may cause the degree of deformation during the assembly and use of the array to exceed the design requirements. During the inspection process, there are test consistency and stability problems caused by the production tolerance of the product itself. At the same time, for large radar antennas, real-time and continuous debugging is carried out according to the situation of each chip component. An antenna has hundreds of thousands or even millions of transceiver channels, which affects the inspection accuracy of the transceiver components.

Summary of the invention

The purpose of the present invention is to solve the shortcomings of the prior art and to propose a chip integration test board based on piezoelectric ceramics.

In order to achieve the above-mentioned object, the present invention adopts the following technical scheme: a chip integrated test board based on piezoelectric ceramics, comprising a chip test integrated structure;

The chip test integrated structure comprises a base and an upper cover, wherein the base and the upper cover are provided with a volume cavity for placing the test board;

The test board comprises a printed layer, a transfer layer is arranged on the printed layer, and a plurality of piezoelectric ceramics are arranged on the transfer layer;

A T/R chip packaging component is arranged on the transfer layer;

The base and the upper cover are clamped to make the T/R chip packaging assembly squeeze the piezoelectric ceramic on the transfer layer, and the pressure state of the T/R chip is tested.

As a further description of the above technical solution: the T/R chip packaging component includes a box body, the top of the box body is connected to the outside, and a plurality of first feeding points are arranged in an array at the bottom of the box body.

As a further description of the above technical solution: the distance between two adjacent first feeding points is 0.4mm-0.9mm.

As a further description of the above technical solution: the transfer layer includes a positioning frame, and the end surface of the positioning frame is provided with a flexible interconnection layer;

A plurality of flexible connectors and the piezoelectric ceramics are arranged on the flexible interconnection layer.

As a further description of the above technical solution: the setting positions of the plurality of the flexible connectors are arranged corresponding to the positions of the plurality of the first feeding points.

As a further description of the above technical solution: the flexible connector includes a plurality of second feeding points, which are in contact and connected with the first feeding points to test the T/R chip.

As a further description of the above technical solution: the contact resistance between the first feeding point and the second feeding point is less than or equal to 150 mΩ, and the material of the flexible interconnection layer is silicone.

As a further description of the above technical solution: the upper and lower end surfaces of the piezoelectric ceramic are connected to wires, and the size of the piezoelectric ceramic in the vertical direction changes after power is supplied.

As a further description of the above technical solution: the force strain of the piezoelectric ceramic is in the range of 0.1%-0.2%, and the thickness is 0.4mm-0.6mm.

As a further description of the above technical solution: the size of the printed layer, the transfer layer and the T/R chip packaging component after connection is 0.8mm-1.0mm.

The above technical solution has the following advantages or beneficial effects:

1. Piezoelectric ceramics are integrated in the test board. The positive piezoelectric effect generated by the pressure on the piezoelectric ceramics can be used to collect the pressure state of the T/R chip package components during the test. The inverse piezoelectric effect of the local piezoelectric ceramics can bring about local mechanical size changes, and the local pressure state of the transfer layer can be changed, thereby adjusting the pressure condition of the T/R chip package components, so that each contact feeding point is evenly pressurized, and there will be no test performance deviation due to inconsistent contact states.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a schematic diagram of a test board and chip test integrated structure proposed by the present invention;

FIG2 is a schematic diagram of the structure of the printing layer and the transfer layer in the present invention;

FIG3 is a bottom view of the T/R chip package assembly of the present invention;

FIG4 is a perspective view of a transfer layer in the present invention;

FIG5 is a top view of the transfer layer of the present invention;

FIG6 is a partial enlarged view of the flexible connector in FIG5 ;

FIG7 is a partial enlarged view of the piezoelectric ceramic in FIG5;

FIG8 is a three-dimensional view of a piezoelectric ceramic according to the present invention;

FIG9 is a schematic structural diagram of another embodiment of the present invention;

Legend:

1. Base; 2. Upper cover; 3. Printed layer; 4. Transfer layer; 41. Positioning frame; 42. Flexible interconnection layer; 43. Flexible connector; 431. Second feeding point; 5. Piezoelectric ceramics; 6. T/R chip packaging assembly; 61. Box body; 62. First feeding point; 7. Limiting plate; 8. Piezoelectric ceramic actuator; 9. Antenna unit; 10. Support structure.

DETAILED DESCRIPTION

The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

1 to 8 , an embodiment of the present invention is as follows: a chip integrated test board based on piezoelectric ceramics, comprising a chip test integrated structure;

The chip test integrated structure comprises a base 1 and an upper cover 2, wherein the base 1 and the upper cover 2 are provided with a volume cavity for placing the test board;

The test board includes a printed layer 3, a transfer layer 4 is arranged on the printed layer 3, and a plurality of piezoelectric ceramics 5 are arranged on the transfer layer 4; a T/R chip packaging component 6 is arranged on the transfer layer 4; the clamping base 1 and the upper cover 2 are clamped to make the T/R chip packaging component 6 squeeze the piezoelectric ceramics 5 on the transfer layer 4 to test the pressure state of the T/R chip.

The inventors found in their research that in the miniaturized, high-density integrated inter-layer vertical interconnection, it is necessary to realize the connection of RF microwave signals, low-frequency control signals, and power supply signals. The introduction of a low-profile flexible interconnection structure can greatly solve the interconnection accuracy and tolerance problems caused by the deformation of the array surface. At the same time, the solder-free contact structure realizes lossless signal interconnection and maintainability issues between the tested parts. Therefore, based on the ability of piezoelectric ceramics to compensate for deformation, the inventors integrated piezoelectric ceramics into the flexible interconnection structure, which is equivalent to an actuator. Through the layout and size design of piezoelectric ceramics, during the flexible vertical interconnection between boards, the signal changes caused by the mutual matching pressure of the piezoelectric ceramics can be monitored, and the detection and information feedback of the test distance and pressure can be realized to realize the real-time monitoring of the interconnection state of the interconnection interface.

Piezoelectric materials are a type of electronic material that is sensitive to electricity, sound, light, and heat. They can realize the function of mutual conversion between mechanical energy and electrical energy and are widely used in industrial sectors and high-tech fields. When external force acts on piezoelectric materials to cause deformation, the distance between positive and negative bound charges inside the material becomes smaller, the polarization intensity also becomes smaller, and some of the free charges originally adsorbed on the electrodes are released, resulting in discharge, which is called the positive piezoelectric effect. The density of the charge is proportional to the magnitude of the applied pressure. When a certain intensity electric field is applied to the two poles of the piezoelectric material, the distance between the positive and negative charges in the sheet becomes larger, the polarization intensity also becomes larger, and some free charges are adsorbed on the electrodes to cause charging. The movement of charges in the circuit can output mechanical energy to the outside, which is called the inverse piezoelectric effect. Using the positive piezoelectric effect of piezoelectric materials, the pressure changes and distance changes of the interconnection end faces can be monitored, and whether there is overvoltage and pressure imbalance can be monitored in real time; using the inverse piezoelectric effect of piezoelectric materials, we can change the mechanical dimensions of the local interconnection interface through the actuator, and improve the reliability of the interconnection by adjusting the state of the interconnection end faces.

In this embodiment, the base 1 and the upper cover 2 of the chip test integrated structure clamp and limit the T/R chip package component 6. The piezoelectric ceramic 5 is integrated at the transfer layer 4. Through the positive piezoelectric effect generated by the pressure on the piezoelectric ceramic 5, the pressure state of the T/R chip package component 6 during the test can be collected. Then, through the inverse piezoelectric effect of the local piezoelectric ceramic, the local mechanical size change can be brought about, and the local pressure state of the transfer layer 4 can be changed, thereby adjusting the pressure of the T/R chip package component 6, so that each contact feeding point is evenly compressed, and there will be no test performance deviation due to inconsistent contact state, realizing the planar contact flexible interconnection of the high-frequency signal, low-frequency signal and power supply signal of the chip T/R chip, greatly improving the maintainability and signal connection reliability of the T/R chip, and a limit plate is set on the transfer layer 4 for placing the T/R chip package component 6, and the end face of the limit plate is in the same plane as the upper end face of the base 1.

Furthermore, the system connected to the test board is designed as an intelligent system with automatic error feedback and real-time automatic adjustment based on the feedback error information (implemented through existing PLC or MCU processor programming, not described in detail), realizing full automation in microsystem debugging and assembly lines, avoiding errors caused by different T/R chips being tested that lead to pseudo-differences in test performance, and greatly improving the stability, reliability and test efficiency of the test system.

3 , the T/R chip packaging assembly 6 includes a box body 61 , the top of the box body 61 is connected to the outside, and a plurality of first feeding points 62 are arranged in an array at the bottom of the box body 61 , and the spacing between two adjacent first feeding points 62 is 0.4 mm-0.9 mm.

In this embodiment, the T/R chip is set in the T/R chip packaging component 6. After packaging, a plurality of first feeding points 62 are arranged in a rectangular shape on the array surface interconnected to the outside. The spacing between the feeding points is 0.5 mm, 0.6 mm, 0.8 mm, etc. The function of the feeding points is defined by the T/R chip design.

4-5 , the transfer layer 4 includes a positioning frame 41 , and a flexible interconnection layer 42 is provided on the end face of the positioning frame 41 ; a plurality of flexible connectors 43 and piezoelectric ceramics 5 are provided on the flexible interconnection layer 42 ; and the positions of the plurality of flexible connectors 43 are arranged corresponding to the positions of the plurality of first feeding points 62 .

In this embodiment, a plurality of flexible connectors 43 and piezoelectric ceramics 5 may be provided on the flexible interconnection layer 42. The flexible connector 43 may transmit radio frequency signals, power supply and control signals, and the corresponding positions are arranged according to the position and definition of the first feeding point 62 of the interconnection end face of the T/R chip package component 6, and high-precision vertical interconnection is performed with the first feeding point 62 of the interconnection end face of the T/R chip package component 6. The piezoelectric ceramics 5 are evenly distributed on the flexible interconnection layer 42, and play the role of information collection and actuator without affecting the transmission of electrical performance, and compensate for the uneven deformation phenomenon caused by the T/R chip interconnection.

6 , the flexible connector 43 includes a plurality of second feeding points 431 , which are in contact and connected with the first feeding points 62 to test the T/R chip.

In this embodiment, the flexible connector 43 forms a radio frequency channel through a plurality of second feeding points 431. The second feeding points 431 are preferably provided with 9, the middle one is used as the central conductor 431a, and the remaining 8 are surrounded on the outside and grounded as the outer conductor 431b of the radio frequency channel. The T/R chip package assembly 6 is pressed by the chip test integrated structure, so that the central conductor of the flexible connector 43 is in contact with the first feeding point 62 to achieve radio frequency interconnection, and realize the low-profile flexible solder-free interconnection between the printed layer 3 of the unit combination array in the chip array and the chip T/R chip. At the same time, the pressure condition of the interconnection end face, the pressure balance condition, the deformation condition of the structural plate, etc. can be monitored, so as to avoid the overpressure problem of mutual matching and provide information support for solving the problem of uneven pressure.

7-8 , the contact resistance between the first feeding point 62 and the second feeding point 431 is less than or equal to 150 mΩ, and the material of the flexible interconnect layer 42 is silicone.

In this embodiment, the first feeding point 62 and the second feeding point 431 are composed of conductive particles. The second feeding point 431 forms a cylinder in the flexible interconnection layer 42, which has certain elastic expansion and contraction characteristics. When subjected to vertical pressure, it is elastically compressed together with the flexible interconnection layer 42 to form a conductive channel. The contact resistance of the first feeding point 62 and the second feeding point 431 is less than 150mΩ. The material used for the flexible interconnection layer 42 is non-conductive silicone. The elasticity of the silicone is used to form a flexible elastic insulating layer. The elastic properties of the silicone are used to contact each other to form a conductive path when subjected to pressure, and the silicone part without conductive particles remains in an insulating state. The thickness of the flexible interconnection layer 42 can be as low as 0.5mm, which can solve the problem of interconnection height above 0.5mm. When the second feeding point 431 is used alone, it can be used as a vertical interconnection mechanism for power supply and control signal transmission. According to the interface on the T/R chip packaging component 6, the flexible connector 43 is distributed and integrated at the corresponding position in the flexible interconnect layer 42, and the size of the conductive column formed by the second feeding point 431 is designed according to the requirements of the frequency and current size of the transmission signal.

The upper and lower end surfaces of the piezoelectric ceramic 5 are connected to the wires, and the size of the piezoelectric ceramic 5 in the vertical direction changes after power is applied; the range of the force strain of the piezoelectric ceramic 5 is 0.1%-0.2%, and the thickness is 0.4mm-0.6mm.

In this embodiment, the piezoelectric ceramics 5 are evenly distributed in the flexible interconnection layer 42, and need to avoid the position of the first feeding point 62, and are arranged at other positions that do not interfere with signal transmission, which does not affect the electrical performance. The piezoelectric ceramics 5 as an actuator need to be processed to 0.5mm, and need to be appropriately sized according to the strain of the material (0.1%-0.2%), which is suitable for light and thin structures, does not require a separate support point, and has low power consumption and does not affect system efficiency.

By applying an external electric field through the wire, the mechanical dimensions of the interconnected end faces can be slightly changed, so that the pressure on the interconnected end faces is balanced and the deformation tolerance meets the mutual matching requirements, making the connection more reliable. The pressure information, pressure information, distance dimensions, etc. of the interlayer interconnection can be collected, and then the piezoelectric ceramic actuator can be deformed in size through the inverse piezoelectric effect.

The size of the printed layer 3, the transfer layer 4 and the T/R chip packaging component 6 after connection is 0.8 mm-1.0 mm.

In this embodiment, the structure of the traditional high and low frequency floating connector is avoided, which greatly reduces the axial size of the antenna array surface caused by the use of traditional interconnection connectors. The axial size of the traditional smallest SMP, SSMP and 3SMP three-piece vertical interconnection is not less than 11mm. With the low-profile elastic interconnection of this application, the axial size can be reduced to 0.8mm-1.0mm, saving nearly 90% of the size.

Example 2

Referring to Figure 9, the test board is used in the antenna unit, and the T/R chip packaging component 6 can be pressed onto the transfer layer 4 with a structural cover to ensure good contact. The piezoelectric ceramic actuator 8 is arranged between the antenna unit 9 and the supporting structure 10. When the antenna unit is deformed, the pressure generated at each position of the piezoelectric ceramic actuator is different, resulting in different sizes of electrical signals generated by the piezoelectric ceramic 5. By collecting and analyzing the electrical signals of the piezoelectric ceramic 5, the piezoelectric ceramic actuators at positions with large differences can be reversely energized to produce an inverse piezoelectric effect, thereby producing mechanical deformation. The mechanical driving force of the piezoelectric ceramic actuator is directly used to compensate for its deformation size. The pressure conditions at different positions can be fed back through the piezoelectric ceramic 5. After analyzing the pressure state, it can be converted into mechanical energy through the inverse piezoelectric effect, the pressure state is adjusted, and the pressure conditions at different positions are balanced, without affecting the contact of other antenna positions, thereby keeping the large-surface contact balanced and consistent.

Finally, it should be noted that the above is only a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the aforementioned embodiments, it is still possible for those skilled in the art to modify the technical solutions described in the aforementioned embodiments or to make equivalent substitutions for some of the technical features therein. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims (10)

1. A chip integrated test board based on piezoelectric ceramics comprises a chip test integrated structure;

The chip test integrated structure comprises a base (1) and an upper cover (2), wherein the base (1) and the upper cover (2) are provided with a volume cavity for placing the test board; the method is characterized in that:

The test board comprises a printing layer (3), wherein an adapting layer (4) is arranged on the printing layer (3), and a plurality of piezoelectric ceramics (5) are arranged on the adapting layer (4);

The T/R chip packaging assembly (6) is arranged on the switching layer (4);

And clamping the base (1) and the upper cover (2) to enable the T/R chip packaging assembly (6) to squeeze the piezoelectric ceramics (5) on the switching layer (4) so as to test the pressed state of the T/R chip.

2. The test panel of claim 1, wherein: the T/R chip packaging assembly (6) comprises a box body (61), wherein the upper part of the box body (61) is communicated with the outside, and a plurality of first feeding points (62) are arranged on the bottom array of the box body (61).

3. The test panel of claim 2, wherein: the distance between two adjacent first feed points (62) is 0.4mm-0.9mm.

4. The test panel of claim 2, wherein: the transfer layer (4) comprises a positioning frame (41), and the end face of the positioning frame (41) is provided with a flexible interconnection layer (42);

A plurality of flexible connectors (43) and the piezoelectric ceramics (5) are arranged on the flexible interconnection layer (42).

5. The test panel of claim 4, wherein: the flexible connectors (43) are arranged at positions corresponding to the positions of the first feeding points (62).

6. The test panel of claim 4, wherein: the flexible connector (43) comprises a plurality of second feeding points (431) which are communicated with the first feeding points (62) in a contact way to test the T/R chip.

7. The test panel of claim 6, wherein: the contact resistance of the first feeding point (62) and the second feeding point (431) is less than or equal to 150mΩ, and the flexible interconnection layer (42) is made of silica gel.

8. The test panel of claim 1, wherein: the upper end face and the lower end face of the piezoelectric ceramic (5) are connected with a lead, and the dimension of the piezoelectric ceramic (5) in the vertical direction is changed after the piezoelectric ceramic is electrified.

9. The test panel of claim 1, wherein: the stress strain of the piezoelectric ceramic (5) is in the range of 0.1-0.2%, and the thickness is 0.4-0.6 mm.

10. The test panel of claim 1, wherein: the size of the printed layer (3), the transfer layer (4) and the T/R chip packaging assembly (6) after being connected is 0.8mm-1.0mm.