CN118484167A - Universal cyclic shift circuit - Google Patents
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- CN118484167A CN118484167A CN202410651061.8A CN202410651061A CN118484167A CN 118484167 A CN118484167 A CN 118484167A CN 202410651061 A CN202410651061 A CN 202410651061A CN 118484167 A CN118484167 A CN 118484167A
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- 238000012545 processing Methods 0.000 claims description 15
- 238000000034 method Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 3
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- 238000013461 design Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
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- 230000009286 beneficial effect Effects 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
- G06F5/01—Methods or arrangements for data conversion without changing the order or content of the data handled for shifting, e.g. justifying, scaling, normalising
- G06F5/015—Methods or arrangements for data conversion without changing the order or content of the data handled for shifting, e.g. justifying, scaling, normalising having at least two separately controlled shifting levels, e.g. using shifting matrices
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/76—Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data
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Abstract
A general cyclic shift circuit relates to the technical field of digital circuits, and has the main structure that: the device comprises m-level selector groups for receiving n-bit input data, wherein each level selector group comprises n 3:1 selectors, and the n 3:1 selectors of each level selector group are jointly controlled by a shift direction control signal C and a shift value control signal S, and the shift direction control signal C controls the shift direction of each level selector group to be left shift or right shift; the shift value control signal S controls the shift or non-shift of each stage selector group respectively, and the whole circuit can be controlled to be cyclically shifted by different bits finally through the shift value combination of each stage selector group. The invention can conveniently realize left or right cyclic shift of any bit width data.
Description
Technical Field
The invention relates to the technical field of digital circuits, in particular to a general cyclic shift circuit.
Background
The left cyclic shift and the right cyclic shift are common processing structures for algorithm and data splicing;
In HDL design language, only the left shift and the right shift are processed, and cyclic shift is not supported; and typically requires that the shift value be a constant value and that the shift value not be a variable. If a cyclic shift is to be supported, which shifts to a variable, it is common practice to:
case(s)
‘h0:o＝i；
‘h1:o＝{i[0],i[3:1]}；
‘h2:o＝{i[1:0],i[3:2]}；
‘h3:o＝{i[2:0],o[3]}；
Endcase
however, this approach can only perform data processing with a fixed data bit width, and if multiple bit widths are to be implemented, multiple similar circuits need to be designed to make a selection; while shifting left and right also requires a separate design.
Some prior art related to cyclic shift implementation, for example, implementation schemes of 'cyclic shift device, cyclic shift method, LDPC decoding device, television receiver and receiving system' with application number 200980139184.7 are: in the cyclic shift apparatus 33 including the barrel shifter 61 for performing cyclic shift with respect to the M pieces of input data, in the case of cyclic shifting parallel data composed of N pieces of input data smaller than the M pieces of input data by a shift amount k smaller than N, the selection circuit 62 selects first to nth-k shift data #1 to #n-k outputted by the barrel shifter 62 and outputs as first to nth-k output data #1 to #n-k, and selects nth-k+1+ (M-N) to nth+ (M-N) shift data #m-k+1 to #m outputted by the barrel shifter 62 and outputs as nth-k+1 to nth output data #n-k+1 to #n. The implementation scheme of the 'cyclic shift device and method of the sequence and the storage medium' with the application number 201811455830.8 is as follows: a first set of cyclic shift registers including a plurality of first cyclic shifters; the second group of cyclic shift registers comprises a plurality of second cyclic shifters, each output end of the kth first cyclic shifter is sequentially connected to the kth input end of each second cyclic shifter, and k is a positive integer; and the sequence rearrangement module is suitable for receiving the output data of the output end of each second cyclic shifter and rearranging the sequence of the output data to obtain an output sequence. The implementation scheme of the data processing device and method with the application number 201710527822.9 is as follows: the data processing device comprises a control unit, a first processing unit and a second processing unit, wherein the control unit is used for enabling the first processing unit and the second processing unit according to control signals; the first processing unit is used for performing S-bit cyclic shift on the first input data to the Z-S-th input data to obtain first cyclic shift data; the first processing unit is further configured to perform cyclic shift of s+p-Z bits on the Z-s+1th input data to the Z-th input data, to obtain second cyclic shift data; the second processing unit is used for receiving the first cyclic shift data and the second cyclic shift data transmitted by the first processing unit and outputting the first cyclic shift data and the second cyclic shift data. The prior art cannot realize the use of a set of circuits, and simultaneously realize the selection of the left shift or the right shift direction and support the shift value as a variable.
Disclosure of Invention
Based on the above problems, the invention aims to support cyclic left shift or cyclic right shift and simultaneously support parameterized data bit width by configuration, and can adapt to common use scenes such as FPGA/ASIC.
The technical scheme adopted by the invention for achieving the purpose of the invention is that the general cyclic shift circuit comprises m-level selector groups for receiving n-bit input data, wherein each level selector group comprises n 3:1 selectors, n is the bit width of the input data, and m is the minimum integer which is equal to or more than log 2 n;
The selector groups are sequentially from top to bottom 0 th-level selector groups to m-1 th-level selector groups, n-1 th bit 3:1 selector groups to 0 th bit 3:1 selector groups are sequentially from left to right in each level selector group, and n-1 th bit to 0 th bit are sequentially from left to right in input data;
Wherein:
The jth bit 3:1 selector of the 0 th level selector group is connected with the jth bit of input data, the 1 st input end of the selector group is connected with the input data bit with the jth bit cycle interval of 1 according to the right-to-left direction relative to the jth bit of the input data, and the 2 nd input end of the selector group is connected with the input data bit with the jth bit cycle interval of 1 according to the left-to-right direction relative to the jth bit of the input data;
The input end of the jth bit 3:1 selector of the ith level selector group is connected with the output end of the jth bit 3:1 selector of the ith-1 level selector group, the 1 st input end of the jth bit 3:1 selector is connected with the output end of the 3:1 selector of the jth bit 3:1 selector of the ith-1 level selector group according to the cycle interval of 2 i from right to left, and the 2 nd input end of the jth bit 3:1 selector is connected with the output end of the 3:1 selector of the jth bit 3:1 selector of the ith-1 level selector group according to the cycle interval of 2 i from left to right; the ith selector group is any one of the 1 st selector group to the m-1 st selector group;
the i is an integer which is more than or equal to 1 and less than or equal to m-1, and the j is an integer which is more than or equal to 0 and less than or equal to n-1;
The n 3:1 selectors of each stage selector group are commonly controlled by a shift direction control signal C and a shift value control signal S, wherein: the shift direction control signal C controls the shift direction of each stage of selector group to be left shift or right shift; the shift value control signal S is a binary value of a value to be shifted, and the bit number of the binary value of the value to be shifted sequentially corresponds to the 0 th-1 st-level selector group from right to left, and respectively controls the shift or non-shift of each level selector group.
Further, the 3:1 selector consists of two 2:1 selectors, wherein:
The 0 th input end of the first 2:1 selector is used as the 2 nd input end of the 3:1 selector, the 1 st input end of the first 2:1 selector is used as the 1 st input end of the 3:1 selector, the output end of the first 2:1 selector is connected with the 1 st input end of the second 2:1 selector, and the control end of the first 2:1 selector is connected with the shift direction control signal C;
The 0 th input end of the second 2:1 selector is used as the 0 th input end of the 3:1 selector, the output end of the second 2:1 selector is used as the output end of the 3:1 selector, and the control end of the second 2:1 selector is connected with a corresponding bit of the binary value of the shift value control signal S.
Further, the shift value control signal S is a binary value of a to-be-shifted value, and indicates that the shift is not performed when one bit is equal to 0, and the 3:1 selector in the selector group corresponding to the bit transfers the data of the 0 th input end to the output end;
the shift value control signal S, that is, a binary value of a value to be shifted, indicates shifting when one bit is equal to 1, and the 3:1 selector in the selector group corresponding to the bit transfers the data of the 1 st input terminal or the 2 nd input terminal to the output terminal.
Further, when the control signal C is equal to 0, the control signal C indicates a shift left, and the 3:1 selector transfers the data of the 2 nd input terminal to the output terminal;
When the control signal C is equal to 1, the right shift is indicated, and the 3:1 selector transmits the data of the 1 st input end to the output end.
Further, the input data is also passed through a register to a 3:1 selector in the level 0 selector set.
Further, a register is connected in series to the output of the 3:1 selector of at least one stage of the selector group.
When the data width to be shifted is large, the shifted level will deepen, resulting in an increase of the number of combinational logic levels, and a reduction of the highest frequency of circuit operation, and at this time, according to the timing sequence of each level of selector group circuit, registers can be inserted in the required level, namely: it may be all 3:1 selector outputs of one stage selector bank plus registers, or it may be all 3:1 selector outputs of multiple stage selector banks plus registers, or even all 3:1 selector outputs of all selector banks plus registers. The output end data of the register is used as the input data or final output data of the next-stage selector group, and the register is used for delay alignment in pipeline processing to improve the working frequency of the circuit.
Considering PPA (Power-Performance-Area), if the cyclic left shift and cyclic right shift are not required to be supported in practical application, the control signal C can be connected with a fixed value, and unnecessary selection logic and connection lines can be removed through tool optimization.
The beneficial effects of the invention are as follows:
The concept of shifting the barrel is used to build a general circuit, the shifting direction is controlled to be left or right by skillfully utilizing the shifting direction control signal C, and the shifting value is supported to be variable by utilizing the shifting value control signal S.
Drawings
FIG. 1 is a schematic diagram of a cyclic shift circuit according to an embodiment of the present invention;
FIG. 2 is a schematic diagram showing the internal structure of a selector according to embodiment 3:1 of the present invention;
fig. 3 is a schematic diagram of implementing a right cyclic shift function according to an embodiment of the present invention.
Detailed Description
In order that the above-recited objects, features and advantages of the present invention will be more clearly understood, a more particular description of the invention will be rendered by reference to the appended drawings and appended detailed description.
Fig. 1 to 3 show a specific embodiment of the cyclic shift circuit of the present invention: the data processing system comprises m-level selector groups for receiving n-bit input data, wherein each level selector group comprises n 3:1 selectors, n is the bit width of the input data, and m is the minimum integer which is equal to or more than log 2 n;
The selector groups are sequentially from top to bottom 0 th-level selector groups to m-1 th-level selector groups, n-1 th bit 3:1 selector groups to 0 th bit 3:1 selector groups are sequentially from left to right in each level selector group, and n-1 th bit to 0 th bit are sequentially from left to right in input data;
Wherein:
The jth bit 3:1 selector of the 0 th level selector group is connected with the jth bit of input data, the 1 st input end of the selector group is connected with the input data bit with the jth bit cycle interval of 1 according to the right-to-left direction relative to the jth bit of the input data, and the 2 nd input end of the selector group is connected with the input data bit with the jth bit cycle interval of 1 according to the left-to-right direction relative to the jth bit of the input data;
The input end of the jth bit 3:1 selector of the ith level selector group is connected with the output end of the jth bit 3:1 selector of the ith-1 level selector group, the 1 st input end of the jth bit 3:1 selector is connected with the output end of the 3:1 selector of the jth bit 3:1 selector of the ith-1 level selector group according to the cycle interval of 2 i from right to left, and the 2 nd input end of the jth bit 3:1 selector is connected with the output end of the 3:1 selector of the jth bit 3:1 selector of the ith-1 level selector group according to the cycle interval of 2 i from left to right; the ith selector group is any one of the 1 st selector group to the m-1 st selector group;
the i is an integer which is more than or equal to 1 and less than or equal to m-1, and the j is an integer which is more than or equal to 0 and less than or equal to n-1;
The n 3:1 selectors of each stage selector group are commonly controlled by a shift direction control signal C and a shift value control signal S, wherein: the shift direction control signal C controls the shift direction of each stage of selector group to be left shift or right shift; the shift value control signal S is a binary value of a value to be shifted, and the bit number of the binary value of the value to be shifted sequentially corresponds to the 0 th-1 st-level selector group from right to left, and respectively controls the shift or non-shift of each level selector group.
In this embodiment, the 3:1 selector is composed of two 2:1 selectors, wherein:
The 0 th input end of the first 2:1 selector is used as the 2 nd input end of the 3:1 selector, the 1 st input end of the first 2:1 selector is used as the 1 st input end of the 3:1 selector, the output end of the first 2:1 selector is connected with the 1 st input end of the second 2:1 selector, and the control end of the first 2:1 selector is connected with the shift direction control signal C;
The 0 th input end of the second 2:1 selector is used as the 0 th input end of the 3:1 selector, the output end of the second 2:1 selector is used as the output end of the 3:1 selector, and the control end of the second 2:1 selector is connected with a corresponding bit of the binary value of the shift value control signal S.
The shift value control signal S is a binary value of a to-be-shifted value, and represents no shift when one bit is equal to 0, and a 3:1 selector in the selector group corresponding to the bit transmits data of a 0 th input end to an output end;
the shift value control signal S, that is, a binary value of a value to be shifted, indicates shifting when one bit is equal to 1, and the 3:1 selector in the selector group corresponding to the bit transfers the data of the 1 st input terminal or the 2 nd input terminal to the output terminal.
When the control signal C is equal to 0, the control signal C represents left shift, and the 3:1 selector transmits the data of the 2 nd input end to the output end;
When the control signal C is equal to 1, the right shift is indicated, and the 3:1 selector transmits the data of the 1 st input end to the output end.
The input data is also connected with a 3:1 selector in the 0 th level selector group through a register D, and the output end of the 3:1 selector is also connected with the register D in series.
As can be seen from fig. 2, each 3:1 selector is composed of two 2:1 selectors, the control terminal of the first 2:1 selector is connected to the shift direction control signal C, the control terminal of the second 2:1 selector is connected to one bit Sx of the binary value of the shift value control signal S, and when Sx is equal to 0, the second 2:1 selector transmits the data Mk of the 0 th input terminal to the output terminal; since the 0 th input of the second 2:1 selector is used as the 0 th input of the 3:1 selector, and the output of the second 2:1 selector is used as the output of the 3:1 selector, the following is achieved: when one of the corresponding bits of the binary value of S is equal to 0, the 3:1 selector passes the data Mk at its 0 th input to the output, i.e. not shifted.
When Sx is equal to 1, the second 2:1 selector passes its 1 st input data, i.e. the first 2:1 selector output data, to the output, i.e. represents a shift. The specific shift direction is selected by controlling the first 2:1 selector by a shift direction control signal C, namely when C is equal to 0, the first 2:1 selector transmits the data M (k-y) of the 0 th input end of the first 2:1 selector to the output end of the first 2:1 selector, namely the data M (k-y) of the 2 nd input end of the 3:1 selector is finally transmitted to the output end, so that left shift is realized; when C is equal to 1, the first 2:1 selector transfers the data M (k+y) at the 1 st input end to the output end, that is, the data M (k+y) at the 1 st input end equivalent to the 3:1 selector is finally transferred to the output end, so that the right shift is realized.
As for the specific value of the shift, the common control of the values of the bits of the binary value of the shift value control signal S is implemented, and in conjunction with fig. 3, a right cyclic shift of 5bit data is taken as an example for further details:
Because the 5bit data has smaller data width, the register D is not needed in this example; of course, in the implementation, due to the influence of various factors such as actual circuit process, if the circuit timing is not good, registers may be added at the required level according to the specific situation.
In addition, since this example does not involve a left cyclic shift process, i.e., C is fixed to be equal to 1, the shift direction control signal C is omitted in fig. 3, and the 2 nd input of the 3:1 selector and its connection lines are omitted for simplicity of description and for ease of understanding of the shift control process.
Since the input data is 5 bits, the supported shift values are 0-4, and the shift values need to be represented by 3 bits, that is, the binary values of the shift value control signal S are S2, S1, S0 from high to low, respectively.
A 0 th stage selector group selecting no shift by S0 being equal to 0, or selecting right cyclic shift by S0 being equal to 1;
As defined above, the input data is from the n-1 bit to the 0 bit in turn from left to right, and from the n-1 bit 3:1 selector to the 0 bit 3:1 selector in turn from left to right in each selector group. Taking the 3 rd bit 3:1 selector (i.e. the selector with the output end number of M03) in the 0 th selector group in fig. 3 as an example, the 1 st input end is connected with the 3 rd bit (i.e. the I3 in the figure) of the input data according to the input data bit with the cycle interval of 1 from right to left, that is, the 1 st input end is connected with the I4 of the input data, the 2 nd bit 3:1 selector (i.e. the selector with the output end number of M02) has the 1 st input end connected with the I3 of the input data, the 1 st bit 3:1 selector (i.e. the selector with the output end number of M01) has the 1 st input end connected with the I2 of the input data, and the 0 th bit 3:1 selector (i.e. the selector with the output end number of M00) has the 1 st input end connected with the I1 of the input data, and the 4 th bit 3:1 selector (i.e. the selector with the output end number of M04) has the 1 st input end connected with the I0 of the input data.
When S0 is equal to 1, each 3:1 selector passes the data at its 1 st input to its output, while the 1 st input is from the left side data, i.e., it is achieved: when S0 is equal to 1, a right circular shift of 1 bit is implemented within the 0 th stage selector set.
Since the wiring cycle interval in the 1 st stage selector group is 2 1 =2, the wiring cycle interval in the 2 nd stage selector group is 2 2 =4, and the same can be achieved:
A1 st stage selector group that selects not to shift by S1 being equal to 0, or right cyclically shifts by 2 bits when S1 is equal to 1;
the 2 nd stage selector group selects not to shift by S2 being equal to 0, or right cyclic shift by 4 bits when S2 is equal to 1.
If S2S1S0 is controlled to be different values, the shift values through each selector group are combined, the whole circuit can be controlled to be finally shifted right circularly by different bits, for example:
S2S1S0 is 001, and the whole circuit is circularly shifted by 1 bit; S2S1S0 is 010, and the whole circuit is shifted by 2 bits in a right circulation way; S2S1S0 is 011, and the whole circuit is circularly shifted by 3 bits; S2S1S0 is 100, and the whole circuit is shifted by 4 bits in a right circulation way.
Through the structure, arbitrary 0-4 bit right cyclic shift (0 bit right cyclic shift is not shifted) of 5bit data can be realized. If the data is 8 bits, the 3-stage selector group structure is adopted, and only 8 selectors are included in each stage of selector group, so that 0-7 bit right cyclic shift can be realized conveniently.
The implementation of the left cyclic shift is the same as described above, except that the 2 nd input of the 3:1 selector is from the right data.
According to the embodiment, the circuit structure of the invention can conveniently realize left-circular or right-circular shift of any bit width data.
The above examples of the present invention are merely illustrative of the present invention and are not intended to limit the embodiments of the present invention. Other variations and modifications of the present invention will be apparent to those of ordinary skill in the art in light of the foregoing description. Not all embodiments are exhaustive. Obvious changes and modifications which are extended by the technical proposal of the invention are still within the protection scope of the invention.
Claims (6)
1. A universal cyclic shift circuit, characterized by:
The data processing system comprises m-level selector groups for receiving n-bit input data, wherein each level selector group comprises n 3:1 selectors, n is the bit width of the input data, and m is the minimum integer which is equal to or more than log 2 n;
The selector groups are sequentially from top to bottom 0 th-level selector groups to m-1 th-level selector groups, n-1 th bit 3:1 selector groups to 0 th bit 3:1 selector groups are sequentially from left to right in each level selector group, and n-1 th bit to 0 th bit are sequentially from left to right in input data;
Wherein:
The jth bit 3:1 selector of the 0 th level selector group is connected with the jth bit of input data, the 1 st input end of the selector group is connected with the input data bit with the jth bit cycle interval of 1 according to the right-to-left direction relative to the jth bit of the input data, and the 2 nd input end of the selector group is connected with the input data bit with the jth bit cycle interval of 1 according to the left-to-right direction relative to the jth bit of the input data;
The input end of the jth bit 3:1 selector of the ith level selector group is connected with the output end of the jth bit 3:1 selector of the ith-1 level selector group, the 1 st input end of the jth bit 3:1 selector is connected with the output end of the 3:1 selector of the jth bit 3:1 selector of the ith-1 level selector group according to the cycle interval of 2 i from right to left, and the 2 nd input end of the jth bit 3:1 selector is connected with the output end of the 3:1 selector of the jth bit 3:1 selector of the ith-1 level selector group according to the cycle interval of 2 i from left to right; the ith selector group is any one of the 1 st selector group to the m-1 st selector group;
the i is an integer which is more than or equal to 1 and less than or equal to m-1, and the j is an integer which is more than or equal to 0 and less than or equal to n-1;
The n 3:1 selectors of each stage selector group are commonly controlled by a shift direction control signal C and a shift value control signal S, wherein: the shift direction control signal C controls the shift direction of each stage of selector group to be left shift or right shift; the shift value control signal S is a binary value of a value to be shifted, and the bit number of the binary value of the value to be shifted sequentially corresponds to the 0 th-1 st-level selector group from right to left, and respectively controls the shift or non-shift of each level selector group.
2. A universal cyclic shift circuit according to claim 1, characterized in that: the 3:1 selector consists of two 2:1 selectors, wherein:
The 0 th input end of the first 2:1 selector is used as the 2 nd input end of the 3:1 selector, the 1 st input end of the first 2:1 selector is used as the 1 st input end of the 3:1 selector, the output end of the first 2:1 selector is connected with the 1 st input end of the second 2:1 selector, and the control end of the first 2:1 selector is connected with the shift direction control signal C;
The 0 th input end of the second 2:1 selector is used as the 0 th input end of the 3:1 selector, the output end of the second 2:1 selector is used as the output end of the 3:1 selector, and the control end of the second 2:1 selector is connected with a corresponding bit of the binary value of the shift value control signal S.
3. A universal cyclic shift circuit according to claim 1, characterized in that:
The shift value control signal S indicates that the shift is not performed when one bit is equal to 0, and the 3:1 selector in the selector group corresponding to the bit transmits the data of the 0 th input end to the output end;
the shift value control signal S indicates a shift when one of the bits is equal to 1, and the 3:1 selector in the selector group corresponding to the bit transfers the data of the 1 st input terminal or the 2 nd input terminal to the output terminal.
4. A universal cyclic shift circuit according to claim 3, characterized in that:
When the control signal C is equal to 0, the control signal C represents left shift, and the 3:1 selector transmits the data of the 2 nd input end to the output end;
When the control signal C is equal to 1, the right shift is indicated, and the 3:1 selector transmits the data of the 1 st input end to the output end.
5. A universal cyclic shift circuit according to claim 1, characterized in that: the input data is also coupled to a 3:1 selector in the level 0 selector bank via a register.
6. A universal cyclic shift circuit according to claim 1, characterized in that: the output end of the 3:1 selector of at least one stage of selector group is connected with a register in series.
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