CN118475118A - Semiconductor structure and method for manufacturing the same - Google Patents

Abstract

A semiconductor structure and a method for fabricating the same, the semiconductor structure comprising: a plurality of memory layers stacked in a vertical direction, each memory layer including a plurality of memory cells extending in a first direction and arranged in a second direction, the memory cells including a transistor and a first capacitance structure arranged in the first direction, the transistor including a channel layer and a word line structure, the channel layer covering at least a portion of a sidewall of the word line structure; and bit lines extending in the vertical direction, the bit lines being positioned on both sides of each transistor in the second direction, the bit lines being in contact with the channel layer. The semiconductor structure can effectively increase the contact area between the bit line and the channel layer, thereby increasing the on-current of the transistor and effectively improving the sensing margin of the semiconductor structure.

Description

Semiconductor structure and method for manufacturing the same

Technical Field

The embodiments of the present disclosure relate to the field of semiconductor technology, and in particular, to a semiconductor structure and a method for preparing the same.

Background Art

The development of dynamic random access memory (DRAM) pursues performance indicators such as high speed, high integration density, and low power consumption. As the size of semiconductor device structures shrinks, the technical barriers encountered by existing structures are becoming more and more obvious. Therefore, developing more novel structures based on existing structures is a favorable means to break through existing technical barriers.

The emergence of three-dimensional dynamic random access memory (3D DRAM), especially 3D DRAM including multilayer horizontal cells (MHC), which generally includes multiple transistors stacked on a substrate, meets the above requirements.

Due to the high integration of 3D DRAM and the reduced spacing between structures, the structural arrangement of the bit lines will greatly affect the sensing margin of the semiconductor structure.

Summary of the invention

According to a first aspect of an embodiment of the present disclosure, a semiconductor structure is provided, comprising: a plurality of storage layers stacked in a vertical direction, each storage layer comprising a plurality of storage cells extending in a first direction and arranged in a second direction, the storage cells comprising transistors and a first capacitor structure arranged in the first direction, the transistors comprising a channel layer and a word line structure, the channel layer at least covering a portion of the sidewall of the word line structure; bit lines extending in the vertical direction, the bit lines being located on both sides of each transistor along the second direction, the bit lines being in contact with the channel layer.

In some embodiments, the word line structure includes a conductor portion and a gate portion that are interconnected, the conductor portion extends along a second direction, the gate portion is located on one side of the conductor portion along a first direction, the channel layer surrounds the side wall of the gate portion and an end surface facing the first capacitor structure, and the size of the channel layer along the first direction is smaller than the size of the gate portion along the first direction.

In some embodiments, the gate portion includes a first gate portion, a second gate portion, and a third gate portion connected in sequence along a first direction, the first gate portion is adjacent to the wire portion, and the third gate portion is adjacent to the first capacitor structure; the cross-sectional area of the second gate portion perpendicular to the first direction is smaller than the cross-sectional area of the first gate portion perpendicular to the first direction, and the cross-sectional area of the second gate portion perpendicular to the first direction is smaller than the cross-sectional area of the third gate portion perpendicular to the first direction; the word line structure also includes a gate dielectric layer located between the second gate portion, the third gate portion, and the channel layer.

In some embodiments, the bit lines are located at both sides of the second gate portion along the second direction.

In some embodiments, the spacing between adjacent bit lines along the second direction is smaller than the spacing between adjacent channel layers along the second direction, and the spacing between adjacent bit lines respectively contacting two adjacent channel layers along the second direction is larger than the spacing between two bit lines contacting the same channel layer; in the direction of the bit line toward the contacted channel layer, the width of the bit line along the first direction gradually increases.

In some embodiments, the two bit lines on either side of each transistor are electrically connected.

In some embodiments, the semiconductor structure further includes: a second capacitor structure, the second capacitor structure is located between the first capacitor structures, and the first capacitor structure and the second capacitor structure are alternately arranged along the second direction and contact each other.

According to a second aspect of an embodiment of the present disclosure, a method for preparing a semiconductor structure is provided, comprising: forming a stacking structure, the stacking structure comprising a first stacking layer and a second stacking layer alternately stacked in a vertical direction, the stacking structure comprising a plurality of memory cell regions extending in a first direction and arranged in a second direction, the memory cell regions comprising a transistor region and a capacitor region arranged in the first direction; simultaneously forming a bit line on both sides of each transistor region along the second direction, the bit line extending in the vertical direction and passing through the stacking structure; forming a first capacitor structure in the capacitor region in each first stacking layer; forming a channel layer and a word line structure in the transistor region in each first stacking layer, the channel layer being in contact with the bit line and the first capacitor structure, and the channel layer at least covering a portion of the sidewall of the word line structure.

In some embodiments, bit lines are simultaneously formed on both sides of each transistor region along the second direction, including: removing a portion of the stacked structure to form a first sacrificial pattern located between the memory cell regions; forming a first groove located between the transistor regions, the first groove penetrating the first sacrificial pattern, and a size of the first groove along the second direction being greater than or equal to a size of the first sacrificial pattern along the second direction; forming an initial bit line layer on an inner wall of the first groove, and forming a protective layer on an inner wall of the initial bit line layer; removing the first sacrificial pattern to form an etched groove, the etched groove exposing a portion of the side wall of the initial bit line layer; removing a portion of the initial bit line layer along the etched groove, retaining portions of the initial bit line layer located on both sides of each transistor region along the second direction as bit lines.

In some embodiments, a channel layer and a word line structure are formed in the transistor region in each first stacked layer, including: removing a portion of the first stacked layer located in the transistor region to form a second groove; forming an initial channel layer on the inner wall of the second groove; forming a gate dielectric layer and a gate portion covering the initial channel layer in the transistor region; removing the exposed portion of the initial channel layer to form a channel layer; forming a wire portion extending along the second direction, the wire portion contacting a plurality of gate portions arranged along the second direction.

In the disclosed embodiment, the channel layer is arranged to cover the side wall of the word line structure, and two bit lines are respectively arranged on both sides of the transistor formed by the channel layer and the word line structure along the second direction. By utilizing the structural arrangement in which the two bit lines are in contact with the channel layer, the contact area between the bit lines and the channel layer can be effectively increased, thereby increasing the on-current of the transistor, thereby effectively improving the sensing margin of the semiconductor structure.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1a is a schematic diagram of a semiconductor structure according to an exemplary embodiment;

FIG. 1b is a schematic diagram of a semiconductor structure according to another exemplary embodiment;

FIG. 2a is a partial schematic diagram of a semiconductor structure according to another exemplary embodiment;

FIG. 2 b is a partial schematic diagram of another semiconductor structure according to another exemplary embodiment;

FIG3 is a schematic top view of a semiconductor structure according to an exemplary embodiment;

FIG4 is a flow chart of a method for preparing a semiconductor structure according to an embodiment of the present disclosure;

5a to 51 are schematic diagrams showing a semiconductor structure preparation process according to an embodiment of the present disclosure.

Description of reference numerals:

MR: memory cell region; TR: transistor region; CR capacitor region; M1: memory cell; T1: transistor; C1 capacitor structure; S1: sidewall of gate portion; S2: end face of gate portion; RR: stacking structure; X: first direction; Y: second direction; Z: vertical direction; 100: semiconductor structure; 101': first stacking layer; 101: memory layer; 102': second stacking layer; 102: spacer layer; 103: first sacrificial pattern; 104: first slot; 105: etched groove ; 106: isolation pattern; 107: isolation structure; 210’: initial bit line layer; 210: bit line; 220: protection layer; 301: first electrode portion; 301a: columnar conductive portion; 301b: plate-shaped conductive portion; 302: first dielectric layer; 303: second electrode portion; 310: first capacitor structure; 320: second capacitor structure; 410’: initial channel layer; 410: channel layer; 501: gate portion; 502: conductor portion; 503: gate dielectric layer; 510: word line structure.

DETAILED DESCRIPTION

The technical solution of the present disclosure will be further described in detail below in conjunction with the accompanying drawings and embodiments. Although the exemplary implementation methods of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the implementation methods described here. On the contrary, these implementation methods are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

The present disclosure is described in more detail in the following paragraphs by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become more apparent from the following description and claims. It should be noted that the drawings are in very simplified form and in non-precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present disclosure.

It will be understood that the meaning of “on,” “over,” and “over” of the present disclosure should be interpreted in the broadest manner, so that “on” not only means that it is “on” something with no intervening features or layers (i.e., directly on something), but also includes the meaning that it is “on” something with intervening features or layers.

In the embodiments of the present disclosure, the terms "first", "second", "third", etc. are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

In the disclosed embodiments, the term "layer" refers to a portion of a material including an area having a thickness. A layer may extend over the entirety of a lower or upper structure, or may have an extent less than the extent of a lower or upper structure. In addition, a layer may be an area of a homogeneous or inhomogeneous continuous structure having a thickness less than the thickness of a continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be between any horizontal faces at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and/or along an inclined surface. A layer may include multiple sublayers.

It should be noted that the technical solutions described in the embodiments of the present disclosure can be combined arbitrarily without conflict.

FIG. 1a is a schematic diagram of a semiconductor structure 100 according to an exemplary embodiment, FIG. 1b is a schematic diagram of a semiconductor structure 100 according to another exemplary embodiment, FIG. 2a is a partial schematic diagram of a semiconductor structure 100 according to another exemplary embodiment, FIG. 2b is a partial schematic diagram of another semiconductor structure 100 according to another exemplary embodiment, and FIG. 3 is a top view schematic diagram of a semiconductor structure 100 according to an exemplary embodiment. The semiconductor structure 100 will be described below in conjunction with FIG. 1a to FIG. 3.

1a, the semiconductor structure 100 includes a plurality of storage layers 101 stacked along a vertical direction Z, each storage layer 101 includes a plurality of storage cells M1 extending along a first direction X and arranged along a second direction Y, the storage cell M1 includes a transistor T1 and a first capacitor structure 310 arranged along the first direction X, the transistor T1 includes a channel layer 410 and a word line structure 510, the channel layer 410 at least covers a portion of a sidewall S1 of the word line structure 510; and a bit line 210 extending along the vertical direction Z, the bit line 210 being located on both sides of each transistor T1 along the second direction Y, and the bit line 210 is in contact with the channel layer 410.

Taking a three-dimensional dynamic random access memory as an example, a multi-layer storage layer structure including multiple storage cells is used to improve the integration of the semiconductor structure. The channel layer is set to cover the side wall of the word line structure, and two bit lines are respectively set on both sides of the transistor formed by the channel layer and the word line structure along the second direction. The structure setting in which the two bit lines are in contact with the channel layer can effectively increase the contact area between the bit line and the channel layer, thereby increasing the on-current of the transistor, so as to effectively improve the sensing margin of the semiconductor structure. The bit line 210 is set between the transistor regions TR, which can reduce the size of the storage cell M1 in the first direction X direction, improve the integration of the semiconductor structure 100, and significantly improve the storage density.

As shown in FIG. 1a, in the vertical direction Z, the storage layer 101 and the spacer layer 102 are alternately stacked in sequence, and the spacer layer 102 includes an insulating material for isolating adjacent storage layers 101. The insulating material includes, but is not limited to, silicon oxide, silicon nitride, silicon carbide, etc. Each storage layer 101 may include a plurality of storage cell regions MR extending along a first direction X and arranged along a second direction Y, and the storage cell region MR includes a transistor region TR and a capacitor region CR arranged along the first direction X. The transistor T1 is located in the transistor region TR, and the first capacitor structure 310 may be located in the capacitor region CR as a capacitor structure C1, and the transistor T1 and the capacitor structure C1 are electrically connected to each other and together constitute a storage cell M1.

In some embodiments, as shown in FIG. 1a, the first capacitor structure 310 includes a first electrode portion 301, a first dielectric layer 302, and a second electrode portion 303. The second electrode portion 303 is in contact with the channel layer 410, and the second electrode portion 303 can be a tubular structure or a columnar structure. Taking the second electrode portion 303 as a tubular structure as an example, the first dielectric layer 302 conformally covers the inner wall of the second electrode portion 303, the first electrode portion 301 is filled in the first dielectric layer 302, and the first dielectric layer 302 is sandwiched between the first electrode portion 301 and the second electrode portion 303. The first electrode portion 301 includes a columnar conductive portion 301a located in each capacitor region CR and a plate-shaped conductive portion 301b located at the end of each capacitor region CR, and each columnar conductive portion 301a is electrically connected to each other through the plate-shaped conductive portion 301b. The material of the first dielectric layer 302 may be a high dielectric constant material, a silicon oxide material, a silicon nitride material, a silicon oxynitride material, or the like or a combination thereof, and the high dielectric constant material includes one or more of the following: hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, etc. The materials of the first electrode portion 301 and the second electrode portion 303 may include a conductive material, for example, one or more of a metal, an alloy, a conductive metal-containing material, and a conductive doped semiconductor material. The second electrode portion 303 may be a single-layer structure, for example, the second electrode portion 303 may be a titanium nitride layer. The first electrode portion 301 may be a single-layer or multi-layer structure, for example, the first electrode portion 301 may be a multi-layer structure, and the multi-layer structure includes a titanium nitride layer 301c, and a tungsten layer composed of a columnar conductive portion 301a and a plate-shaped conductive portion 301b. The titanium nitride layer 301 c can conformally cover the inner wall of the first dielectric layer 302 and can serve as a diffusion barrier layer for the tungsten layer. The tungsten layer can reduce the resistivity of the first electrode portion 301 .

In some embodiments, referring to FIG. 1b, the semiconductor structure 100 further includes: a second capacitor structure 320, the second capacitor structure 320 is located between the first capacitor structure 310, and the first capacitor structure 310 and the second capacitor structure 320 are alternately arranged along the second direction Y and contact each other. The second capacitor structure 320 includes a third electrode portion 304 and a second dielectric layer 305. The second dielectric layer 305 is connected to the first capacitor structure 310 on both sides along the second direction Y. The third electrode portion 304 is electrically connected to the first electrode portion 301, and the first capacitor structure 310 and the second capacitor structure 320 are used to jointly constitute the capacitor structure C1. For example, contact plugs can be formed above the third electrode portion 304 and the first electrode portion 301, respectively, and connecting lines connecting the contact plugs can be formed. The second capacitor structure 320 can be a plurality of columnar structures extending along the vertical direction Z and arranged along the second direction Y platform. The third electrode portion 304 may be a single-layer or multi-layer structure. For example, the third electrode portion 304 may be a multi-layer structure composed of a titanium nitride layer and a tungsten layer. The titanium nitride layer may conformally cover the inner wall of the second dielectric layer 305 and may serve as a diffusion barrier layer for the tungsten layer. The tungsten layer may reduce the resistivity of the third electrode portion 304. By providing the second capacitor structure 320, the facing area between the third electrode portion 304 and the second electrode portion 303 is increased, thereby increasing the overall capacitance of the capacitor structure C1 formed by the second capacitor structure 320 and the first capacitor structure 310.

In other embodiments, the second capacitor structure 320 is filled between the first capacitor structures 310. For example, the second capacitor structure 320 can also be filled between the first capacitor structures 310 adjacent along the vertical direction Z. The second capacitor structure 320 can be an integral structure surrounding the first capacitor structure 310, thereby further increasing the capacitance of the capacitor structure C1.

In some embodiments, the transistor T1 includes a word line structure 510 and a channel layer 410, the word line structure 510 includes a wire portion 502 and a gate portion 501 connected to each other, the wire portion 502 extends along the second direction Y, the gate portion 501 is located on one side of the wire portion 502 along the first direction X, and the channel layer 410 surrounds the side wall S1 of the gate portion 501 and the end surface S2 facing the first capacitor structure 310. The word line structure 510 has a comb-like morphology, and the gate portion 501 extends from one side of the wire portion 502 along the first direction X toward the capacitor region CR. The channel layer 410 has a cylindrical morphology, has an opening facing the wire portion 502 along the first direction X, and the gate portion 501 is embedded in the cylindrical channel layer 410. The cross-section of the channel layer 410 along the first direction X is U-shaped.

The gate portion 501 may include a conductive material, such as one or more of the following: a metal (e.g., tungsten (W), titanium (Ti), molybdenum (Mo), niobium (Nb), vanadium (V), hafnium (Hf), tantalum (Ta), chromium (Cr), zirconium (Zr), iron (Fe), ruthenium (Ru), cobalt (Co), nickel (Ni)); an alloy (e.g., a Co-based alloy, a Ti-based alloy, an alloy based on Co and Ni, an alloy based on Fe and Co); a conductive metal-containing material (e.g., a conductive metal nitride, a conductive metal silicide, a conductive metal carbide, a conductive metal oxide); and a conductive doped semiconductor material (e.g., conductive doped polysilicon, conductive doped germanium (Ge), conductive doped silicon germanium (SiGe)).

The channel layer 410 may include a channel material, such as one or more of the following: silicon (e.g., single crystal silicon, polycrystalline silicon), germanium, silicon germanium, and oxide semiconductor materials (e.g., zinc tin oxide (ZnxSnyO, commonly known as "ZTO"), indium zinc oxide (InxZnyO, commonly known as "IZO"), zinc oxide (ZnxO), indium gallium zinc oxide (InxGayZnzO, commonly known as "IGZO"), indium gallium silicon oxide (InxGaySizO, commonly known as "IGSO"), and indium tungsten oxide (InxWyO, commonly known as "IWO").

In some embodiments, the size of the channel layer 410 along the first direction X is smaller than the size of the gate portion 501 along the first direction X. The size of the channel layer 410 along the first direction X may also be equal to the size of the gate portion 501 along the first direction X.

In some embodiments, as shown in FIG. 2a, FIG. 2a is a partial enlarged view of the area circled by the dotted circle in FIG. 1b, the word line structure 510 further includes a gate dielectric layer 503 located between the channel layer 410 and the gate portion 501. The size of the gate dielectric layer 503 along the first direction X may be less than or equal to the size of the gate portion 501 along the first direction X. The gate dielectric layer 503 covers the end surface S2 and at least a portion of the side wall S1 of the gate portion 501, and the channel layer 410 covers the surface of the gate dielectric layer 503 away from the gate portion 501. The channel layer 410 is flush with the end of the gate dielectric layer 503 facing the wire portion 502.

In some embodiments, referring to FIGS. 2b and 3 , FIG. 2a is another partial enlarged view of the area circled by the dotted circle in FIG. 1b , the gate portion 501 includes a first gate portion 501a, a second gate portion 501b and a third gate portion 501c sequentially connected along the first direction X, the first gate portion 501a is adjacent to the wire portion 502, and the third gate portion 501c is adjacent to the first capacitor structure 310; the cross-sectional area of the second gate portion 501b perpendicular to the first direction X is smaller than the cross-sectional area of the first gate portion 501a perpendicular to the first direction X, and the cross-sectional area of the second gate portion 501b perpendicular to the first direction X is smaller than the cross-sectional area of the third gate portion 501c perpendicular to the first direction X; the word line structure 510 also includes a gate dielectric layer 503 located between the second gate portion 501b, the third gate portion 501c and the channel layer 410.

The size of the first gate portion 501a and the third gate portion 501c is greater than the size of the second gate portion 501b. For example, the width of the first gate portion 501a and the third gate portion 501c along the second direction Y is greater than the width of the second gate portion 501b along the second direction Y. The gate portion 501 formed by the first gate portion 501a, the second gate portion 501b and the third gate portion 501c is dumbbell-shaped in cross section perpendicular to the vertical direction Z. The first gate portion 501a, the second gate portion 501b and the third gate portion 501c can be smoothly connected, that is, there is a connection section with a gradually decreasing cross-sectional area between the first gate portion 501a and the second gate portion 501b, and there is a connection section with a gradually increasing cross-sectional area between the second gate portion 501b and the third gate portion 501c.

The gate dielectric layer 503 may not cover or only partially cover the sidewall of the first gate portion 501a, and the channel layer 410 may only cover the gate dielectric layer 503 around the second gate portion 501b and the third gate portion 501c, but not the gate dielectric layer 503 around the first gate portion 501a, thereby increasing the distance between the channel layer 410 and the wire portion 502. The end of the gate dielectric layer 503 facing the wire portion 502 protrudes beyond the end of the channel layer 410 facing the wire portion 502, thereby preventing the channel layer 410 from contacting the gate portion 501.

In some embodiments, the bit line 210 is located on both sides of the second gate portion 501b along the second direction Y. Since the second gate portion 501b has a smaller size along the second direction Y, compared with the space between the third gate portions 501c, there is a larger space between the second gate portions 501b to accommodate the bit line 210, which can reduce the parasitic capacitance of adjacent bit lines 210 between the second gate portions 501b, reduce the coupling between the bit lines 210, and effectively improve the sensing margin of the semiconductor structure. The first gate portion 501a and a portion of the gate dielectric layer 503 are between the bit line 210 and the wire portion 502, which can reduce the parasitic capacitance between the bit line 210 and the wire portion 502.

In some embodiments, as shown in FIG. 3 , the spacing Wb1 between the bit lines 210 adjacent along the second direction Y is less than the spacing Wc between the channel layers 410 adjacent along the second direction Y, and the spacing Wb1,q between the adjacent bit lines 210 respectively contacting two adjacent channel layers 410 along the second direction Y is greater than the spacing Wb2 between the two bit lines 210 contacting the same channel layer 410; in the direction of the bit line 210 toward the contacted channel layer 410, the width of the bit line 210 along the first direction X gradually increases. The sidewalls of the bit line 210 toward the conductor portion 501 and toward the first capacitor structure 310 may be curved surfaces. The bit line 210 extends along the vertical direction Z and contacts the multi-channel layer 410 stacked in the vertical direction Z. The width of the sidewall of the bit line 210 contacting the channel layer 410 is greater than the width of the sidewall of the bit line 210 away from the channel layer 410. For example, the cross-sectional shape of the bit line 210 perpendicular to the vertical direction Z may be a trapezoid. By increasing the contact area between the bit line 210 and the channel layer 410 , the on-current of the transistor T1 can be increased, thereby effectively improving the sensing margin of the semiconductor structure.

In some embodiments, the two bit lines 210 on both sides of each transistor T1 are electrically connected, that is, the two bit lines 210 in contact with the same channel layer 410 are electrically connected. Contact plugs and connecting lines electrically connecting the two contact plugs can be respectively arranged on the top of the bit lines 210. The two bit lines 210 in contact with the same channel layer 410 are electrically connected by the contact plugs and the connecting lines, and the two bit lines 210 can be synchronously controlled, thereby improving the bit line control efficiency and the data reading and writing time of the semiconductor structure.

An embodiment of the present disclosure provides a method for preparing a semiconductor structure.

FIG4 is a flow chart of a method for preparing a semiconductor structure according to an embodiment of the present disclosure; FIG5a to FIG5l are schematic diagrams of a semiconductor structure preparation process according to an embodiment of the present disclosure. The method for preparing a semiconductor structure provided by an embodiment of the present disclosure will be described in detail below in conjunction with FIG4 and FIG5a to FIG5l. Referring to FIG4, the preparation method includes at least the following steps:

S110: forming a stack structure, the stack structure comprising a first stack layer and a second stack layer alternately stacked in a vertical direction, the stack structure comprising a plurality of memory cell regions extending in a first direction and arranged in a second direction, the memory cell region comprising a transistor region and a capacitor region arranged in the first direction;

S120: forming bit lines simultaneously on both sides of each transistor region along the second direction, wherein the bit lines extend along the vertical direction and penetrate the stacked structure;

S130: forming a first capacitor structure in a capacitor region in each first stacked layer;

S140: forming a channel layer and a word line structure in the transistor region of each first stacked layer, wherein the channel layer contacts the bit line and the first capacitor structure, and the channel layer at least covers a portion of the sidewall of the word line structure.

It should be understood that the steps shown in FIG. 4 are not exclusive, and other steps may be performed before, after or between any steps in the illustrated operation; the steps shown in FIG. 4 may be adjusted in order according to actual needs.

As shown in FIG. 5a , a stacked structure RR may be formed on a substrate (not shown in the figure), the material of the substrate including a semiconductor material, for example, a single semiconductor material (for example, silicon (Si) or germanium (Ge), etc.), a III-V compound semiconductor material (for example, gallium nitride (GaN), gallium arsenide (GaAs) or indium phosphide (InP), etc.), a II-VI compound semiconductor material (for example, zinc sulfide (ZnS), cadmium sulfide (CdS) or cadmium telluride (CdTe), etc.), an organic semiconductor material or other semiconductor materials known in the art. The stacked structure RR includes a first stacked layer 101′ and a second stacked layer 102′ alternately stacked along a vertical direction Z, and the materials of the first stacked layer 101′ and the second stacked layer 102′ may be insulating materials such as silicon oxide materials, silicon nitride materials, and silicon oxynitride materials. The materials of the first stacked layer 101′ and the second stacked layer 102′ are different, for example, the first stacked layer 101′ is a silicon nitride layer, and the second stacked layer 102′ is a silicon oxide layer. The formation process of the stacked structure RR includes a thin film deposition process, and the deposition process may include chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma enhanced ALD, physical vapor deposition (PVD), plasma enhanced chemical vapor deposition (PECVD) or low pressure chemical vapor deposition (LPCVD), etc.

In some embodiments, an etch stop layer may be formed on the substrate, and the stacked structure RR may be formed on the etch stop layer. The material of the etch stop layer includes polysilicon, metal oxide, nitride, etc. The etch stop layer may protect the substrate in subsequent processes.

In some embodiments, referring to Figures 5b to 5f, bit lines are formed simultaneously on both sides of each transistor region along the second direction in step S120, including: removing a portion of the stacked structure RR to form a first sacrificial pattern 103 located between the memory cell regions MR; forming a first groove 104 located between the transistor regions TR, the first groove 104 penetrates the first sacrificial pattern 103, and the size of the first groove 104 along the second direction Y is greater than or equal to the size of the first sacrificial pattern 103 along the second direction; forming an initial bit line layer 210' on the inner wall of the first groove 104, and forming a protective layer 220 on the inner wall of the initial bit line layer 210'; removing the first sacrificial pattern 103 to form an etched groove 105, the etched groove exposing a portion of the sidewall of the initial bit line layer 210'; removing a portion of the initial bit line layer 210' along the etched groove 105, and retaining the portion of the initial bit line layer 210' located on both sides of each transistor region TR along the second direction Y as the bit line 210.

5b, the stacked structure RR can be divided into a memory cell region MR and an isolation region IR, a plurality of memory cell regions MR are arranged at intervals along the second direction Y, and each memory cell region MR extends along the first direction X. The memory cell region MR includes a transistor region TR and a capacitor region CR connected to each other, and the transistor region TR and the capacitor region CR are arranged along the first direction X. The transistor region TR is used to form a transistor and the capacitor region CR is used to form a capacitor structure. A portion of the stacked structure RR located in the isolation region IR is removed to form an opening that penetrates the stacked structure RR, and the opening can expose the etch stop layer located below the stacked structure RR to form a first sacrificial pattern 103 that fills the opening.

5c, a portion of the first sacrificial pattern 103 is removed to form a first groove 104, the first groove 104 is located between the transistor regions TR, and the size of the first groove 104 along the first direction X is smaller than the size of the transistor region TR along the first direction X, that is, a portion of the first sacrificial pattern 103 is retained on both sides of the first groove 104 along the first direction X. The size of the first groove 104 along the second direction Y is equal to the size of the first sacrificial pattern 103 along the second direction Y, and the sidewall of the first groove 104 along the second direction Y is flush with the sidewall of the first sacrificial pattern 103 along the second direction Y.

In other embodiments, the size of the first slot 104 along the second direction Y may be greater than the size of the first sacrificial pattern 103 along the second direction Y. Both side walls of the first slot 104 along the second direction Y protrude from the two side walls of the first sacrificial pattern 103 along the second direction Y, the projection of the first slot 104 along the first direction X completely overlaps with the projection of the first sacrificial pattern 103 along the first direction X, and the transistor region TR remains rectangular. Alternatively, one of the two side walls of the first slot 104 along the second direction Y is flush with one side wall of the first sacrificial pattern 103 along the second direction Y, and the other of the two side walls of the first slot 104 along the second direction Y protrudes from the other side wall of the first sacrificial pattern 103 along the second direction Y along the second direction Y, the projection of the first slot 104 along the first direction X covers the projection of the first sacrificial pattern 103 along the first direction X, and the transistor region TR may be polygonal in shape, for example, may be dumbbell-shaped.

In some embodiments, the first slot 104 and the second sacrificial pattern located in the first slot 104 may be formed first, the first sacrificial pattern 103 may be formed, and the second sacrificial pattern may be removed to expose the first slot 104. Alternatively, an opening corresponding to the first sacrificial pattern 103 may be formed first, a second sacrificial pattern corresponding to the first slot 104 may be formed in the opening, the remaining portion of the opening may be filled with the first sacrificial pattern 103, and the second sacrificial pattern may be removed to form the first slot 104. The present disclosure does not limit the order of forming the first slot 104 and the first sacrificial pattern 103.

The first sacrificial pattern 103 and the second sacrificial pattern can be made of dielectric materials such as polysilicon, phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, tetraethyl orthosilicate (TEOS), and aluminum oxide (AlOx). The first sacrificial pattern 103 and the second sacrificial pattern are made of different materials, and are both different from the materials of the first stacked layer 101' and the second stacked layer 102'. For example, the material of the first sacrificial pattern 103 can be aluminum oxide, and the second sacrificial pattern can be polysilicon.

As shown in FIG. 5d , an initial bit line layer 210 ′ is formed on the inner wall of the first slot 104, the initial bit line layer 210 ′ is in contact with the first stacked layer 101 ′ and the second stacked layer 102 ′, a protective layer 220 is formed on the inner wall of the initial bit line layer 210 ′, and the initial bit line layer 210 ′ and the protective layer 220 fill the first slot 104. The initial bit line layer 210 ′ may be a conductive material, such as one or more of the following: metal (e.g., tungsten (W), titanium (Ti), tantalum (Ta), ruthenium (Ru), cobalt (Co), molybdenum (Mo), etc.), conductive metal nitride (e.g., titanium nitride), tantalum nitride, etc.) and metal-semiconductor compound (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.). The protective layer 220 may be an insulating material such as a silicon oxide material or a silicon nitride material, and the material of the protective layer 220 is different from the material of the first sacrificial pattern 103.

In some embodiments, before forming the protective layer 220, an anisotropic etching process along the vertical direction Z can be used to remove a portion of the initial bit line layer 210' covering the top surface of the stacked structure RR and a portion of the initial bit line layer 210' at the bottom of the first groove 104, leaving only the initial bit line layer 210' located on the inner side wall of the first groove 104.

Referring to FIG. 5e , the first sacrificial pattern 103 is removed to form an etched groove 105, which exposes a portion of the sidewall of the initial bit line layer 210 ′. The etched groove 105 is located on both sides of the initial bit line layer 210 ′ along the first direction X, and exposes the two sidewalls of the initial bit line layer 210 ′ in the first direction X. Referring to FIG. 5f , wet etching is performed along the etched groove 105 to remove the two sidewalls of the initial bit line layer 210 ′ along the first direction X, and the portions of the initial bit line layer 210 ′ located on both sides of each transistor region TR along the second direction Y are retained as the bit line 210. Two separate bit lines 210 are retained in each first groove 104. Due to the lateral etching load effect, the etching rate of the initial bit line layer 210' close to the side wall of the etching groove 105 along the second direction Y is relatively low, so that in the direction of the bit line 210 toward the contacted transistor region TR, the width of the retained bit line 210 along the first direction X can be gradually increased, for example, the side wall of the bit line 210 toward the wire portion 501 and toward the first capacitor structure 310 can be a curved surface. Referring to FIG. 5g, after the bit line 210 is formed, the isolation pattern 106 is filled in the etching groove 105. The material of the isolation pattern 106 can be a dielectric material such as polysilicon, phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, tetraethyl orthosilicate (TEOS), aluminum oxide (AlOx), etc. The isolation pattern 106 is different from the material of the first stacked layer 101' and the second stacked layer 102', for example, the material of the isolation pattern 106 can be polysilicon.

As shown in FIG. 5h , the capacitor region CR in each first stacking layer 101 ′ forms a first capacitor structure 310. The isolation pattern 106 divides the stacking structure RR of the capacitor region CR into a plurality of parts arranged at intervals along the second direction Y, and an opening penetrating the stacking structure RR is formed at one end of the plurality of capacitor regions CR along the first direction X, and the first stacking layer 101 ′ of the capacitor region CR is removed by lateral etching along the opening to form a first space, and the second electrode portion 303, the first dielectric layer 302 and the first electrode portion 301 are sequentially deposited in the first space. The second electrode portion 303 contacts the remaining first stacking layer 101 ′ and the second stacking layer 102 ′. Taking the second electrode portion 303 as a cylindrical structure as an example, the first dielectric layer 302 conformally covers the inner wall of the second electrode portion 303, the first electrode portion 301 is filled in the first dielectric layer 302, and the first dielectric layer 302 is sandwiched between the first electrode portion 301 and the second electrode portion 303. The first electrode portion 301 includes a columnar conductive portion 301 a located in each capacitor region CR and a plate-shaped conductive portion 301 b located in an opening at an end of each capacitor region CR.

In some embodiments, referring to FIG. 1b, after forming the first capacitor structure 310, it also includes: removing part of the isolation pattern 106 to form an opening that penetrates the stacked structure RR, forming a second capacitor structure 320 in the opening, the second capacitor structure 320 is located between the first capacitor structure 310, and the first capacitor structure 310 and the second capacitor structure 320 are alternately arranged along the second direction Y and contact each other. The second capacitor structure 320 includes a third electrode portion 304 and a second dielectric layer 305. The third electrode portion 304 is electrically connected to the first electrode portion 301, and the first capacitor structure 310 and the second capacitor structure 320 are used to jointly constitute a capacitor structure C1. By setting the second capacitor structure 320, the area directly facing the third electrode portion 304 and the second electrode portion 303 is increased, so that the overall capacitance of the capacitor structure C1 jointly constituted by the second capacitor structure 320 and the first capacitor structure 310 can be improved. By first forming the first capacitor structure 310 and then forming the second capacitor structure 320, it is ensured that when the first capacitor structure 310 is formed, the second electrode portion 303 has the second stacked layer 102' as support, which can avoid the collapse of the second electrode portion 303 and improve the structural stability of the first capacitor structure 310.

In some embodiments, after removing part of the isolation pattern 106 to form an opening penetrating the stacking structure RR, lateral etching is performed along the opening to remove the second stacking layer 102' between the first capacitor structures 310 in the vertical direction Z, thereby forming an overall space exposing the side walls of the first capacitor structure 310 along the vertical direction Z and along the second direction Y, and a second dielectric layer 305 and a third electrode portion 304 covering the second electrode portion 303 are sequentially deposited in the overall space to form a second capacitor structure 320 surrounding the first capacitor structure 310, thereby further increasing the capacitance of the capacitor structure C1.

In some embodiments, referring to Figures 5i to 5l, in step S140, a channel layer 410 and a word line structure 510 are formed in the transistor region TR in each first stacked layer 101', including: removing a portion of the first stacked layer 101' located in the transistor region TR to form a second groove 101e; forming an initial channel layer 410' on the inner wall of the second groove 101e; forming a gate dielectric layer 503 and a gate portion 501 covering the initial channel layer 410' in the transistor region TR; removing the exposed portion of the initial channel layer 410' to form a channel layer 410; forming a wire portion 502 extending along the second direction Y, and the wire portion 502 is in contact with a plurality of gate portions 501 arranged along the second direction Y.

As shown in FIG. 5i, an opening may be formed at the end of the transistor region TR away from the capacitor region CR, and a portion of the first stacked layer 101' located in the transistor region TR may be removed by etching laterally along the opening to form a second groove 101e. The second groove 101e exposes the third electrode portion 303 of the first capacitor structure 310 and the sidewall of the bit line 210 along the second direction Y. The projection of the second groove 101 in the vertical direction Z is comb-shaped, and the tooth-shaped groove of the second groove 101 extends from the opening at the end of the capacitor region CR toward the first capacitor structure 310.

As shown in FIG5j, an initial channel layer 410' is formed on the inner wall of the second groove 101e by a deposition process, and the initial channel layer 410' is in contact with the bit line 210 and the third electrode portion 303 of the first capacitor structure 310. The initial channel layer 410' also covers the surface of the isolation pattern 106 exposed by the second groove 101e, and the initial channel layer 410' extends as a whole in the second direction Y. The deposition process may include chemical vapor deposition, atomic layer deposition process, plasma enhancement, physical vapor deposition, plasma enhanced chemical vapor deposition or low pressure chemical vapor deposition. The material of the initial channel layer 410' includes one or more of the following: silicon (e.g., monocrystalline silicon, polycrystalline silicon), germanium, silicon germanium and oxide semiconductor materials (e.g., zinc tin oxide, indium zinc oxide, zinc oxide, indium gallium zinc oxide, indium gallium silicon oxide, indium tungsten oxide).

As shown in FIG. 5k , an initial gate dielectric layer covering the initial channel layer 410 ′ and an initial gate portion covering the initial gate dielectric layer are formed in the transistor region TR, and the initial channel layer 410 ′, the initial gate dielectric layer and the initial gate portion fill the second groove 101e. The initial gate dielectric layer extends as a whole in the second direction Y, and the initial gate portion extends as a whole in the second direction Y. The initial gate portion is etched laterally along the opening of the end of the capacitor region CR, and only part of the initial gate portion located in the toothed groove of the second groove 101 is retained as the gate portion 501, that is, each gate portion 501 is arranged at intervals along the second direction Y and arranged at intervals along the vertical direction Z, and the gate portion 501 is arranged in an array along the second direction Y and the vertical direction Z. The gate portion 501 exposes the initial gate dielectric layer, and with the gate portion 501 as a protective structure, the initial gate dielectric layer is etched laterally along the opening of the end of the capacitor region CR until the initial channel layer 410 ′ is exposed. For example, the size of the retained gate dielectric layer 503 in the first direction X is smaller than the size of the transistor region TR in the first direction X. With the gate portion 501 and the gate dielectric layer 503 as protection structures, the exposed portion of the initial channel layer 410' is removed by lateral etching along the opening of the end of the capacitor region CR, and at least the portion of the initial channel layer 410' contacting the bit line 210 and the first capacitor structure 310 is retained to form a channel layer 410, and the size of the channel layer 410 in the first direction X is smaller than the size of the gate dielectric layer 503 in the first direction X.

In some embodiments, as shown in FIG. 3 , the gate portion 501 includes a first gate portion 501a, a second gate portion 501b, and a third gate portion 501c, the third gate portion 501c being sequentially connected along a first direction X. The gate dielectric layer 503 may be located on the sidewalls of the second gate portion 501b, the third gate portion 501c, and a portion of the sidewalls of the first gate portion 501a, and the channel layer 410 may be located only on the periphery of the second gate portion 501b and the third gate portion 501c.

In some embodiments, referring to Figure 5c and Figure 3, when the size of the first groove 104 along the second direction Y may be larger than the size of the first sacrificial pattern 103 along the second direction Y, the widths of the formed first gate portion 501a and the third gate portion 501c along the second direction Y are larger than the width of the second gate portion 501b along the second direction Y, and the gate portion 501 formed by the first gate portion 501a, the second gate portion 501b and the third gate portion 501c as a whole has a dumbbell-shaped cross-sectional shape perpendicular to the vertical direction Z.

In some embodiments, as shown in FIG. 51, a wire portion 502 extending along the second direction Y is formed, and the wire portion 502 contacts a plurality of gate portions 501 arranged along the second direction Y, and the wire portion 502 may be made of the same material as the gate portion 501. The wire portion 502 may be formed in an opening at the end of the transistor region TR away from the capacitor region CR. Before forming the wire portion 502, an insulating material may also be deposited at the end of the channel layer 410 facing the opening to isolate the wire portion 502 from the channel layer 410. The wire portion 502, the gate portion 501, and the gate dielectric layer 503 together constitute a word line structure 510, and the gate portion 501 and the gate dielectric layer 503 of the word line structure 510 are embedded in the channel layer 410 to form a transistor T1 with a channel-all-around structure (CAA). The semiconductor structure 100 includes storage layers 101 spaced apart in a vertical direction Z, and each storage layer 101 includes a plurality of transistors T1 and a plurality of first capacitor structures 310, the transistors T1 and the first capacitor structures 310 are arranged one by one along a first direction X, and one transistor T1 and one corresponding first capacitor structure 310 constitute a storage unit M1. The plurality of storage units M1 are sequentially spaced apart and arranged along a second direction Y, and each storage unit M1 extends along the first direction X.

In some embodiments, as shown in FIG. 51, the protective layer 220 and the isolation pattern 106 are replaced with an insulating material to form an isolation structure 107, and the insulating material can be a low dielectric constant material, including but not limited to silicon oxide, silicon nitride, silicon carbide, silicon carbide nitride or silicon oxynitride. The isolation structure 107 can be a columnar structure extending along the vertical direction Z. The second stacked layer 102' can also be replaced with an insulating material to form a spacer layer 102, and the spacer layer 102 and the isolation structure 107 can be integrally formed, and the spacer layer 102 and the isolation structure 107 can surround the sidewalls of the transistor T1 and/or the first capacitor structure 310. By providing a low dielectric constant material in the isolation region IR between the transistor regions TR, the coupling between adjacent transistors T1 can be reduced, and the parasitic capacitance between adjacent bit lines 210 can be reduced, thereby reducing the power consumption of the semiconductor structure.

In some embodiments, the semiconductor structure 100 includes: a memory, which may be a dynamic random access memory, or a memory known in the art, such as a phase change memory or a ferroelectric memory.

The various semiconductor structures shown in this specific embodiment can be used in electronic devices with storage functions. The electronic device can be a terminal device, such as a mobile phone, a tablet computer, a smart bracelet, or a personal computer (PC), a server, a workstation, etc. The storage function in the electronic device can be implemented by the following memories: dynamic random access memory (DRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), magnetic random access memory (MRAM) or resistive random access memory (RRAM).

The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims (10)

1. A semiconductor structure, comprising:

A plurality of memory layers stacked in a vertical direction, each memory layer including a plurality of memory cells extending in a first direction and arranged in a second direction, the memory cells including a transistor and a first capacitance structure arranged in the first direction, the transistor including a channel layer and a word line structure, the channel layer covering at least a portion of a sidewall of the word line structure;

And bit lines extending along the vertical direction, wherein the bit lines are positioned on two sides of each transistor along the second direction, and the bit lines are in contact with the channel layer.

2. The semiconductor structure of claim 1, wherein the word line structure comprises a wire portion and a gate portion connected to each other, the wire portion extending in a second direction, the gate portion being located on a side of the wire portion in the first direction, the channel layer surrounding a sidewall of the gate portion and an end face toward the first capacitance structure, a dimension of the channel layer in the first direction being smaller than a dimension of the gate portion in the first direction.

3. The semiconductor structure of claim 2, wherein the gate portion comprises a first gate portion, a second gate portion, and a third gate portion connected in sequence along a first direction, the first gate portion being adjacent to the wire portion, the third gate portion being adjacent to the first capacitance structure;

The cross-sectional area of the second gate portion perpendicular to the first direction is smaller than the cross-sectional area of the first gate portion perpendicular to the first direction, and the cross-sectional area of the second gate portion perpendicular to the first direction is smaller than the cross-sectional area of the third gate portion perpendicular to the first direction;

the word line structure further includes a gate dielectric layer between the second gate portion, the third gate portion, and the channel layer.

4. The semiconductor structure of claim 3, wherein the bit line is located on both sides of the second gate portion along the second direction.

5. The semiconductor structure of any of claims 1-4, wherein a pitch between adjacent bit lines along the second direction is smaller than a pitch between adjacent channel layers along the second direction, and a pitch between adjacent bit lines respectively in contact with two adjacent channel layers along the second direction is larger than a pitch between two bit lines in contact with the same channel layer;

the width of the bit line in the first direction is gradually increased in a direction of the bit line toward the contacted channel layer.

6. The semiconductor structure of any of claims 1-4, wherein two bit lines on either side of each transistor are electrically connected.

7. The semiconductor structure of any of claims 1-4, further comprising: and the second capacitor structures are positioned between the first capacitor structures, and the first capacitor structures and the second capacitor structures are alternately arranged along the second direction and are contacted with each other.

8. A method of fabricating a semiconductor structure, comprising:

Forming a stack structure including a first stack layer and a second stack layer alternately stacked in a vertical direction, the stack structure including a plurality of memory cell regions extending in a first direction and arranged in a second direction, the memory cell regions including transistor regions and capacitor regions arranged in the first direction;

simultaneously forming bit lines on two sides of each transistor region along the second direction, wherein the bit lines extend along the vertical direction and penetrate through the stacked structure;

forming a first capacitor structure in the capacitor region in each of the first stacked layers;

The transistor region in each of the first stacked layers forms a channel layer and a word line structure, the channel layer being in contact with the bit line and the first capacitance structure, the channel layer covering at least a portion of a sidewall of the word line structure.

9. The method of manufacturing according to claim 8, wherein forming bit lines simultaneously on both sides of each of the transistor regions in the second direction comprises:

Removing a portion of the stack structure to form a first sacrificial pattern between the memory cell regions;

Forming first grooves between transistor regions, the first grooves penetrating through the first sacrificial patterns, and the first grooves having a size along the second direction that is greater than or equal to the size of the first sacrificial patterns along the second direction;

Forming an initial bit line layer on the inner wall of the first slot, and forming a protective layer on the inner wall of the initial bit line layer;

removing the first sacrificial pattern to form an etched trench, wherein the etched trench exposes a part of the side wall of the initial bit line layer;

And removing part of the initial bit line layer along the etched groove, and reserving the part of the initial bit line layer, which is positioned at two sides of each transistor area along the second direction, as a bit line.

10. The method of manufacturing of claim 8, wherein forming the transistor region in each of the first stacked layers into a channel layer and a word line structure comprises:

Removing a portion of the first stack layer in the transistor region to form a second trench;

Forming an initial channel layer on the inner wall of the second groove;

forming a gate dielectric layer and a gate portion in the transistor region to cover the initial channel layer;

Removing a portion of the exposed initial channel layer to form a channel layer;

And forming a wire part extending along the second direction, wherein the wire part is contacted with the grid parts arranged along the second direction.