CN118473417A - Unipolar code analog decoding circuit - Google Patents
Unipolar code analog decoding circuit Download PDFInfo
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- CN118473417A CN118473417A CN202410910386.3A CN202410910386A CN118473417A CN 118473417 A CN118473417 A CN 118473417A CN 202410910386 A CN202410910386 A CN 202410910386A CN 118473417 A CN118473417 A CN 118473417A
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M5/00—Conversion of the form of the representation of individual digits
- H03M5/02—Conversion to or from representation by pulses
- H03M5/04—Conversion to or from representation by pulses the pulses having two levels
- H03M5/06—Code representation, e.g. transition, for a given bit cell depending only on the information in that bit cell
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Abstract
The invention discloses a unipolar code analog decoding circuit, which belongs to the technical field of basic circuit design, and the circuit converts a unipolar analog code stream VSIG transmitted by a medium into a digital signal VD, and comprises a front-end amplifying circuit, a band-gap reference source circuit, a comparison threshold selecting circuit and a comparator; the front-end amplifying circuit is operative to amplify the received analog signal VSIG into an analog voltage VA superimposed on the common mode level and input to the positive input terminal of the comparator. On the basis of applying a traditional operational amplifier circuit, the unipolar code analog decoding circuit disclosed by the invention is used for comparing a signal after being amplified by an operational amplifier input in a non-inverting way with an analog reference voltage VREF by using a comparator, so that decoding is completed to generate a digital code stream. The structure has low power consumption, simple structure and convenient mass production.
Description
Technical Field
The invention belongs to the technical field of basic circuit design, and particularly relates to a unipolar code analog decoding circuit.
Background
Nowadays, with the rapid development of various communication systems and technologies including mobile communication and optical fiber communication, wireless local area networks have become hot spots for research and development of universities, research institutes and communication related industries worldwide by decoding digital signals after channel transmission. The signal receiver is an active circuit whose main function is to amplify the analog signal, provide appropriate gain to overcome noise of subsequent circuits, and convert the analog signal to digital symbols for subsequent digital baseband use. It should not only have very low noise, high gain, but also provide a sufficiently high linearity.
Transmission of unipolar codes, NRZ (non return to zero) codes, return to zero (RZ) codes, etc. over various media (radio waves, optical fibers, cables) often requires that their code streams be transmitted superimposed on a high frequency carrier. Therefore, the corresponding analog receiver must demodulate the digital code stream received by the corresponding analog receiver from the carrier wave and then digitally decode the digital code stream, and the system needs to use an analog front-end amplifier, a down-conversion circuit, an analog baseband processing circuit and an analog-to-digital converter (ADC), which is complex in circuit and high in power consumption.
Single-stage analog signal transmission is characterized by the use of voltages of only one polarity to characterize binary data. In unipolar coding, a high level represents a binary "1", and a zero level or line idle state represents a binary "0". Thus, for such a signal, only a simple analog decoding circuit is required to implement.
Disclosure of Invention
The invention aims to provide a unipolar code analog decoding circuit which uses an operational amplifier and a comparator which are input in the same phase to carry out digital decoding on the basis of the traditional operational amplifier, does not need to use a complex receiver circuit including an ADC, can be realized by only a simple analog decoding circuit, and can well solve the problems in the background technology.
In order to achieve the above purpose, the present invention provides the following technical solutions: a unipolar code analog decoding circuit converts a unipolar analog code stream VSIG transmitted from a medium into a digital signal VD, and includes a front-end amplifying circuit, a band gap reference source circuit, a comparison threshold selecting circuit and a comparator;
The front-end amplifying circuit is operative to amplify the received analog signal VSIG into an analog voltage VA superimposed on a common mode level and input the analog voltage VA to the positive input terminal of the comparator; the bandgap reference source circuit and the comparison threshold circuit jointly act to generate a reference voltage VREF, the reference voltage VREF is input to the negative input end of the comparator, and the analog voltage VA and the reference voltage VREF are compared through the comparator to output a digital code VD.
Preferably, the front-end amplifying circuit comprises a straightening capacitor C1, a resistor R8, a resistor R1, an operational amplifier OPA1, a resistor R2, a variable resistor R3 and a capacitor C2;
When the DC-DC converter works, an analog signal VSIG generates an alternating current signal after passing through the DC-DC converter C1; the common mode voltage VCOM generates a dc bias to the ac signal through the resistor R8, then the ac signal is applied to the non-inverting input terminal of the operational amplifier OPA1 through the resistor R1, and finally the operational amplifier OPA1 outputs the analog voltage VA to the positive input terminal of the comparator; in the process, the resistor R2, the variable resistor R3 and the OPA1 form a variable gain amplifying circuit for adjusting the gain of the operational amplifier OPA 1; the capacitor C2 and the variable resistor R3 form a low-pass filter loop for filtering the high-frequency interference of the operational amplifier OPA 1.
Preferably, a band gap reference source circuit is arranged in the band gap reference source, and comprises PNP tertiary pipes Q1, Q2 and Q3, an operational amplifier OPA4, PMOS pipes M8, M9 and M10 and resistors R4 and R5;
One end of the operational amplifier OPA4 is connected with the emitter of the PNP transistor Q1, and the other end is connected with the resistor R4; during operation, PTAT current which varies positively with temperature is generated on the PMOS tubes M8, M9 and M10, PTAT voltage which varies positively with temperature is generated on the resistor R5, and voltage on the PNP transistor Q3 is CTAT voltage which varies negatively with temperature.
Preferably, the comparator threshold selection circuit comprises operational amplifiers OPA5, OPA6, variable resistors R6, R7 and a PMOS tube M11;
When the band-gap reference voltage VBG generated by the band-gap reference source circuit works, variable voltage is generated on a voltage dividing circuit formed by the R6 and the R7 through the operational amplifier OPA5, the variable resistors R6 and R7 and the PMOS tube M11 and is transmitted to the operational amplifier OPA6, and then the reference voltage VREF is formed through gain buffering of the operational amplifier OPA6 and is transmitted to the negative input end of the comparator.
Preferably, a comparator circuit is arranged in the comparator, and the comparator circuit comprises current sources I1 and I2, PMOS tubes M1, M2, M3, M4, M5, M6 and M7 and an inverter INV1;
The PMOS tubes M1 and M2 are input pair tubes of the comparator circuit and are respectively used for receiving an analog voltage VA generated by the front-end amplifying circuit and a comparison voltage VREF generated by the comparator threshold selecting circuit; the width-to-length ratio of the PMOS tubes M3 and M4 is larger than that of the PMOS tubes M5 and M6, so that an active load with a hysteresis function is formed; the PMOS transistor M7, the current source I2, and the inverter INV1 form a two-stage amplifying circuit for amplifying, shaping, and outputting the digital level VD from the analog output of the comparator circuit.
Preferably, the PMOS transistors M1 and M2 in the comparator circuit are also grounded through the current source I1.
Preferably, the front-end amplifying circuit, the band gap reference source, the comparison threshold selecting circuit and the comparator have a common ground VSS and power supply VDD.
Compared with the prior art, the invention has the beneficial effects that:
The analog decoding circuit of the unipolar code can amplify signals and then superimpose the signals on the common-mode voltage of the front-end amplifier, and then compare the signals with the common-mode level to obtain a data code stream, wherein the common-mode level of the amplifier is determined by the reference voltage VREF.
The unipolar code analog decoding circuit has the characteristic of monolithic integration, and on the basis of applying a traditional operational amplifier circuit, after a signal is amplified by an operational amplifier input in a non-inverting way, the signal is compared with an analog reference voltage VREF by using a comparator, so that decoding is completed to generate a digital code stream; the structure has low power consumption and simple structure, and is convenient for large-scale mass production.
Drawings
Fig. 1 is a block diagram of an analog decoding circuit according to the present invention.
Fig. 2 is a front-end amplification circuit diagram in an analog decoding circuit.
Fig. 3 is a block diagram of a low offset operational amplifier circuit in the front-end amplifier circuit.
Fig. 4 is a circuit diagram of a comparator in an analog decoding circuit.
Fig. 5 is a circuit diagram of a bandgap reference source in an analog decoding circuit.
Fig. 6 is a diagram of a comparator threshold selection circuit in an analog decoding circuit.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
As shown in fig. 1, the present embodiment provides a unipolar code analog decoding circuit, which converts a unipolar analog code stream VSIG transmitted from a medium into a digital signal VD, and includes a front-end amplifying circuit, a bandgap reference circuit, a comparison threshold selecting circuit and a comparator;
The front-end amplifying circuit is operative to amplify the received analog signal VSIG into an analog voltage VA superimposed on a common mode level and input the analog voltage VA to the positive input terminal of the comparator; the bandgap reference source circuit and the comparison threshold circuit jointly act to generate a reference voltage VREF, the reference voltage VREF is input to the negative input end of the comparator, and the analog voltage VA and the reference voltage VREF are compared through the comparator to output a digital code VD.
Specifically, as shown in fig. 2, the front-end amplifying circuit includes a straightening capacitor C1, a resistor R8, a resistor R1, an operational amplifier OPA1, a resistor R2, a variable resistor R3, and a capacitor C2;
When the DC-DC converter works, an analog signal VSIG generates an alternating current signal after passing through the DC-DC converter C1; the common mode voltage VCOM generates a dc bias to the ac signal through the resistor R8, then the ac signal is applied to the non-inverting input terminal of the operational amplifier OPA1 through the resistor R1, and finally the operational amplifier OPA1 outputs the analog voltage VA to the positive input terminal of the comparator; in the process, the resistor R2, the variable resistor R3 and the OPA1 form a variable gain amplifying circuit for adjusting the gain of the operational amplifier OPA 1; and the capacitor C2 and the variable resistor R3 form a low-pass filter loop for filtering high-frequency interference of the operational amplifier OPA1, so that the input impedance of the in-phase amplifier is very high, and the signal attenuation in the transmission process of the system is reduced.
Specifically, as shown in fig. 3, the present embodiment also provides an operational amplifier circuit applied to a front-end amplifying circuit, and since the front-end amplifying circuit is a variable gain amplifier, the adjusting gain is often tens of times higher, so that the input dc offset of the operational amplifying circuit can be amplified to tens of mV, and if the auto-zeroing offset-eliminating circuit is not used in the operational amplifier, the comparator at the rear stage can generate a larger comparison error. OPA2 is the main amplifier of the zeroing operational amplifier and OPA3 is the auxiliary amplifier of the zeroing operational amplifier, both of which can be implemented with conventional differential operational amplifier circuits. In this structure, DC offset (direct current offset) of OPA2 in the main signal path is suppressed by the amplification gain of OPA3, thereby reducing the offset of the entire signal path. When CK1 is high, SW1, SW4 are on, the auxiliary amplifier is disconnected from the main signal path to make its own correction, and the correction voltages are stored on C3, C4. When CK2 is high, SW2, SW3 are turned on, and auxiliary amplifier OPA3 is reconnected to the main signal path, thereby detecting an input offset of main op-amp OPA2, which is stored on C5, C6. After a number of CK1, CK2 switches, the input offset on the main signal path is gradually reduced to a small value.
Specifically, as shown in fig. 4, the present embodiment further provides a comparator circuit applied in a comparator, where the comparator circuit includes current sources I1, I2, PMOS transistors M1, M2, M3, M4, M5, M6, M7, and an inverter INV1;
The PMOS tubes M1 and M2 are input pair tubes of the comparator circuit and are respectively used for receiving an analog voltage VA generated by the front-end amplifying circuit and a comparison voltage VREF generated by the comparator threshold selecting circuit; the width-to-length ratio of the PMOS tubes M3 and M4 is larger than that of the PMOS tubes M5 and M6, so that an active load with a hysteresis function is formed; the PMOS tube M7, the current source I2 and the inverter INV1 form a two-stage amplifying circuit which is used for amplifying, shaping and outputting digital level VD of the analog output of the comparator circuit, and the comparator compares VA with VREF, and the common mode voltage of the two is close to VCOM, so that decoding errors caused by certain direct current bias are avoided.
Specifically, as shown in fig. 5, the present embodiment further provides a bandgap reference source circuit applied in the bandgap reference source, where the bandgap reference source circuit includes PNP transistors Q1, Q2, Q3, an operational amplifier OPA4, PMOS transistors M8, M9, M10, and resistors R4, R5;
One end of the operational amplifier OPA4 is connected with the emitter of the PNP transistor Q1, and the other end is connected with the resistor R4; during operation, PTAT current which varies positively with temperature is generated on the PMOS tubes M8, M9 and M10, PTAT voltage which varies positively with temperature is generated on the resistor R5, and voltage on the PNP transistor Q3 is CTAT voltage which varies negatively with temperature. Therefore, the positive temperature coefficient of the voltage on the resistor R5 is offset with the negative temperature coefficient on the PNP transistor Q3, so that the output voltage VBG is a zero temperature coefficient band gap reference source.
Specifically, as shown in fig. 6, the comparator threshold selection circuit includes operational amplifiers OPA5 and OPA6, variable resistors R6 and R7, and a PMOS transistor M11;
When the band-gap reference voltage VBG generated by the band-gap reference source circuit works, variable voltage is generated on a voltage dividing circuit formed by the R6 and the R7 through the operational amplifier OPA5, the variable resistors R6 and R7 and the PMOS tube M11 and is transmitted to the operational amplifier OPA6, and then the reference voltage VREF is formed through gain buffering of the operational amplifier OPA6 and is transmitted to the negative input end of the comparator. In this process, OPA5 acts to equalize the VC1 voltage with VBG and to isolate VBG from the impedance of the later stage voltage dividing circuit; and the resistors R6 and R7 are used as variable resistance circuits, and the VC2 output voltage is selected through a set of switches. The operational amplifier OPA6 is formed as a unity gain buffer and outputs a reference voltage VREF to be used by a comparator circuit of the comparator.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various modifications and variations can be made to the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.
Claims (7)
1. The unipolar code analog decoding circuit is characterized by converting a unipolar analog code stream VSIG transmitted by a medium into a digital signal VD, and comprises a front-end amplifying circuit, a band-gap reference source circuit, a comparison threshold selecting circuit and a comparator;
The front-end amplifying circuit is operative to amplify the received analog signal VSIG into an analog voltage VA superimposed on a common mode level and input the analog voltage VA to the positive input terminal of the comparator; the bandgap reference source circuit and the comparison threshold circuit jointly act to generate a reference voltage VREF, the reference voltage VREF is input to the negative input end of the comparator, and the analog voltage VA and the reference voltage VREF are compared through the comparator to output a digital code VD.
2. The unipolar code analog decoding circuit of claim 1, wherein the front-end amplification circuit includes a straightening capacitor C1, a resistor R8, a resistor R1, an operational amplifier OPA1, a resistor R2, a variable resistor R3, and a capacitor C2;
When the DC-DC converter works, an analog signal VSIG generates an alternating current signal after passing through the DC-DC converter C1; the common mode voltage VCOM generates a dc bias to the ac signal through the resistor R8, then the ac signal is applied to the non-inverting input terminal of the operational amplifier OPA1 through the resistor R1, and finally the operational amplifier OPA1 outputs the analog voltage VA to the positive input terminal of the comparator; in the process, the resistor R2, the variable resistor R3 and the OPA1 form a variable gain amplifying circuit for adjusting the gain of the operational amplifier OPA 1; the capacitor C2 and the variable resistor R3 form a low-pass filter loop for filtering the high-frequency interference of the operational amplifier OPA 1.
3. The unipolar code analog decoding circuit of claim 2, wherein the bandgap reference source has a bandgap reference source circuit therein, the bandgap reference source circuit including PNP transistors Q1, Q2, Q3, operational amplifier OPA4, PMOS transistors M8, M9, M10 and resistors R4, R5;
One end of the operational amplifier OPA4 is connected with the emitter of the PNP transistor Q1, and the other end is connected with the resistor R4; during operation, PTAT current which varies positively with temperature is generated on the PMOS tubes M8, M9 and M10, PTAT voltage which varies positively with temperature is generated on the resistor R5, and voltage on the PNP transistor Q3 is CTAT voltage which varies negatively with temperature.
4. A unipolar code analog decoding circuit according to claim 3, the comparator threshold selection circuit including operational amplifiers OPA5, OPA6, varistors R6, R7 and PMOS transistor M11;
When the band-gap reference voltage VBG generated by the band-gap reference source circuit works, variable voltage is generated on a voltage dividing circuit formed by the R6 and the R7 through the operational amplifier OPA5, the variable resistors R6 and R7 and the PMOS tube M11 and is transmitted to the operational amplifier OPA6, and then the reference voltage VREF is formed through gain buffering of the operational amplifier OPA6 and is transmitted to the negative input end of the comparator.
5. The unipolar code analog decoding circuit of claim 4, wherein the comparator has a comparator circuit therein, the comparator circuit including current sources I1, I2, PMOS transistors M1, M2, M3, M4, M5, M6, M7 and inverter INV1;
The PMOS tubes M1 and M2 are input pair tubes of the comparator circuit and are respectively used for receiving an analog voltage VA generated by the front-end amplifying circuit and a comparison voltage VREF generated by the comparator threshold selecting circuit; the width-to-length ratio of the PMOS tubes M3 and M4 is larger than that of the PMOS tubes M5 and M6, so that an active load with a hysteresis function is formed; the PMOS transistor M7, the current source I2, and the inverter INV1 form a two-stage amplifying circuit for amplifying, shaping, and outputting the digital level VD from the analog output of the comparator circuit.
6. The unipolar code analog decoding circuit of claim 5, wherein the PMOS transistors M1, M2 in the comparator circuit are further coupled to ground via a current source I1.
7. A unipolar code analog decoding circuit according to any of claims 1 to 6, characterised in that the front end amplifying circuit, the bandgap reference source, the comparison threshold selection circuit and the comparator have a common ground VSS and power supply VDD.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410910386.3A CN118473417A (en) | 2024-07-09 | 2024-07-09 | Unipolar code analog decoding circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410910386.3A CN118473417A (en) | 2024-07-09 | 2024-07-09 | Unipolar code analog decoding circuit |
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| CN118473417A true CN118473417A (en) | 2024-08-09 |
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| CN202410910386.3A Withdrawn CN118473417A (en) | 2024-07-09 | 2024-07-09 | Unipolar code analog decoding circuit |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN119519713A (en) * | 2025-01-21 | 2025-02-25 | 成都电科星拓科技有限公司 | TPS readout circuit |
| CN119543936A (en) * | 2025-01-21 | 2025-02-28 | 成都电科星拓科技有限公司 | TPS digital-to-analog conversion circuit |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060197574A1 (en) * | 2005-03-07 | 2006-09-07 | Cadence Design Systems, Inc. | Auto-zero circuit |
| JP2014060484A (en) * | 2012-09-14 | 2014-04-03 | Renesas Electronics Corp | Semiconductor device |
| CN106817099A (en) * | 2017-04-06 | 2017-06-09 | 高科创芯(北京)科技有限公司 | For the amplifier of physiology potential signal detection |
| CN117640308A (en) * | 2023-12-08 | 2024-03-01 | 珠海楠欣半导体科技有限公司 | Demodulation module, digital isolator, chip, demodulation method and electronic equipment |
-
2024
- 2024-07-09 CN CN202410910386.3A patent/CN118473417A/en not_active Withdrawn
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060197574A1 (en) * | 2005-03-07 | 2006-09-07 | Cadence Design Systems, Inc. | Auto-zero circuit |
| JP2014060484A (en) * | 2012-09-14 | 2014-04-03 | Renesas Electronics Corp | Semiconductor device |
| CN106817099A (en) * | 2017-04-06 | 2017-06-09 | 高科创芯(北京)科技有限公司 | For the amplifier of physiology potential signal detection |
| CN117640308A (en) * | 2023-12-08 | 2024-03-01 | 珠海楠欣半导体科技有限公司 | Demodulation module, digital isolator, chip, demodulation method and electronic equipment |
Non-Patent Citations (2)
| Title |
|---|
| 廖永波: "电源管理芯片设计教程", 31 May 2012, 冶金工业出版社, pages: 52 * |
| 陈铖颖: "ＣＭＯＳ模拟集成电路版图设计：基础、方法与验证", 31 January 2022, 机械工业出版社, pages: 342 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN119519713A (en) * | 2025-01-21 | 2025-02-25 | 成都电科星拓科技有限公司 | TPS readout circuit |
| CN119543936A (en) * | 2025-01-21 | 2025-02-28 | 成都电科星拓科技有限公司 | TPS digital-to-analog conversion circuit |
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Application publication date: 20240809 |