CN118473393A - Port driving circuit, port driving method and chip - Google Patents

Abstract

The application discloses a port driving circuit, a port driving method and a chip, wherein the port driving circuit comprises a first logic processing module, a first inversion module, a second logic processing module, a second inversion module and an output module, wherein the first control signal is generated according to a first enabling signal, a data signal and a first feedback signal, the second feedback signal is generated according to the first control signal, the second control signal is generated according to a second enabling signal, the data signal and the second feedback signal, and the first feedback signal is generated according to the second control signal, so that the potential of one of the first control signal and the second control signal is delayed to change under the condition that the potential of the data signal is inverted, and the synchronous on time of transistors with different channel types in the output module is reduced through the first control signal and the second control signal, so that the duration of short-circuit current is shortened, and the power consumption is reduced.

Description

Port driving circuit, port driving method and chip

Technical Field

The present application relates to the technical field of electronic circuits, and in particular to a port driving circuit, a port driving method and a chip.

Background Art

The port driving circuit is used to drive the corresponding load, and the port driving circuit improves the driving capability through the output module. The output module may include a P-channel transistor and an N-channel transistor connected between the power supply terminal and the ground terminal.

However, when the potential of the data signal is reversed, the P-channel transistor controlled by the first control signal and the N-channel transistor controlled by the second control signal will be turned on synchronously, which will generate a corresponding short-circuit current. In particular, as the potential reversal frequency of the data signal and/or the capacitance of the load increases, the short-circuit current also increases accordingly.

Summary of the invention

The present application provides a port driving circuit, a port driving method and a chip to alleviate the technical problem of long synchronous conduction time of transistors of different channel types.

In a first aspect, the present application provides a port driving circuit, which includes a first logic processing module, a first inversion module, a second logic processing module, a second inversion module and an output module, wherein the first logic processing module is used to generate a first control signal according to a first enable signal, a data signal and a first feedback signal; the first inversion module is used to generate a second feedback signal according to the first control signal; the second logic processing module is used to generate a second control signal according to the second enable signal, the data signal and the second feedback signal; the second inversion module is used to generate a first feedback signal according to the second control signal; and the output module is used to generate a corresponding driving signal according to the first control signal and the second control signal.

In some embodiments, the first logic processing module includes a first logic processing unit and a first feedback processing unit. The first logic processing unit is used to output a NAND logic operation result of a first enable signal and a data signal as a first control signal when the first feedback signal is at a low level; the first feedback processing unit is used to control the first logic processing unit to output a low-level first control signal when the first feedback signal, the first enable signal and the data signal are all at high levels.

In some embodiments, the first logic processing unit includes a first transistor, a second transistor, a third transistor and a fourth transistor, the first electrode of the first transistor is connected to the first power supply terminal, the control electrode of the first transistor is connected to the first enable signal, and the first transistor is a P-channel transistor; the first electrode of the second transistor is connected to the first power supply terminal, the control electrode of the second transistor is connected to the data signal, and the second transistor is a P-channel transistor; the first electrode of the third transistor is connected to the second electrode of the first transistor and the second electrode of the second transistor and generates a first control signal, the control electrode of the third transistor is connected to the control electrode of the first transistor, and the third transistor is an N-channel transistor; the first electrode of the fourth transistor is connected to the second electrode of the third transistor, the control electrode of the fourth transistor is connected to the control electrode of the second transistor, the second electrode of the fourth transistor is connected to the first feedback processing unit, and the fourth transistor is an N-channel transistor.

In some embodiments, the first feedback processing unit includes a fifth transistor, a first electrode of the fifth transistor is connected to the second electrode of the fourth transistor, a control electrode of the fifth transistor is connected to the first feedback signal, and the second electrode of the fifth transistor is connected to the second power supply terminal; the channel type of the fifth transistor is the same as the channel type of the third transistor or the channel type of the fourth transistor.

In some embodiments, the first inverting module includes a first resistor, a sixth transistor and a seventh transistor, one end of the first resistor is connected to the first power supply terminal; the first electrode of the sixth transistor is connected to the other end of the first resistor, the control electrode of the sixth transistor is connected to the first control signal, and the sixth transistor is a P-channel transistor; the first electrode of the seventh transistor is connected to the second electrode of the sixth transistor and generates a second feedback signal, the control electrode of the seventh transistor is connected to the control electrode of the sixth transistor, the second electrode of the seventh transistor is connected to the second power supply terminal, and the channel type of the seventh transistor is different from the channel type of the sixth transistor.

In some embodiments, the second logic processing module includes a second logic processing unit and a second feedback processing unit. The second logic processing unit is used to output the OR-NOT logical operation result of the second enable signal and the data signal as the second control signal when the second feedback signal is at a high voltage; the second feedback processing unit is used to control the second logic processing unit to output a high-voltage second control signal when the second feedback signal, the second enable signal and the data signal are all at low voltages.

In some embodiments, the second logic processing unit includes an eighth transistor, a ninth transistor, a tenth transistor and an eleventh transistor, the first electrode of the eighth transistor is connected to the second power supply terminal, the control electrode of the eighth transistor is connected to the second enable signal, and the eighth transistor is an N-channel transistor; the first electrode of the ninth transistor is connected to the second power supply terminal, the control electrode of the ninth transistor is connected to the data signal, and the ninth transistor is an N-channel transistor; the first electrode of the tenth transistor is connected to the second electrode of the eighth transistor and the second electrode of the ninth transistor and generates a second control signal, the control electrode of the tenth transistor is connected to the control electrode of the eighth transistor, and the tenth transistor is a P-channel transistor; the first electrode of the eleventh transistor is connected to the second electrode of the tenth transistor, the control electrode of the eleventh transistor is connected to the control electrode of the ninth transistor, the second electrode of the eleventh transistor is connected to the second feedback processing unit, and the channel type of the eleventh transistor is the same as the channel type of the tenth transistor.

In some embodiments, the second feedback processing unit includes a twelfth transistor, a first electrode of the twelfth transistor is connected to the second electrode of the eleventh transistor, a control electrode of the twelfth transistor is connected to the second feedback signal, and the second electrode of the twelfth transistor is connected to the first power supply terminal; the channel type of the twelfth transistor is the same as the channel type of the tenth transistor or the channel type of the eleventh transistor.

In some embodiments, the second inverting module includes a thirteenth transistor, a fourteenth transistor and a second resistor, the first electrode of the thirteenth transistor is connected to the first power supply terminal, the control electrode of the thirteenth transistor is connected to the second control signal, and the thirteenth transistor is a P-channel transistor; the first electrode of the fourteenth transistor is connected to the second electrode of the thirteenth transistor and generates a first feedback signal, the control electrode of the fourteenth transistor is connected to the control electrode of the thirteenth transistor, and the fourteenth transistor is an N-channel transistor; one end of the second resistor is connected to the second electrode of the fourteenth transistor, and the other end of the second resistor is connected to the second power supply terminal.

In a second aspect, the present application provides a port driving method, which includes: generating a first control signal according to a first enable signal, a data signal and a first feedback signal; generating a second feedback signal that is inverted from the first control signal according to the first control signal; generating a second control signal according to a second enable signal, a data signal and a second feedback signal; generating a first feedback signal that is inverted from the second control signal according to the second control signal; and generating a corresponding driving signal according to the first control signal and the second control signal.

In a third aspect, the present application provides a chip, which includes the above-mentioned port driving circuit.

The port driving circuit, port driving method and chip provided in the present application generate a first control signal according to a first enable signal, a data signal and a first feedback signal, generate a second feedback signal according to the first control signal, generate a second control signal according to a second enable signal, a data signal and a second feedback signal, and generate a first feedback signal according to the second control signal. In the case where the potential of the data signal is flipped, the potential of one of the first control signal and the second control signal can be delayed to change, thereby reducing the synchronous conduction time of transistors of different channel types in the output module through the first control signal and the second control signal, thereby reducing the duration of the short-circuit current and reducing power consumption.

BRIEF DESCRIPTION OF THE DRAWINGS

The technical solution and other beneficial effects of the present application will be made apparent by describing in detail the specific implementation methods of the present application in conjunction with the accompanying drawings.

FIG. 1 is a first circuit schematic diagram of a port driving circuit in the related art.

FIG. 2 is a second circuit schematic diagram of a port driving circuit provided in an embodiment of the present application.

FIG. 3 is a timing diagram of the port driving circuit shown in FIG. 2 .

FIG. 4 is a circuit schematic diagram of a port driving circuit provided in an embodiment of the present application.

FIG. 5 is a first timing diagram of the port driving circuit shown in FIG. 4 .

FIG. 6 is a second timing diagram of the port driving circuit shown in FIG. 4 .

FIG. 7 is a circuit diagram of a chip provided in an embodiment of the present application.

FIG8 is a flow chart of a port driving method provided in an embodiment of the present application.

DETAILED DESCRIPTION

The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or suggesting relative importance or implicitly indicating the number of technical features indicated. The features specified as "first" and "second" may explicitly or implicitly include one or more of the said features. In the description of the present invention, "multiple" means two or more, unless otherwise clearly and specifically defined.

FIG1 is a first circuit schematic diagram of a port driving circuit in the related art. FIG2 is a second circuit schematic diagram of a port driving circuit provided in an embodiment of the present application. As shown in FIG1 and FIG2, the port driving circuit includes a P-channel pull-up transistor T1 and an N-channel pull-down transistor T2, wherein a first electrode of the pull-up transistor T1 is connected to a first power supply terminal VCC, a second electrode of the pull-up transistor T1 is connected to a first electrode of the pull-down transistor T2, and a second electrode of the pull-down transistor T2 is connected to a second power supply terminal GND.

The connection point between the pull-up transistor T1 and the pull-down transistor T2 is connected to one end of the equivalent capacitor C1 of the load through the pad 90 , and the other end of the equivalent capacitor C1 is connected to the second power supply terminal GND.

As shown in Fig. 2, the port driving circuit may further include an inverter INV1, which is used to generate a second enable signal ENb that is inverted from the first enable signal EN according to the first enable signal EN. That is, when the first enable signal EN is at a high potential, the second enable signal ENb is at a low potential; or when the first enable signal EN is at a low potential, the second enable signal ENb is at a high potential.

In some embodiments, according to the characteristics of the circuit structure, a high potential can control a P-channel transistor to be cut off or an N-channel transistor to be turned on; and a low potential can control a P-channel transistor to be turned on or an N-channel transistor to be cut off.

The port driving circuit may further include a NAND gate NAND1 and a NOR gate NOR1, wherein the NAND gate NAND1 may output a corresponding first control signal PUB according to a NAND logic operation result of a first enable signal EN and a data signal DS, wherein the first control signal PUB is used to control the switch state of the pull-up transistor T1. The NOR gate NOR1 may output a corresponding second control signal PD according to a NOR logic operation result of a second enable signal ENb and a data signal DS, wherein the second control signal PD is used to control the switch state of the pull-down transistor T2.

As the equivalent capacitance C1 of the load increases, the sizes of the pull-up transistor T1 and the pull-down transistor T2 also need to increase accordingly to match the driving capabilities of the pull-up transistor T1 and the pull-down transistor T2 .

In some embodiments, the pull-up transistor T1 and the pull-down transistor T2 may form a CMOS driver, which may be used to drive a relatively large capacitive load off-chip, such as a gate of a power transistor.

However, as shown in FIG3 , when the potential of the data signal DS is reversed, for example, when the data signal DS switches from a high potential "1" to a low potential "0", under the control of the first control signal PUB and the second control signal PD, the pull-up transistor T1 and the pull-down transistor T2 are synchronously turned on for a period of time, which will generate a corresponding short-circuit current. For example, in the dotted box shown in FIG3 , the current XPF flowing through the pull-up transistor T1 will change from a negative value to zero, and the current XNF flowing through the pull-down transistor T2 will increase from zero. This will allow current to flow directly from the first power supply terminal VCC to the second power supply terminal GND through a lower impedance, thereby consuming unnecessary power. This phenomenon is called shoot-through dissipation.

The present embodiment provides a port driving circuit, please refer to Figures 4 to 7. As shown in Figures 4 and 7, the port driving circuit includes a first logic processing module 10, a first inversion module 30, a second logic processing module 20, a second inversion module 40 and an output module 50. The first logic processing module 10 is used to generate a first control signal PUB according to a first enable signal EN, a data signal DS and a first feedback signal PDb_D; the first inversion module 30 is used to generate a second feedback signal PU_D according to the first control signal PUB; the second logic processing module 20 is used to generate a second control signal PD according to the second enable signal ENb, the data signal DS and the second feedback signal PU_D; the second inversion module 40 is used to generate a first feedback signal PDb_D according to the second control signal PD; and the output module 50 is used to generate a corresponding driving signal OUT according to the first control signal PUB and the second control signal PD.

It can be understood that the port driving circuit, port driving method and chip provided in the present embodiment generate a first control signal PUB according to the first enable signal EN, the data signal DS and the first feedback signal PDb_D, generate a second feedback signal PU_D according to the first control signal PUB, generate a second control signal PD according to the second enable signal ENb, the data signal DS and the second feedback signal PU_D, and generate a first feedback signal PDb_D according to the second control signal PD. In the case where the potential of the data signal DS is flipped, the potential of one of the first control signal PUB and the second control signal PD can be delayed to change, thereby reducing or eliminating the synchronous conduction time of transistors of different channel types in the output module 50 through the first control signal PUB and the second control signal PD, thereby reducing or eliminating the duration of the short-circuit current, and reducing power consumption or avoiding power waste.

It should be noted that the output module 50 may include a P-channel pull-up transistor T1 and an N-channel pull-down transistor T2. The output end of the first logic processing module 10 is connected to the control electrode of the pull-up transistor T1 to control the switch state of the pull-up transistor T1 through the first control signal PUB. The input end of the first inversion module 30 is connected to the output end of the first logic processing module 10, and the output end of the first inversion module 30 is connected to an input end of the second logic processing module 20 to provide the first control signal PUB to the second logic processing module 20 after inversion processing. The output end of the second logic processing module 20 is connected to the control electrode of the pull-down transistor T2 to control the switch state of the pull-down transistor T2 through the second control signal PD. The input end of the second inversion module 40 is connected to the output end of the second logic processing module 20, and the output end of the second inversion module 40 is connected to an input end of the first logic processing module 10 to provide the second control signal PD to the first logic processing module 10 after inversion processing.

In one embodiment, as shown in Figures 4 and 7, the first logic processing module 10 includes a first logic processing unit 11 and a first feedback processing unit 12. The first logic processing unit 11 is used to output the NAND logic operation result of the first enable signal EN and the data signal DS as the first control signal PUB when the first feedback signal PDb_D is at a low level; the first feedback processing unit 12 is used to control the first logic processing unit 11 to output the low-level first control signal PUB when the first feedback signal PDb_D, the first enable signal EN and the data signal DS are all at high levels.

It should be noted that the first logic processing unit 11 is connected to the first feedback processing unit 12 to realize the above-mentioned functions of the first logic processing unit 11 and the first feedback processing unit 12 .

In one embodiment, as shown in FIG. 4 and FIG. 7 , the first logic processing unit 11 includes a first transistor M1, a second transistor M2, a third transistor M3 and a fourth transistor M4, wherein a first electrode of the first transistor M1 is connected to a first power supply terminal VCC, a control electrode of the first transistor M1 is connected to a first enable signal EN, and the first transistor M1 is a P-channel transistor; a first electrode of the second transistor M2 is connected to a first power supply terminal VCC, a control electrode of the second transistor M2 is connected to a data signal DS, and the second transistor M2 is a P-channel transistor; a first electrode of the third transistor M3 is connected to a second electrode of the first transistor M1 and a second electrode of the second transistor M2 and generates a first control signal PUB, a control electrode of the third transistor M3 is connected to a control electrode of the first transistor M1, and the third transistor M3 is an N-channel transistor; a first electrode of the fourth transistor M4 is connected to a second electrode of the third transistor M3, a control electrode of the fourth transistor M4 is connected to a control electrode of the second transistor M2, a second electrode of the fourth transistor M4 is connected to the first feedback processing unit 12, and the fourth transistor M4 is an N-channel transistor.

It should be noted that this embodiment is not limited to the first feedback processing unit 12 being connected between the second electrode of the fourth transistor M4 and the second power supply terminal GND. The first feedback processing unit 12 can also be connected between the fourth transistor M4 and the third transistor M3, or can also be connected between the third transistor M3 and the second transistor M2.

The first electrode may be one of the source and the drain, and the second electrode may be the other of the source and the drain. For example, when the first electrode is the source, the second electrode is the drain; or when the first electrode is the drain, the second electrode is the source. The control electrode may be a gate or a base, etc. The second power supply terminal GND may be a ground terminal.

In one embodiment, as shown in Figures 4 and 7, the first feedback processing unit 12 includes a fifth transistor M5, a first electrode of the fifth transistor M5 is connected to the second electrode of the fourth transistor M4, a control electrode of the fifth transistor M5 is connected to the first feedback signal PDb_D, and a second electrode of the fifth transistor M5 is connected to the second power supply terminal GND; a channel type of the fifth transistor M5 is the same as a channel type of the third transistor M3 and/or a channel type of the fourth transistor M4.

It should be noted that this embodiment is not limited to the fifth transistor M5 being connected between the second electrode of the fourth transistor M4 and the second power supply terminal GND. The fifth transistor M5 can also be connected between the fourth transistor M4 and the third transistor M3, or can be connected between the third transistor M3 and the second transistor M2.

In one embodiment, as shown in Figures 4 and 7, the first inverting module 30 includes a first resistor R1, a sixth transistor M6 and a seventh transistor M7, one end of the first resistor R1 is connected to the first power supply terminal VCC; the first electrode of the sixth transistor M6 is connected to the other end of the first resistor R1, the control electrode of the sixth transistor M6 is connected to the first control signal PUB, and the sixth transistor M6 is a P-channel transistor; the first electrode of the seventh transistor M7 is connected to the second electrode of the sixth transistor M6 and generates a second feedback signal PU_D, the control electrode of the seventh transistor M7 is connected to the control electrode of the sixth transistor M6, the second electrode of the seventh transistor M7 is connected to the second power supply terminal GND, and the channel type of the seventh transistor M7 is different from the channel type of the sixth transistor M6.

It should be noted that the first resistor R1 is connected in series between the first power supply terminal VCC and the sixth transistor M6, which can reduce the current flowing through the sixth transistor M6, thereby weakening the pull-up capability, thereby making the pull-down capability of the first inverting module 30 greater than the pull-up capability, and the potential of the second feedback signal PU_D can be pulled down to the potential of the second power supply terminal GND more quickly during the synchronous conduction of the sixth transistor M6 and the seventh transistor M7. In this way, the synchronous conduction time of the sixth transistor M6 and the seventh transistor M7 can be reduced, that is, the duration of the short-circuit current flowing through the sixth transistor M6 and the seventh transistor M7 is reduced, thereby saving power consumption. In some embodiments, the first resistor R1 can be omitted, and the first electrode of the sixth transistor M6 is connected to the first power supply terminal VCC.

In one embodiment, as shown in Figures 4 and 7, the second logic processing module 20 includes a second logic processing unit 21 and a second feedback processing unit 22. The second logic processing unit 21 is used to output the OR-N logic operation result of the second enable signal ENb and the data signal DS as the second control signal PD when the second feedback signal PU_D is at a high level; the second feedback processing unit 22 is used to control the second logic processing unit 21 to output the high-level second control signal PD when the second feedback signal PU_D, the second enable signal ENb and the data signal DS are all at low levels.

It should be noted that the second logic processing unit 21 is connected to the second feedback processing unit 22 to achieve the above-mentioned functions of the second logic processing unit 21 and the second feedback processing unit 22 .

In one embodiment, as shown in FIG. 4 and FIG. 7 , the second logic processing unit 21 includes an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, and an eleventh transistor M11. The first electrode of the eighth transistor M8 is connected to the second power supply terminal GND, the control electrode of the eighth transistor M8 is connected to the second enable signal ENb, and the eighth transistor M8 is an N-channel transistor; the first electrode of the ninth transistor M9 is connected to the second power supply terminal GND, the control electrode of the ninth transistor M9 is connected to the data signal DS, and the ninth transistor M9 is an N-channel transistor; the first electrode of the tenth transistor M10 is connected to the second power supply terminal GND, the control electrode of the ninth transistor M9 is connected to the data signal DS, and the ninth transistor M9 is an N-channel transistor; One electrode is connected to the second electrode of the eighth transistor M8 and the second electrode of the ninth transistor M9 and generates a second control signal PD, the control electrode of the tenth transistor M10 is connected to the control electrode of the eighth transistor M8, and the tenth transistor M10 is a P-channel transistor; the first electrode of the eleventh transistor M11 is connected to the second electrode of the tenth transistor M10, the control electrode of the eleventh transistor M11 is connected to the control electrode of the ninth transistor M9, the second electrode of the eleventh transistor M11 is connected to the second feedback processing unit 22, and the channel type of the eleventh transistor M11 is the same as the channel type of the tenth transistor M10.

It should be noted that this embodiment is not limited to the second feedback processing unit 22 being connected between the second electrode of the eleventh transistor M11 and the first power supply terminal VCC. The second feedback processing unit 22 can also be connected between the tenth transistor M10 and the eleventh transistor M11, or can also be connected between the ninth transistor M9 and the tenth transistor M10.

In one embodiment, as shown in Figures 4 and 7, the second feedback processing unit 22 includes a twelfth transistor M12, a first electrode of the twelfth transistor M12 is connected to the second electrode of the eleventh transistor M11, a control electrode of the twelfth transistor M12 is connected to the second feedback signal PU_D, and a second electrode of the twelfth transistor M12 is connected to the first power supply terminal VCC; the channel type of the twelfth transistor M12 is the same as the channel type of the tenth transistor M10 or the channel type of the eleventh transistor M11.

It should be noted that this embodiment is not limited to the twelfth transistor M12 being connected between the second electrode of the eleventh transistor M11 and the first power supply terminal VCC. The twelfth transistor M12 can also be connected between the tenth transistor M10 and the eleventh transistor M11, or can also be connected between the ninth transistor M9 and the tenth transistor M10.

In one embodiment, as shown in Figures 4 and 7, the second inverting module 40 includes a thirteenth transistor M13, a fourteenth transistor M14 and a second resistor R2, the first electrode of the thirteenth transistor M13 is connected to the first power supply terminal VCC, the control electrode of the thirteenth transistor M13 is connected to the second control signal PD, and the thirteenth transistor M13 is a P-channel transistor; the first electrode of the fourteenth transistor M14 is connected to the second electrode of the thirteenth transistor M13 and generates a first feedback signal PDb_D, the control electrode of the fourteenth transistor M14 is connected to the control electrode of the thirteenth transistor M13, and the fourteenth transistor M14 is an N-channel transistor; one end of the second resistor R2 is connected to the second electrode of the fourteenth transistor M14, and the other end of the second resistor R2 is connected to the second power supply terminal GND.

It should be noted that the second resistor R2 is connected in series between the second power supply terminal GND and the fourteenth transistor M14, which can reduce the current flowing through the fourteenth transistor M14, thereby weakening the pull-down capability, thereby making the pull-up capability of the second inverting module 40 greater than the pull-down capability, and the potential of the first feedback signal PDb_D can be pulled up to the potential of the first power supply terminal VCC more quickly during the synchronous conduction of the thirteenth transistor M13 and the fourteenth transistor M14. In this way, the synchronous conduction time of the thirteenth transistor M13 and the fourteenth transistor M14 can be reduced, that is, the duration of the short-circuit current flowing through the thirteenth transistor M13 and the fourteenth transistor M14 is reduced, thereby saving power consumption. In some embodiments, the second resistor R2 can be omitted, and the second electrode of the fourteenth transistor M14 is connected to the second power supply terminal GND.

The working principle of the above port driving circuit is described as follows:

In the initial state, the data signal DS is a high potential "1", the ninth transistor M9 is turned on, the second control signal PD is a low potential "0", the thirteenth transistor M13 is turned on, the fourteenth transistor M14 is turned off, and the first feedback signal PDb_D is a high potential "1"; the first enable signal EN is a high potential "1", the third transistor M3, the fourth transistor M4 and the fifth transistor M5 are all turned on, the first control signal PUB is a low potential "0", the sixth transistor M6 is turned on, the seventh transistor M7 is turned off, and the second feedback signal PU_D is a high potential "1".

Please refer to Figures 5 and 6. As shown in Figure 5, the data signal DS flips from a high potential "1" to a low potential "0", the second transistor M2 is turned on, and the first control signal PUB is gradually pulled up from a low potential "0", so the P-channel pull-up transistor T1 is gradually cut off, and the current XPF flowing through the pull-up transistor T1 tends to 0; before the potential of the first control signal PUB reaches the potential flip point of the second feedback signal PU_D, the second feedback signal PU_D still remains at a high potential "1", the twelfth transistor M12 is in a cut-off state, and the second control signal PD still remains at a low potential "0".

After the potential of the first control signal PUB reaches the potential inversion point of the second feedback signal PU_D, the seventh transistor M7 is turned on, and the second feedback signal PU_D is switched to a low potential "0". Since the data signal DS and the second enable signal ENb are both low potential "0", the tenth transistor M10, the eleventh transistor M11 and the twelfth transistor M12 are all turned on, and the second control signal PD begins to be gradually pulled up from the low potential "0", and the pull-down transistor T2 is gradually turned on, and the current XNF flowing through the pull-down transistor T2 starts to increase from 0.

It can be seen that in the process of the data signal DS flipping from the high potential "1" to the low potential "0", as shown in the dotted box in Figure 5, the current XPF flowing through the pull-up transistor T1 and the current XNF flowing through the pull-down transistor T2 are not non-0 at the same time, which means that the pull-up transistor T1 and the pull-down transistor T2 are not turned on synchronously, thus reducing the short-circuit current and the power consumption.

As shown in Figure 6, the data signal DS flips from a low potential "0" to a high potential "1", the ninth transistor M9 is turned on, and the second control signal PD is gradually pulled down from a high potential "1", so the N-channel pull-down transistor T2 is gradually cut off, and the current XNF flowing through the pull-down transistor T2 tends to 0; before the potential of the second control signal PD reaches the potential flip point of the first feedback signal PDb_D, the first feedback signal PDb_D still remains at a low potential "0", and the fifth transistor M5 is in a cut-off state. At this time, the first control signal PUB still remains at a high potential "1".

After the potential of the second control signal PD reaches the potential inversion point of the first feedback signal PDb_D, the thirteenth transistor M13 is turned on, and the first feedback signal PDb_D is switched to a high potential "1". Since the data signal DS and the first enable signal EN are both high potential "1", the third transistor M3, the fourth transistor M4 and the fifth transistor M5 are all turned on, and the first control signal PUB begins to be gradually pulled down from the high potential "1", and the pull-up transistor T1 is gradually turned on, and the current XPF flowing through the pull-up transistor T1 starts to increase from 0.

It can be seen that in the process of the data signal DS flipping from the low potential "0" to the high potential "1", as shown in the dotted box in Figure 6, the current XPF flowing through the pull-up transistor T1 and the current XNF flowing through the pull-down transistor T2 are not non-0 at the same time, which means that the pull-up transistor T1 and the pull-down transistor T2 are not turned on synchronously, thereby reducing the short-circuit current and the power consumption.

In one embodiment, this embodiment provides a chip, as shown in Figure 7, which includes the above-mentioned port driving circuit. The chip can be various integrated circuits with output pins, such as a storage integrated circuit, a control integrated circuit, etc.

It can be understood that since the chip provided in this embodiment includes the above-mentioned port driving circuit, it can also generate a first control signal PUB according to the first enable signal EN, the data signal DS and the first feedback signal PDb_D, generate a second feedback signal PU_D according to the first control signal PUB, generate a second control signal PD according to the second enable signal ENb, the data signal DS and the second feedback signal PU_D, and generate a first feedback signal PDb_D according to the second control signal PD. In the case where the potential of the data signal DS is flipped, the potential of one of the first control signal PUB and the second control signal PD can be delayed to change, thereby reducing the synchronous conduction time of transistors of different channel types in the output module 50 through the first control signal PUB and the second control signal PD, thereby reducing the duration of the short-circuit current and reducing power consumption.

It should be noted that the chip may further include a pad 90 , through which the output end of the output module 50 may be connected to an external pin.

In one embodiment, this embodiment provides a port driving method, as shown in FIG8 , the port driving method comprises the following steps:

Step S10: Generate a first control signal according to a first enable signal, a data signal and a first feedback signal.

Step S20: generating a second feedback signal having an anti-phase with the first control signal according to the first control signal.

Step S30: Generate a second control signal according to the second enable signal, the data signal and the second feedback signal.

Step S40: generating a first feedback signal which is inversely proportional to the second control signal according to the second control signal.

Step S50: Generate a corresponding driving signal according to the first control signal and the second control signal.

It can be understood that the port driving method provided in this embodiment generates a first control signal PUB according to the first enable signal EN, the data signal DS and the first feedback signal PDb_D, generates a second feedback signal PU_D according to the first control signal PUB, generates a second control signal PD according to the second enable signal ENb, the data signal DS and the second feedback signal PU_D, and generates a first feedback signal PDb_D according to the second control signal PD. In the case where the potential of the data signal DS is flipped, the potential of one of the first control signal PUB and the second control signal PD can be delayed to change, thereby reducing the synchronous conduction time of transistors of different channel types in the output module 50 through the first control signal PUB and the second control signal PD, thereby reducing the duration of the short-circuit current and reducing power consumption.

It should be noted that the port driving method can be executed in a processor or a storage medium such as a storage chip.

In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

The port driving circuit, port driving method and chip provided in the embodiments of the present application are introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims (11)

1. A port driving circuit, characterized in that the port driving circuit comprises: A first logic processing module, wherein the first logic processing module is used to generate a first control signal according to a first enable signal, a data signal and a first feedback signal; A first inversion module, wherein the first inversion module is used to generate a second feedback signal according to the first control signal; a second logic processing module, the second logic processing module being configured to generate a second control signal according to a second enable signal, the data signal and the second feedback signal; a second inverting module, the second inverting module being configured to generate the first feedback signal according to the second control signal; An output module, wherein the output module is used to generate a corresponding driving signal according to the first control signal and the second control signal. 2. The port driving circuit according to claim 1, wherein the first logic processing module comprises: a first logic processing unit, wherein the first logic processing unit is configured to output a logical NAND result of the first enable signal and the data signal as the first control signal when the first feedback signal is at a low level; The first feedback processing unit is used to control the first logic processing unit to output the first control signal of low potential when the first feedback signal, the first enable signal and the data signal are all at high potential. 3. The port driving circuit according to claim 2, wherein the first logic processing unit comprises: a first transistor, wherein a first electrode of the first transistor is connected to a first power supply terminal, a control electrode of the first transistor is connected to the first enable signal, and the first transistor is a P-channel transistor; a second transistor, wherein a first electrode of the second transistor is connected to the first power supply terminal, a control electrode of the second transistor is connected to the data signal, and the second transistor is a P-channel transistor; a third transistor, wherein a first electrode of the third transistor is connected to a second electrode of the first transistor and a second electrode of the second transistor and generates the first control signal, a control electrode of the third transistor is connected to a control electrode of the first transistor, and the third transistor is an N-channel transistor; A fourth transistor, wherein a first electrode of the fourth transistor is connected to a second electrode of the third transistor, a control electrode of the fourth transistor is connected to a control electrode of the second transistor, a second electrode of the fourth transistor is connected to the first feedback processing unit, and the fourth transistor is an N-channel transistor. 4. The port driving circuit according to claim 3, characterized in that the first feedback processing unit comprises a fifth transistor, a first electrode of the fifth transistor is connected to a second electrode of the fourth transistor, a control electrode of the fifth transistor is connected to the first feedback signal, and a second electrode of the fifth transistor is connected to a second power supply terminal; A channel type of the fifth transistor is the same as a channel type of the third transistor or a channel type of the fourth transistor. 5. The port driving circuit according to claim 1, wherein the first inverting module comprises: A first resistor, one end of which is connected to a first power supply end; a sixth transistor, wherein a first electrode of the sixth transistor is connected to the other end of the first resistor, a control electrode of the sixth transistor is connected to the first control signal, and the sixth transistor is a P-channel transistor; A seventh transistor, wherein a first electrode of the seventh transistor is connected to a second electrode of the sixth transistor and generates the second feedback signal, a control electrode of the seventh transistor is connected to a control electrode of the sixth transistor, a second electrode of the seventh transistor is connected to a second power supply terminal, and a channel type of the seventh transistor is different from a channel type of the sixth transistor. 6. The port driving circuit according to claim 1, wherein the second logic processing module comprises: a second logic processing unit, the second logic processing unit being configured to output a logical negation result of a logical operation of the second enable signal and the data signal as the second control signal when the second feedback signal is at a high level; The second feedback processing unit is used to control the second logic processing unit to output the second control signal of high potential when the second feedback signal, the second enable signal and the data signal are all at low potential. 7. The port driving circuit according to claim 6, wherein the second logic processing unit comprises: an eighth transistor, wherein a first electrode of the eighth transistor is connected to the second power supply terminal, a control electrode of the eighth transistor is connected to the second enable signal, and the eighth transistor is an N-channel transistor; a ninth transistor, wherein a first electrode of the ninth transistor is connected to the second power supply terminal, a control electrode of the ninth transistor is connected to the data signal, and the ninth transistor is an N-channel transistor; a tenth transistor, wherein a first electrode of the tenth transistor is connected to a second electrode of the eighth transistor and a second electrode of the ninth transistor and generates the second control signal, a control electrode of the tenth transistor is connected to a control electrode of the eighth transistor, and the tenth transistor is a P-channel transistor; an eleventh transistor, wherein a first electrode of the eleventh transistor is connected to a second electrode of the tenth transistor, a control electrode of the eleventh transistor is connected to a control electrode of the ninth transistor, a second electrode of the eleventh transistor is connected to the second feedback processing unit, and a channel type of the eleventh transistor is the same as a channel type of the tenth transistor. 8. The port driving circuit according to claim 7, characterized in that the second feedback processing unit comprises a twelfth transistor, a first electrode of the twelfth transistor is connected to the second electrode of the eleventh transistor, a control electrode of the twelfth transistor is connected to the second feedback signal, and a second electrode of the twelfth transistor is connected to the first power supply terminal; A channel type of the twelfth transistor is the same as a channel type of the tenth transistor or a channel type of the eleventh transistor. 9. The port driving circuit according to claim 1, wherein the second inverting module comprises: a thirteenth transistor, wherein a first electrode of the thirteenth transistor is connected to the first power supply terminal, a control electrode of the thirteenth transistor is connected to the second control signal, and the thirteenth transistor is a P-channel transistor; a fourteenth transistor, wherein a first electrode of the fourteenth transistor is connected to a second electrode of the thirteenth transistor and generates the first feedback signal, a control electrode of the fourteenth transistor is connected to a control electrode of the thirteenth transistor, and the fourteenth transistor is an N-channel transistor; A second resistor, one end of the second resistor is connected to the second electrode of the fourteenth transistor, and the other end of the second resistor is connected to the second power supply end. 10. A port driving method, characterized in that the port driving method comprises: Generate a first control signal according to the first enable signal, the data signal and the first feedback signal; generating a second feedback signal which is inversely proportional to the first control signal according to the first control signal; generating a second control signal according to a second enable signal, the data signal and the second feedback signal; generating the first feedback signal which is inversely proportional to the second control signal according to the second control signal; A corresponding driving signal is generated according to the first control signal and the second control signal. 11. A chip, characterized in that the chip comprises the port driving circuit according to any one of claims 1 to 9.