CN118473194B - Synchronous rectification chip circuit - Google Patents
Synchronous rectification chip circuit Download PDFInfo
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- CN118473194B CN118473194B CN202410940399.5A CN202410940399A CN118473194B CN 118473194 B CN118473194 B CN 118473194B CN 202410940399 A CN202410940399 A CN 202410940399A CN 118473194 B CN118473194 B CN 118473194B
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- 230000001360 synchronised effect Effects 0.000 title claims abstract description 79
- 238000001514 detection method Methods 0.000 claims description 56
- 230000000087 stabilizing effect Effects 0.000 claims description 20
- 238000013468 resource allocation Methods 0.000 abstract description 3
- 238000007726 management method Methods 0.000 description 42
- 238000010586 diagram Methods 0.000 description 11
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- 230000005611 electricity Effects 0.000 description 6
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Classifications
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of AC power input into DC power output; Conversion of DC power input into AC power output
- H02M7/02—Conversion of AC power input into DC power output without possibility of reversal
- H02M7/04—Conversion of AC power input into DC power output without possibility of reversal by static converters
- H02M7/12—Conversion of AC power input into DC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/21—Conversion of AC power input into DC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M7/217—Conversion of AC power input into DC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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Abstract
The invention discloses a synchronous rectification chip circuit, which mainly solves the problems of high cost and multiple withstand voltage versions of synchronous rectification chips in the prior art. The circuit comprises a synchronous rectification driving chip, a switching tube NH1, a grid electrode, a drain electrode and a diode D7, wherein the switching tube NH1 is connected with the grid electrode and the drain electrode of the synchronous rectification driving chip, the diode D7 is connected with the drain electrode of the switching tube NH1, and the cathode of the diode D7 is connected with the source electrode of the switching tube, wherein a VIN pin is led out from the synchronous rectification driving chip to the output voltage VOUT end of the circuit of the synchronous rectification driving chip, the driving chip is simple in design and low in cost, and synchronous rectification chips with different withstand voltage versions are realized by matching high-voltage transistors NH2 and switching tubes NH1 with different specifications, so that the application range of the driving chip is greatly improved, the resource allocation cost is reduced, and the cost of a switching power supply system is greatly reduced.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a synchronous rectification chip circuit.
Background
In order to improve efficiency, most of the existing switching power supplies are rectified by a Schottky diode into transistor synchronous rectification, and a synchronous switching MOS tube replaces a rectifying diode, so that rectifying voltage drop is obviously reduced, and the efficiency of the switching power supplies is improved. However, the switching MOS transistor needs to be driven by voltage, so how to properly take power from the power supply system becomes a problem of synchronous rectification driving chips. Since the output power supply voltage may occur in a case where the voltage is low (3.3V output) and the output is short-circuited, the synchronous rectification driving chip needs to have a power supply voltage independent of the output power supply voltage.
As shown in fig. 1, most of the prior art takes power from the drain terminal D of the synchronous rectification switching tube. The drain end D of the synchronous rectification switch tube is also the output end of the output winding Ls of the transformer, when the primary side main power tube is opened, under the voltage coupling action of the transformer, the source and drain ends of the synchronous rectification switch tube can generate high voltage, and the prior art mostly adopts the voltage to charge the VCC capacitor C0 of the chip. Therefore, the synchronous rectification chip U2 has only 3 ports, only one capacitor is needed outside, and the application system is extremely simple. And the synchronous rectification chip is not influenced by the output voltage VOUT. However, the power supply scheme has the problem of high cost, and the reason is that the voltage peak can appear at the source and drain ends of the synchronous rectification switch tube due to leakage inductance of the transformer, so that the voltage-withstanding requirement of the synchronous rectification switch tube is extremely high. When the output voltage VOUT is 20V, the drain-source withstand voltage of the synchronous rectification switching tube is at least 120V.
In the prior art, when electricity is taken from the drain end of the switching tube, a driving chip is required to be provided with a high-voltage electricity taking bias and detection circuit with 120V, and a corresponding withstand voltage ESD device is required. In the prior art, the area of the ESD device is increased proportionally as the voltage is higher, and the cost is correspondingly increased. Therefore, the cost of the existing synchronous rectification chip is high. In order to reduce the cost of a part of power supply system with low voltage withstand requirement, synchronous rectification chips mostly adopt schemes with various voltage withstand versions. For example, a synchronous rectification driving chip designed by a 60V voltage-resistant device is adopted on a switching power supply system with the output voltage of 12V or 9V, and a synchronous rectification driving chip designed by a 120V voltage-resistant device is adopted on a switching power supply system with the output voltage of 20V. This results in the need to produce synchronous rectification chips of various withstand voltage versions, which often require stock due to the excessive production time of the chip wafers. If the 60V withstand voltage version is produced too much, but the market demand becomes smaller, but the 120V withstand voltage version becomes more demanding. This causes problems in resource allocation, indirectly increasing system cost. And if a higher demand for output voltage occurs, the circuit needs to be redesigned, continuing to increase the cost.
Fig. 2 is a schematic diagram of a synchronous rectification power supply structure in the prior art. In the prior art, synchronous rectification power supply techniques are various, but are summarized as shown in fig. 2. The driving chip U1 and the switching tube NH1 are usually sealed together to form a synchronous rectification chip U2. Because the design principle of the driving chip U1 is to take electricity from the drain end of the switching tube, the HVESD, the HV bias detection module and the internal high-voltage transistor NH2 of the driving chip U1 are connected to the drain end of the switching tube NH1 and are uniformly connected to the D pin end of the synchronous rectification chip. Wherein HVESD is a pin port ESD protection device of the driver chip U1. The HV bias detection module is responsible for acquiring voltage bias from the end D when power is on, so that the driving chip can normally start up. The voltage of the D terminal of the synchronous rectification chip is a switching waveform, and electricity taking can be realized only when the D terminal is at a high level, so that the HV bias detection module also has a D terminal voltage detection function, when the D terminal voltage is detected to be high enough, signals are output to the charge pump module and the processing driving module, then the grid Vg of NH2 is controlled to output a high level to open a high-voltage transistor NH2, current flows through the NH2 transistor from the D terminal, flows through the backflow prevention diode D3 and charges the VCC capacitor. When the processing driving module detects that the VCC voltage is too high, the charge pump circuit is controlled to turn off the transistor NH2. The anti-reverse diode D3 functions to prevent VCC current from flowing back to the D terminal when the D terminal voltage becomes low.
In the prior art, as shown in patent CN109412436B, high-voltage transistors with N1 and N2 are connected to the VD end, and the first signal judging module receives the VD chip and outputs the judgment to the comparing unit to control the capacitor bias unit to turn on the high-voltage transistors with N1 and N2 after the judgment is processed. Wherein the first signal judgment module is equivalent to the HV offset detection module described in fig. 2, the first and second comparison units are equivalent to the process control module, and the first and second capacitance offset units are equivalent to the charge pump module. This patent describes the lack of a start-up power supply, and in theory the bias voltage module needs to be connected to either the VD terminal or HVIN terminals, otherwise the chip cannot be powered up. Alternatively, as shown in patent CN117639526a, the high voltage transistor N1 and the charge pump module 1 are connected to the VD terminal, outputting a low voltage vdla to the internal circuitry for processing. Wherein the charge pump module 1 is charged from the VD terminal and is responsible for the switching control of the high voltage transistor N1, which is equivalent to the HV bias detection and charge pump module in fig. 2. The transistor N1 needs to employ a high withstand voltage device and the port VD needs to employ a high withstand voltage ESD protection device.
Disclosure of Invention
The invention aims to provide a synchronous rectification chip circuit, which mainly solves the problems of high cost and multiple withstand voltage versions of synchronous rectification chips in the prior art.
In order to achieve the above purpose, the technical scheme adopted by the invention is as follows:
A synchronous rectification chip circuit comprises a synchronous rectification driving chip, a switching tube NH1 with a grid electrode and a drain electrode connected with the synchronous rectification driving chip, the positive electrode of the diode D7 is connected with the drain electrode of the switching tube NH1, and the negative electrode of the diode D is connected with the source electrode of the switching tube; the synchronous rectification driving chip also leads out a VIN pin to the output voltage VOUT end of the synchronous rectification chip circuit;
The synchronous rectification driving chip comprises a charging management circuit, a power-on power-off circuit and a detection processing driving circuit which are connected with the charging management circuit, the voltage management circuit is connected with the detection processing driving circuit and the power-on power-taking circuit, and the charge pump is connected with the voltage management circuit, the detection processing driving circuit, the power-on power-taking circuit and the charge management circuit; the synchronous rectification driving chip leads out VIN pins from the power-on power-taking circuit, leads out the same Vs pins from the power-on power-taking circuit, the charging management circuit, the voltage management circuit, the detection processing driving circuit and the charge pump, leads out Vg pins from the charge pump, leads out the same GND pins from the power-on power-taking circuit, the voltage management circuit and the detection processing driving circuit, leads out the same VCC pins from the power-on management circuit, the voltage management circuit and the detection processing driving circuit, and leads out DRV pins from the detection processing driving circuit, wherein the grid electrode of a switch tube NH1 is connected with the DRV pins, and the drain electrode of the switch tube NH1 is connected with the Vg pins.
Further, in the invention, the power-on circuit comprises a transistor P2 and a voltage stabilizing circuit, wherein the drain electrode of the transistor P2 is connected with the voltage stabilizing circuit, the source electrode of the transistor P2 is connected with the charge management circuit and the charge pump, the grid electrode of the transistor P2 is connected with the detection processing driving circuit, the drain electrode of the transistor P2 is led out to the VIN pin, and the other end of the voltage stabilizing circuit is led out to the GND pin.
Further, in the present invention, the charge management circuit includes a power supply switching circuit connected to the source of the transistor P2, an operational amplifier U3 having a positive power supply terminal connected to the power supply switching circuit, a voltage dividing resistor R1 and a voltage dividing resistor R2 connected to the positive input terminal of the operational amplifier U3, a voltage dividing resistor R3 and a voltage dividing resistor R4 connected to the negative input terminal of the operational amplifier U3, and a transistor P1 having a gate connected to the output terminal of the operational amplifier U3, wherein the source of the transistor P1 is connected to the other terminal of the voltage dividing resistor R3 and led out to the VCC pin, the drain of the transistor P1 is connected to the source of the transistor P2, the other terminal of the voltage dividing resistor R4, and the negative power supply terminal of the operational amplifier U3 are led out to the GND pin, and the control terminal of the operational amplifier U3 is connected to the detection processing driving circuit.
Further, in the invention, the power-on circuit comprises a transistor N1, a transistor N2, a diode D1, a voltage stabilizing tube D2 and a resistor R5, wherein the grid electrode of the transistor N1 is connected with the drain electrode of the transistor N2, the anode of the diode D1 is connected with the source electrode of the transistor N1, the cathode of the diode D1 is connected with the charge management circuit and the charge pump, the cathode of the voltage stabilizing tube D2 is connected with the grid electrode of the transistor N1, the resistor R5 is connected between the drain electrode and the grid electrode of the transistor N1, the grid electrode of the transistor N2 is connected with the detection processing driving circuit, the drain electrode of the transistor N1 is led out to the VIN pin, and the source electrode of the transistor N2 and the anode of the voltage stabilizing tube D2 are led out to the GND pin.
Compared with the prior art, the invention has the following beneficial effects:
The driving chip provided by the invention is simple in design and low in cost, and synchronous rectification chips with different withstand voltage versions are realized by matching with the high-voltage transistors NH2 and the switching tubes NH1 with different specifications, so that the application range of the driving chip is greatly improved, the resource allocation cost is reduced, and the cost of a switching power supply system is greatly reduced.
Drawings
Fig. 1 is a diagram of a prior art synchronous rectification system.
Fig. 2 is a schematic diagram of a synchronous rectification power supply structure in the prior art.
Fig. 3 is an application diagram of the synchronous rectification system in embodiment 1 of the present invention.
Fig. 4 is a block diagram of a synchronous rectification driving chip according to embodiment 1 of the present invention.
Fig. 5 is a circuit diagram of a synchronous rectification chip according to embodiment 1 of the present invention.
Fig. 6 is a circuit diagram of a synchronous rectification chip in accordance with embodiment 2 of the present invention.
Fig. 7 is a waveform diagram of a switching cycle of the key signal in embodiment 1 of the present invention.
Fig. 8 is a waveform of key signals in the power-up process of embodiment 1 of the present invention.
Detailed Description
The invention will be further illustrated by the following description and examples, which include but are not limited to the following examples.
Example 1
The invention discloses a synchronous rectification chip circuit which comprises a synchronous rectification driving chip, a switching tube NH1, a diode D7 and a diode D, wherein the grid electrode and the drain electrode of the switching tube NH1 are connected with the synchronous rectification driving chip, the diode D7 is connected with the drain electrode of the switching tube NH1, and the cathode of the diode D is connected with the source electrode of the switching tube, and the synchronous rectification driving chip also leads out a VIN pin to the output voltage VOUT end of the synchronous rectification chip circuit.
The synchronous rectification driving chip comprises a charging management circuit, a power-on power-off circuit and a detection processing driving circuit which are connected with the charging management circuit, the voltage management circuit is connected with the detection processing driving circuit and the power-on power-taking circuit, and the charge pump is connected with the voltage management circuit, the detection processing driving circuit, the power-on power-taking circuit and the charge management circuit; the synchronous rectification driving chip leads out VIN pins from the power-on power-taking circuit, leads out the same Vs pins from the power-on power-taking circuit, the charging management circuit, the voltage management circuit, the detection processing driving circuit and the charge pump, leads out Vg pins from the charge pump, leads out the same GND pins from the power-on power-taking circuit, the voltage management circuit and the detection processing driving circuit, leads out the same VCC pins from the power-on management circuit, the voltage management circuit and the detection processing driving circuit, and leads out DRV pins from the detection processing driving circuit, wherein the grid electrode of a switch tube NH1 is connected with the DRV pins, and the drain electrode of the switch tube NH1 is connected with the Vg pins.
In this embodiment, the power-on power-off circuit includes a transistor P2 and a voltage stabilizing circuit, where a drain electrode of the transistor P2 is connected to the voltage stabilizing circuit, a source electrode of the transistor P2 is connected to the charge management circuit and the charge pump, a gate electrode of the transistor P2 is connected to the detection processing driving circuit, a drain electrode of the transistor P2 is led out to the VIN pin, and another end of the voltage stabilizing circuit is led out to the GND pin.
In this embodiment, the charge management circuit includes a power switching circuit connected to the source of the transistor P2, an operational amplifier U3 with a positive power terminal connected to the power switching circuit, a voltage dividing resistor R1 and a voltage dividing resistor R2 connected to the positive input terminal of the operational amplifier U3, a voltage dividing resistor R3 and a voltage dividing resistor R4 connected to the negative input terminal of the operational amplifier U3, and a transistor P1 with a gate connected to the output terminal of the operational amplifier U3, wherein the source of the transistor P1 is connected to the other end of the voltage dividing resistor R3 and led out to the VCC pin, the drain of the transistor P1 is connected to the source of the transistor P2, the other end of the voltage dividing resistor R4, and the negative power terminal of the operational amplifier U3 are led out to the GND pin, and the control terminal of the operational amplifier U3 is connected to the detection processing driving circuit.
As shown in FIG. 3, in the application of the embodiment, the port of VIN pin is connected to the output voltage VOUT of the application system through a resistor R9, and simultaneously, the pins Vg and Vs are connected with a transistor NH2, the grid electrode of the transistor NH2 is connected with the Vg pin, and the source electrode of the transistor NH2 is connected with the Vs pin. When the system is powered on, the synchronous rectification chip does not work, and the power supply VCC is at a low level. At this time, the switching tube NH1 is kept in an off state, and only the parasitic diode D7 performs the output rectifying operation. When the system is powered on, the output winding Ls of the transformer charges the output capacitor C1 through the diode D7, and the voltage of VOUT gradually rises. The chip VCC capacitor is charged through the R9 resistor. After the VCC voltage reaches the working threshold of the synchronous rectification driving chip, the internal charging management circuit and the charge pump work, the VCC voltage is charged high by taking electricity from the end D, and the switching tube NH1 is started after the VCC voltage reaches the synchronous rectification working threshold.
Fig. 4 is a block diagram of a synchronous rectification driving chip according to the present invention. The device comprises a power-on power-off circuit, a charging management circuit, a voltage management circuit, a charge pump and a detection processing driving circuit. The power-on power-off circuit is connected to the detection processing driving circuit, the VIN pin of the chip and the VHC node in the chip, is controlled by the detection processing driving circuit and is responsible for providing VIN voltage to the VHC node when the chip is powered on. The VHC node is connected to a Vs pin of the chip, and the voltage of the Vs pin follows the voltage change of the source terminal of the high-voltage transistor. The on-chip VHC node is also connected to a charge management circuit, a voltage management circuit, a charge pump, and a detection process drive circuit. The charge management circuit receives the VHC voltage and outputs the VHC voltage to the VCC pin, and is connected with the detection processing driving circuit and controlled by the detection processing driving circuit. The voltage management circuit is connected to the VCC, the VHC node, the charge pump and the detection processing driving circuit and is responsible for managing the output voltage of the charge pump. The charge pump is connected with the detection processing driving circuit and outputs to the Vg pin to drive the high-voltage transistor NH2 switch. The detection processing driving circuit outputs a switching tube driving signal to the DRV pin. The power-on power-off circuit charges a power supply VCC of the synchronous rectification chip through a VHC node when the system is powered on, so that the power-on function of the driving chip is realized. The voltage management circuit, charge pump and high voltage transistor NH2 are responsible for converting the switching tube drain voltage to an internal low voltage VHC. The voltage management circuit controls the internal low voltage VHC to charge the chip supply voltage VCC. The detection processing driving circuit and the switching tube NH1 realize synchronous rectification function, and detect and control VCC voltage, so as to avoid the over high VCC voltage. In practical application, the functions can be combined or split into different circuit combinations.
Fig. 5 is a circuit diagram of a synchronous rectification driving chip according to the present invention. The synchronous rectification driving chip is provided with 6 pin ends, namely a starting power supply input VIN, a switching power supply control output Vg, a voltage input Vs, a chip power supply VCC, a switching tube driving control DRV and a ground GND, and is sealed in a package body through the high-voltage transistor NH2 and the switching tube NH 1. The starting power supply input VIN is connected to the voltage stabilizing circuit of the power-on power-off circuit and the drain end of the transistor P2, the source end of the transistor P2 is connected to the VHC voltage end of the charging management circuit, and the grid electrode of the transistor P2 is connected to the detection processing driving circuit. And when the detection processing driving circuit detects that the system is in a switching waveform state, the P2 transistor is turned off, or the P2 transistor is turned off after the power-on is completed. The voltage stabilizing circuit controls the pull-down current, and the voltage of the VIN terminal is limited through an R9 resistor of an external system, so that the voltage of the VIN terminal is prevented from being too high.
At power up, transistor P2 is turned on, VIN charges VHC, and VHC voltage rises to charge VCC. The charge management circuit converts the VHC voltage to a chip slave VCC voltage, responsible for charging VCC capacitor C0. The drain of the transistor P1 is connected with VHC voltage, the source is connected with VCC voltage, and the gate is connected with the output of the operational amplifier U3. The voltage dividing resistor R1 and the voltage dividing resistor R2 divide the VHC voltage, and the divided voltage is output to the negative input terminal of the operational amplifier U3. The voltage dividing resistor R3 and the voltage dividing resistor R4 divide the VCC voltage, and the divided voltage is output to the positive input end of the operational amplifier U3. When the VHC voltage is higher than the VCC voltage by a set value, the operational amplifier U3 outputs a control transistor P1 to be turned on, and the VHC voltage charges the VCC voltage. When the VHC voltage is lower than the set value, the operational amplifier U3 outputs the control transistor P1 to be turned off, and the VHC voltage stops charging the VCC voltage. Meanwhile, the detection processing driving circuit can detect the VCC voltage in real time, and when the VCC voltage is too high, the output control turns off the operational amplifier U3, so that the transistor P1 is turned off, and the VHC voltage stops charging the VCC voltage. The power supply switching circuit is responsible for outputting the higher of the VHC voltage and the VCC voltage to the power supply terminal of the operational amplifier U3, so that the high level output by the operational amplifier U3 is always the highest of the VHC and VCC voltage, and the transistor P1 is ensured to be completely turned off.
The voltage management circuit is connected to the power supply VCC, the VHC voltage terminal, the charge pump circuit and the detection processing driving circuit, and adjusts the charge pump output voltage Vg by detecting the VHC voltage, and the Vg voltage controls the source terminal voltage Vs thereof through the high voltage transistor NH2, thereby controlling the VHC voltage and avoiding the voltage from being excessively high.
The detection processing driving circuit is used for controlling the operation amplifier U3 by detecting VCC voltage, VHC voltage and the grid electrode DRV terminal voltage of the switching tube, and is used for controlling the switch of the switch NH1 and the operation of the charge pump. The charge pump receives signals from the voltage management circuit and the detection processing driving circuit, is connected to a grid electrode Vg and a source electrode Vs/VHC of the high-voltage transistor NH2, outputs Vg voltage higher than VCC voltage when the voltage of the end D is increased, realizes that the NH2 transistor is opened, increases VHC voltage, and controls the transistor P2 to be opened to charge VCC through the operational amplifier U3.
Fig. 7 shows a switching cycle waveform of the key signal in this embodiment. Drain is the primary side main switching tube waveform, D is the synchronous rectification chip D end waveform, VHC waveform in the driving chip is shown as a solid line waveform in fig. 7, and VCC waveform is shown as a broken line waveform in fig. 7. When the main switching tube is opened, the Drain voltage is pulled down, and the D end voltage of the synchronous rectification chip becomes high due to the action of the transformer. When the detection processing driving module of the synchronous rectification chip detects that the voltage of the D terminal rises, the charge pump is started to turn on the high-voltage transistor NH2, as shown in the time t0 of FIG. 7. The VHC voltage rises, and when the voltage is higher than the VCC voltage by a set value, the charge management module of the driver chip works to charge the VCC, and the VCC voltage rises, for example, in the time period t0-t1 in fig. 7. When the main switching tube is closed, the Drain voltage rises, and the D terminal voltage of the synchronous rectification chip becomes low due to the action of the transformer. At this time, the high voltage transistor NH2 of the synchronous rectification driving chip is still turned on, and the VHC voltage will be lower along with the D terminal voltage. At this time, the synchronous rectification driving chip will turn on the switching tube NH1 to realize the synchronous rectification function, and will consume VCC, and the VCC voltage will be slightly lower, as in the period t1-t2 of fig. 7. Thus, when the voltage at the D terminal rises, the VHC voltage follows the rise, and when the voltage is higher than the VCC voltage by a set value, the VCC is charged, and when the voltage is not higher than the VCC set value, the VCC is not charged, as in the time period t2-8 of fig. 7.
Fig. 8 shows waveforms of key signals in the power-up process in this embodiment. The VOUT waveform is the power supply system output power supply waveform, the D waveform is the waveform simplified diagram of the synchronous rectification D end, and the VCC waveform is the waveform of the synchronous rectification chip VCC. When the system is electrified, the voltage of VOUT gradually rises, the synchronous rectification chip takes electricity through the VIN pin or the D-terminal pin, and the voltage of VCC of the chip gradually rises along with VOUT. When the voltage of the VCC pin of the chip rises by a certain threshold, the charge management circuit starts to work, the charge pump drives the high-voltage transistor to be opened, and the VCC voltage is gradually increased. When the VCC voltage reaches a set value, the charging management module controls to stop charging, and the VCC is only charged for a short period of time each time to supplement the voltage dropped when the switch works, so that the VCC voltage is kept balanced.
Example 2
As shown in fig. 6, the difference between the present embodiment and the embodiment 1 is that the power-on circuit includes a transistor N1, a transistor N2, a diode D1, a voltage stabilizing tube D2, and a resistor R5, wherein the gate of the transistor N1 is connected to the drain of the transistor N2, the anode of the diode D1 is connected to the source of the transistor N1, the cathode of the diode D1 is connected to the charge management circuit and the charge pump, the cathode of the voltage stabilizing tube D2 is connected to the gate of the transistor N1, the resistor R5 is connected between the drain and the gate of the transistor N1, the gate of the transistor N2 is connected to the detection processing driving circuit, the drain of the transistor N1 is led out to the VIN pin, and the source of the transistor N2 and the anode of the voltage stabilizing tube D2 are led out to the GND pin. In this embodiment, the VIN terminal adopts a voltage-withstanding medium-voltage transistor N1, which can withstand the output voltage of the power supply system, for example, 20V. The ESD at VIN port therefore needs to be tuned from a normal withstand voltage ESD to a medium voltage ESD device, such as the MV ESD module in fig. 6. The medium voltage ESD area is somewhat larger, which is not specifically circuit-functional here, and is listed for illustrating the cost variation of this solution. When the power supply system output voltage is powered on, VIN voltage rises, the medium-voltage transistor N1 is turned on by the resistor R5, the transistor N1 outputs VIN voltage to the positive electrode of the diode D1, and VHC voltage is outputted from the negative electrode of the diode D1 to charge VCC voltage. The diode D1 acts as a reverse current protection, and because of the short circuit condition of the system power supply, VIN is low, and the chip VCC voltage is prevented from flowing backward to the VIN terminal through the transistor N1. The grid electrode of the transistor N2 is connected to the detection processing driving circuit, the drain electrode of the transistor N2 is connected to the grid electrode of the transistor N1, when the detection processing driving circuit detects that the system is in a switch waveform state, the grid electrode voltage of the N1 transistor is lowered by turning on the N2 transistor, so that the N1 transistor is turned off, or the N1 transistor is turned off after power-on is completed.
The above embodiment is only one of the preferred embodiments of the present invention, and should not be used to limit the scope of the present invention, but all the insubstantial modifications or color changes made in the main design concept and spirit of the present invention are still consistent with the present invention, and all the technical problems to be solved are included in the scope of the present invention.
Claims (1)
1. The synchronous rectification chip circuit is characterized by comprising a synchronous rectification driving chip, a switching tube NH1, a switching tube NH2 and a diode D7, wherein the grid electrode and the drain electrode of the switching tube NH1 are connected with the synchronous rectification driving chip, the drain electrode of the switching tube NH2 is connected with the drain electrode of the switching tube NH1, the source electrode and the grid electrode of the switching tube NH2 are connected with the synchronous rectification driving chip, and the cathode of the diode D7 is connected with the drain electrode of the switching tube NH1, and the anode of the diode D7 is connected with the source electrode of the switching tube NH 1;
The synchronous rectification driving chip comprises a charging management circuit, a power-on power-off circuit and a detection processing driving circuit which are connected with the charging management circuit, the voltage management circuit is connected with the detection processing driving circuit and the power-on power-taking circuit, and the charge pump is connected with the voltage management circuit, the detection processing driving circuit, the power-on power-taking circuit and the charge management circuit; the synchronous rectification driving chip leads out VIN pins from the power-on power-taking circuit, leads out the same source voltage Vs pins from the power-on power-taking circuit, the charging management circuit, the voltage management circuit, the detection processing driving circuit and the charge pump, leads out gate voltage Vg pins from the charge pump, leads out the same grounding GND pins from the power-on power-taking circuit and the voltage management circuit detection processing driving circuit, leads out the same power VCC pins from the charging management circuit, the voltage management circuit and the detection processing driving circuit, and leads out driving DRV pins from the detection processing driving circuit, wherein the grid electrode of a switch tube NH1 is connected with the driving DRV pins, the grid electrode of a switch tube NH2 is connected with the grid voltage Vg pins, and the source electrode of the switch tube NH2 is connected with the source voltage Vs pins;
The power-on power-off circuit comprises a transistor P2 and a voltage stabilizing circuit, wherein the drain electrode of the transistor P2 is connected with one end of the voltage stabilizing circuit, the source electrode of the transistor P2 is connected with the charge management circuit and the charge pump, the grid electrode of the transistor P2 is connected with the detection processing driving circuit, the drain electrode of the transistor P2 is led out to an input VIN pin, and the other end of the voltage stabilizing circuit is led out to a grounding GND pin;
The charging management circuit comprises a power supply switching circuit connected with a source electrode of a transistor P2, an operational amplifier U3, a voltage dividing resistor R1, a voltage dividing resistor R2 and a transistor P1, wherein a positive power end of the operational amplifier U3 is connected with the power supply switching circuit, one end of the voltage dividing resistor R1 is connected with a positive input end of the operational amplifier U3, one end of the voltage dividing resistor R2 is connected with a voltage dividing resistor R3 and a voltage dividing resistor R4 which are connected with a negative input end of the operational amplifier U3, and a gate electrode of the transistor P1 is connected with an output end of the operational amplifier U3, wherein the source electrode of the transistor P1 is connected with the other end of the voltage dividing resistor R3 and is led out to a power supply VCC pin, a drain electrode of the transistor P1 is connected with a source electrode of the transistor P2, the other end of the voltage dividing resistor R4 and a negative power supply end of the operational amplifier U3 are led out to a ground GND pin, a control end of the operational amplifier U3 is connected with a detection processing driving circuit, and a drain electrode of the transistor P1 is led out to a source voltage Vs pin;
The power-on circuit comprises a transistor N1, a transistor N2, a diode D1, a voltage stabilizing tube D2 and a resistor R5, wherein the grid electrode of the transistor N1 is connected with the drain electrode of the transistor N2, the anode of the diode D1 is connected with the source electrode of the transistor N1, the cathode of the diode D1 is connected with the charge management circuit and the charge pump, the cathode of the voltage stabilizing tube D2 is connected with the grid electrode of the transistor N1, the resistor R5 is connected between the drain electrode and the grid electrode of the transistor N1, the grid electrode of the transistor N2 is connected with the detection processing driving circuit, the drain electrode of the transistor N1 is led out to the VIN pin, and the source electrode of the transistor N2 and the anode of the voltage stabilizing tube D2 are led out to the grounding GND pin.
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| CN202410940399.5A CN118473194B (en) | 2024-07-15 | 2024-07-15 | Synchronous rectification chip circuit |
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| CN202410940399.5A CN118473194B (en) | 2024-07-15 | 2024-07-15 | Synchronous rectification chip circuit |
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| CN118473194B true CN118473194B (en) | 2025-01-03 |
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| CN118694147B (en) * | 2024-08-22 | 2025-03-25 | 中科(深圳)无线半导体有限公司 | A depletion-mode GaN switching power supply structure |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN208537681U (en) * | 2018-06-13 | 2019-02-22 | 茂睿芯（深圳）科技有限公司 | Synchronous rectification chip and its automatic detection circuit of power supply, circuit of synchronous rectification |
| CN111865088A (en) * | 2020-07-09 | 2020-10-30 | 无锡芯朋微电子股份有限公司 | Control circuit for synchronous rectification |
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| JP2003244966A (en) * | 2002-02-18 | 2003-08-29 | Mitsubishi Electric Corp | Drive circuit |
| CN108880266B (en) * | 2018-07-17 | 2024-03-12 | 富满微电子集团股份有限公司 | Synchronous rectification circuit, chip and isolated synchronous rectification control circuit |
| JP7212261B2 (en) * | 2019-03-27 | 2023-01-25 | ミツミ電機株式会社 | switching power supply |
| CN111404391A (en) * | 2020-04-24 | 2020-07-10 | 苏州锴威特半导体股份有限公司 | Positive-shock active clamping driving circuit |
| CN113364304B (en) * | 2021-08-10 | 2022-06-14 | 深圳市力生美半导体股份有限公司 | Synchronous rectification sampling control circuit, method and chip |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN208537681U (en) * | 2018-06-13 | 2019-02-22 | 茂睿芯（深圳）科技有限公司 | Synchronous rectification chip and its automatic detection circuit of power supply, circuit of synchronous rectification |
| CN111865088A (en) * | 2020-07-09 | 2020-10-30 | 无锡芯朋微电子股份有限公司 | Control circuit for synchronous rectification |
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