CN118468951A - In-memory computing device and computing method - Google Patents

Abstract

The invention discloses an in-memory computing device and a computing method, relates to the technical field of in-memory computing chip design, and aims to solve the problems that in the prior art, when an original signal and a reverse signal of a signal are output simultaneously, an inverter is required to be additionally arranged, so that the delay and the power consumption of the reverse signal relative to the original signal are increased. The in-memory computing column of the in-memory computing device comprises a computing unit and a plurality of storage units, wherein the computing unit comprises a first computing subunit and a second computing subunit; the first computing subunit includes a first input and a first output; the first input end is used for receiving a first input signal, and the first output end is used for outputting an inverse signal of the first output signal; the second computing subunit includes a second input and a second output; the second input end is used for receiving an inverse signal of the first input signal, and the second output end is used for outputting a first output signal; the method realizes that the output signal and the inverse signal of the output signal can be output simultaneously without configuring an inverter.

Description

In-memory computing device and computing method

Technical Field

The present invention relates to the technical field of in-memory computing chip design, and in particular to an in-memory computing device and a computing method.

Background Art

In-memory computing technology is currently a hot topic in the research of neural network accelerators and artificial intelligence. In order to better utilize the advantages of in-memory computing technology, researchers have improved the SRAM storage array, making the SRAM storage array more suitable for the development of in-memory computing technology. The main function of the current in-memory computing chip is the multiplication and accumulation calculation process of the neural network. The SRAM storage array is improved so that the SRAM storage array can have both storage and multiplication functions.

In the prior art, a method of using a storage array and a computing unit array to jointly form a computing structure is adopted, and their gates are respectively connected to the SRAM complementary bit lines (BLP and BLN), and the intermediate input lines INP and INN. The data (W) stored in the SRAM selects the complementary bit lines (BLP and BLN) to be connected to the computing unit; the transistors in the pull-up network are saved inside the sub-array. However, the total power consumption of the dynamic logic circuit adopted will be significantly higher than that of the static logic gate, because it is controlled by the clock cycle, and there is a flip in each cycle. Due to the periodic pre-charge and discharge operations, dynamic logic usually exhibits high switching activity; and there is only one output, and when the AND gate outputs the logical AND result, it is necessary to use a NAND gate to add an inverter to achieve it, that is, when the inverse signal of the output signal is required, an additional inverter is required to output the output signal and the inverse signal of the output signal, which leads to the problem of delay of the reverse signal relative to the original signal and increased power consumption.

Therefore, it is necessary to design a more advanced computing unit to solve the problem in the prior art that an additional inverter is required when outputting the reverse signal of the signal, resulting in a delay of the reverse signal relative to the original signal and increased power consumption.

Summary of the invention

The object of the present invention is to provide an in-memory computing device and a computing method, which are used to solve the problem in the prior art that when the original signal and the reverse signal of the signal are output simultaneously, an additional inverter is required, resulting in a delay of the reverse signal relative to the original signal and increased power consumption.

In order to achieve the above object, the present invention provides the following technical solutions:

In a first aspect, the present invention provides an in-memory computing device, the in-memory computing device comprising a plurality of in-memory computing columns, the in-memory computing columns comprising a computing unit and a plurality of storage units, the computing unit being connected to the plurality of storage units;

The computing unit comprises a first computing subunit and a second computing subunit; the first computing subunit is connected to the second computing subunit;

The first calculation subunit includes a first input terminal and a first output terminal; the first input terminal is used to receive a first input signal, and the first output terminal is used to output an inverse signal of the first output signal;

The second calculation subunit includes a second input terminal and a second output terminal; the second input terminal is used to receive the inverse signal of the first input signal, and the second output terminal is used to output the first output signal.

In a second aspect, the present invention provides an in-memory computing method, the in-memory computing method is applied to an in-memory computing device; the in-memory computing device includes a plurality of in-memory computing columns, the in-memory computing columns include a computing unit and a plurality of storage units; the method includes:

The calculation unit receives an input signal, an inverse signal of the input signal, and a bit line signal and a bit line inverse signal sent by a plurality of the storage units through a bit line;

Based on the input signal, the inverted signal of the input signal, the bit line signal and the bit line inverted signal, a NAND operation and a NOR operation are performed using preset transistors, so that the calculation unit simultaneously outputs an output signal and an inverted signal of the output signal.

Compared with the prior art, the present invention provides an in-memory computing device, which is configured by setting a plurality of storage units connected to a computing unit in any in-memory computing column of the in-memory computing device; wherein the computing unit includes a first computing subunit and a second computing subunit, and the first computing subunit is connected to the second computing subunit; the first computing subunit includes a first input terminal and a first output terminal; the first input terminal is used to receive a first input signal, and the first output terminal is used to output an inverse signal of the first output signal; the second computing subunit includes a second input terminal and a second output terminal; the second input terminal is used to receive an inverse signal of the first input signal, and the second output terminal is used to output the first output signal; based on this, an in-memory computing device with two-end input and two-end output functions is constructed, and the computing unit is combined with the storage unit to form an SRAM array integrating storage function and computing function; the computing unit can realize the simultaneous output of a logic and result and an inverse signal of the logic and result by simultaneously inputting an input signal and an inverse signal of the input signal, thereby eliminating the need for additional configuration of an inverter, saving the number of transistors in the circuit, and preventing the problem of circuit delay and increased power consumption.

BRIEF DESCRIPTION OF THE DRAWINGS

The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

FIG1 is a schematic diagram of the structure of any in-memory computing column in an in-memory computing device provided by the present invention;

FIG2 is a schematic diagram of the main flow of calculation operations of any one in-memory calculation column in an in-memory calculation device provided by the present invention;

FIG3 is a schematic diagram of signal input and output corresponding to a calculation operation of any in-memory calculation column in an in-memory calculation device provided by the present invention.

Figure numerals: 100-computing unit, 200-storage unit, 110-first computing subunit, 120-second computing subunit, MP1-first P-type transistor, MP2-second P-type transistor, MP3-third P-type transistor, MP4-fourth P-type transistor, MN1-first N-type transistor, MN2-second N-type transistor, MN3-third N-type transistor, MN4-fourth N-type transistor, MN5-fifth N-type transistor, MN6-sixth N-type transistor, MN7-seventh N-type transistor, MN8-eighth N-type transistor, I-first input terminal, O-first output terminal, I’-second input terminal, O’-second output terminal.

DETAILED DESCRIPTION

In order to clearly describe the technical solutions of the embodiments of the present invention, in the embodiments of the present invention, words such as "first" and "second" are used to distinguish between identical or similar items with substantially identical functions and effects. For example, the first threshold and the second threshold are only used to distinguish between different thresholds, and do not limit their order. Those skilled in the art can understand that words such as "first" and "second" do not limit the quantity and execution order, and words such as "first" and "second" do not necessarily limit them to be different.

It should be noted that, in the present invention, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the present invention should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

In the present invention, "at least one" means one or more, and "plurality" means two or more. "And/or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and/or B can mean: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character "/" generally indicates that the associated objects before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can mean: a, b, c, the combination of a and b, the combination of a and c, the combination of b and c, or the combination of a, b and c, where a, b, c can be single or multiple.

There is currently an in-memory computing method that separates the computing unit from the storage array. SRAM (Static Random Access Memory) is composed of a storage array and a computing unit array to form a computing structure. Their gates are connected to the SRAM complementary bit lines (BLP and BLN) and the intermediate input lines INP and INN. The data (W) stored in the SRAM selects the complementary bit lines (BLP and BLN) to connect to the computing unit. The bit operation between IN and W can be reconfigured to AND (INP = IN, INN = 0) through the input data of the computing unit. and

The SRAM storage array is a typical SRAM storage cell structure with 6 transistors. The calculation unit consists of two parts. The first part is a PMOS as a pre-charge tube, and the second part is a pull-down network composed of four transistors. The calculation unit also consists of 6 transistors inside the calculation unit to form a typical calculation unit structure. When the clock is 0, the pre-charged PMOS transistor is turned on and pulled to VDD through the output node voltage. During this period, the pull-down network is not turned on, so the calculation unit does not generate any static power consumption during the pre-charge period. When the time is 1, the pre-charge transistor is turned off, and the pull-down network is turned on. The pull-down network is conditionally discharged according to the input value and the topological structure of the pull-down network. If the input turns on the pull-down network, a low-resistance path is formed between the output node and GND, and the output node is discharged to GND. This calculation unit can only have one calculation in a calculation cycle. Compared with CMOS static logic, this calculation unit saves transistors in the pull-up network inside the sub-array.

Although this computing array can well implement and switch various computing functions, the total power consumption of the dynamic logic circuit used in the computing array will be significantly higher than that of the static logic gate because it is controlled by the clock cycle and there is a flip in each cycle. Due to the periodic pre-charge and discharge operations, dynamic logic usually exhibits high switching activity. And there is only one output, and an additional inverter is required when outputting the reverse signal of the output signal, which increases the number of transistors, thus inevitably causing the circuit delay of the computing circuit and the increase of power consumption.

In view of this, the present invention provides an in-memory computing device, which has a computing unit with a dual-end output function, and combines the computing unit with a storage unit to form an SRAM array integrating storage function and computing function. The computing unit can simultaneously output a logic result and a reverse signal of the logic result by simultaneously inputting a signal and an inverse signal of the signal. There is no need to additionally configure an inverter when outputting the reverse signal, which saves the number of transistors in the circuit and does not cause circuit delays and increased power consumption of the computing circuit. This solves the problem in the prior art that an additional inverter needs to be configured when outputting the reverse signal of the signal, resulting in circuit delays and increased power consumption.

Next, the technical solution of the present invention is described in detail with reference to the accompanying drawings:

Please refer to Figure 1, which is a schematic diagram of the structure of any in-memory computing column in an in-memory computing device provided by the present invention. It should be noted that the in-memory computing device represents an in-memory computing array that can be composed of multiple storage units and multiple computing units, and any in-memory computing column in the in-memory computing array can include multiple storage units and at least one computing unit.

In FIG1 , the storage device may include:

A computing unit 100 and a plurality of storage units 200, wherein the computing unit 100 is connected to the storage unit 200; specifically, the computing unit 100 is connected to the plurality of storage units 200 via a bit line BL and a bit line non-BLB. It should be noted that the scheme has a plurality of storage units identical to the storage unit 200, and the plurality of storage units are connected to the bit line BL and the bit line non-BLB points in parallel, as shown in FIG1 where the dotted line position represents a storage unit identical to the plurality of storage units 200. Of course, in order to increase the computing power of the SRAM array and improve computing efficiency, the computing unit 100 may also include a plurality of, such as 2 or 4; its connection method may also be connected to the bit line BL and the bit line non-BLB in the same manner as the computing unit 100; this is not specifically limited in the scheme.

The computing unit 100 may include a first computing subunit 110 and a second computing subunit 120 ; the first computing subunit 110 is connected to the second computing subunit 120 .

Among them, the first calculation subunit 110 includes a first input terminal I and a first output terminal O; the first input terminal I is used to receive a first input signal, and the first output terminal O is used to output an inverse signal of the first output signal; the second calculation subunit 120 includes a second input terminal I' and a second output terminal O'; the second input terminal I' is used to receive an inverse signal of the first input signal, and the second output terminal O' is used to output the first output signal.

Based on this, the present invention provides an in-memory computing device, which is provided with a computing unit with a dual-end output function, which is combined with a storage array to form an SRAM array integrating storage function and computing function. It can realize the simultaneous output of logic and result and the reverse signal of the logic and result, and there is no need to additionally configure an inverter when outputting the reverse signal. This solves the problem in the prior art that when the original signal and the reverse signal of the signal are output simultaneously, an additional inverter needs to be configured, resulting in a delay of the reverse signal relative to the original signal and an increase in power consumption.

Preferably, the first calculation subunit 110 includes a first P-type transistor MP1, a first N-type transistor MN1 and a fourth N-type transistor MN4; the source of the first P-type transistor MP1 is connected to the power supply terminal VDD, the drain of the first P-type transistor MP1 is connected to the drain of the first N-type transistor MN1, and the drain of the first P-type transistor MP1 is connected to the first output terminal O; the gate of the first N-type transistor MN1 is connected to the bit line BL of the in-memory calculation device, the source of the first N-type transistor MN1 is connected to the drain of the fourth N-type transistor MN4; the source of the fourth N-type transistor MN4 is grounded, and the gate of the fourth N-type transistor MN4 is connected to the first input terminal.

Preferably, the second calculation subunit 120 includes a second P-type transistor MP2, a second N-type transistor MN2 and a third N-type transistor MN3; the source of the second P-type transistor MP2 is connected to the power supply terminal VDD, the drain of the second P-type transistor MP2 is connected to the drain of the second N-type transistor MN2, the drain of the second P-type transistor MP2 is connected to the gate of the first P-type transistor MP1, the gate of the second P-type transistor MP2 is connected to the drain of the first P-type transistor MP1, and the drain of the second P-type transistor MP2 is connected to the second output terminal O’; the gate of the second N-type transistor MN2 is connected to the second input terminal I’, and the source of the second N-type transistor MN2 is grounded; the drain of the third N-type transistor MN3 is connected to the drain of the second N-type transistor MN2, the gate of the third N-type transistor MN3 is connected to the bit line non-BLB of the in-memory calculation device, and the source of the third N-type transistor MN3 is grounded.

Preferably, the plurality of storage cells 200 include a third P-type transistor MP3, a fifth N-type transistor MN5 and an eighth N-type transistor MN8; the source of the third P-type transistor MP3 is connected to the power supply terminal VDD, the drain of the third P-type transistor MP3 is connected to the drain of the fifth N-type transistor MN5, and the gate of the third P-type transistor MP3 is connected to the gate of the fifth N-type transistor MN5; the drain of the fifth N-type transistor MN5 is connected to the drain of the eighth N-type transistor MN8, and the source of the fifth N-type transistor MN5 is grounded; the source of the eighth N-type transistor MN8 is connected to the bit line BL of the in-memory computing device, and the gate of the eighth N-type transistor MN8 is connected to the word line WL of the in-memory computing device.

Preferably, the plurality of storage cells 200 further include a fourth P-type transistor MP4, a sixth N-type transistor MN6 and a seventh N-type transistor MN7; the source of the fourth P-type transistor MP4 is connected to the power supply terminal VDD, the drain of the fourth P-type transistor MP4 is connected to the drain of the sixth N-type transistor MN6, the gate of the fourth P-type transistor MP4 is connected to the drain of the third P-type transistor MP3, the drain of the fourth P-type transistor MP4 is connected to the gate of the third P-type transistor MP3, and the gate of the fourth P-type transistor MP4 is connected to the gate of the sixth N-type transistor MN6; the drain of the seventh N-type transistor MN7 is connected to the drain of the sixth N-type transistor MN6, the gate of the seventh N-type transistor MN7 is connected to the word line WL of the in-memory computing device, and the source of the seventh N-type transistor MN7 is connected to the bit line non-BLB of the in-memory computing device.

Based on this, the structural diagram of the calculation column in the SRAM memory is obtained, which includes the SRAM storage unit and the two-terminal output calculation unit. In the SRAM storage unit, MP3, MP4, MN5 and MN6 form a cross-coupled inverter, and Q and QB are storage nodes. MN7 and MN8 are access transistors, and MP1, MP2, MN1, MN2, MN3, and MN4 are calculation transistors; the input signal of each circuit has a complementary form and also produces complementary outputs. The feedback mechanism formed by MP1, MP2 and MN1, MN2, MN3, and MN4 ensures that the load device is turned off when it is not needed, and the calculation circuit is shared by one per column. When the output signal and the inverse signal of the output signal need to be output at the same time, the input signal and the inverse signal of the input signal are input at the same time to perform logical and calculation.

Specifically: when MP1, MN1, and MN4 perform a NAND operation, the first output terminal O outputs the inverse signal of the first output signal, that is, Where A represents the input signal value corresponding to the first input terminal I, and B represents the signal value output by the storage node Q. When MP2, MN2, and MN3 perform a non-OR operation, the second output terminal O' outputs the first output signal, that is, It should be noted that the meanings of A and B in other places in the specification are the same as those represented here; the word line WL is row-based, the bit line BL and the bit line non-BLB are column-based, and when the SRAM performs normal SRAM operations such as hold operations, read operations, and write operations, it is the same as a conventional SRAM.

In a second aspect, the present invention further provides an in-memory computing method, which is applied to an in-memory computing device; the in-memory computing device includes multiple in-memory computing columns, and any one of the in-memory computing columns may include multiple storage units and at least one computing unit, and the internal circuit structure of the computing unit and the multiple storage units is the same as the circuit structure of the computing unit and the multiple storage units in the in-memory computing column of the in-memory computing device described in the first aspect. Please refer to Figure 2, which is a schematic diagram of the main flow of computing operations of any one in-memory computing column in an in-memory computing device provided by the present invention.

In FIG. 2 , the method may include:

Step 210: The calculation unit receives an input signal, an inverse signal of the input signal, and a bit line signal and a bit line inverse signal sent by the plurality of storage units through bit lines.

Step 220: Based on the input signal, the inverse signal of the input signal, the bit line signal and the bit line inverse signal, use preset transistors to perform NAND operations and NOR operations, so that the calculation unit simultaneously outputs an output signal and the inverse signal of the output signal.

In step 210 to step 220, based on the internal structure of the computing unit, the output signal and the inverse signal of the output signal can be output simultaneously. In combination with the circuit structure described in FIG. 1 , MP1, MN1, and MN4 perform a NAND operation, that is, the first output terminal O outputs the inverse signal of the first output signal, that is, the output When any input of MN1 or MN4 is at a low level, the level of the first output terminal O is controlled by MP1. When MP1 is turned on, the level of the first output terminal O is pulled to VDD, that is, if any input of A or B is 0, the output of the first output terminal O must be 1. Only when the inputs of MN1 and MN4 are at high levels at the same time, MN1 and MN4 are turned on at the same time, and the level of the first output terminal O is pulled to a low potential, which can be expressed by the formula: Among them, MP2, MN2, and MN3 perform an OR operation, that is, the output When any input A or B in MN1 or MN4 is at a low level, the inverting input signal in MN2 or MN3 must be at a high level, one of MN2 or MN3 must be turned on, the level at point O is pulled to the ground potential, and MP1 is turned on; when both input A or B in MN1 or MN4 are at a high level, both inputs of MN2 or MN3 are at a low level, both MN2 or MN3 are turned off, and the level at point O is controlled by MP2, which can be expressed by the formula:

It should be noted that, in the examples disclosed in the specification of the present invention, IN represents the signal A corresponding to the first input terminal O, The signal represents the inverse signal of the output signal corresponding to the first output terminal O, the signal B represents the signal Q input from the bit line BL to the first N-type transistor MN1, Indicates the signal corresponding to the second input terminal I' OUT represents the output signal corresponding to the second output terminal O'; FIG. 3 is based on FIG. 1 and only marks the input and output directions of the signal. Its circuit structure is the same as the circuit structure described in FIG. 1.

Further, in step 220, please refer to FIG3, which is a schematic diagram of signal input and output corresponding to the calculation operation of any one column of the in-memory calculation column in the in-memory calculation device provided by the present invention. In FIG3, the preset transistors may include a first P-type transistor MP1, a second P-type transistor MP2, a first N-type transistor MN1, a second N-type transistor MN2, a third N-type transistor MN3, and a fourth N-type transistor MN4.

Specifically, based on the input signal, the inverse signal of the input signal, the bit line signal and the bit line inverse signal, a preset transistor is used to perform a NAND operation and a NOR operation, so that the calculation unit simultaneously outputs an output signal and an inverse signal of the output signal. The following four implementations may be included:

Method 1: When the input signal is 0 and the bit line signal is 0, a logic AND operation is performed on the first P-type transistor MP1, the first N-type transistor MN1 and the fourth N-type transistor MN4, so that the calculation unit outputs the inverse signal 1 of the output signal; and a logic OR operation is performed on the second P-type transistor MP2, the second N-type transistor MN2 and the third N-type transistor MN3, so that the calculation unit outputs the output signal 0.

As an example, in FIG3, when IN=0, BL=Q=0 is set, then BLB＝QB＝1; further, MP1, MN1, and MN4 can be controlled to perform logical AND operations, that is, output And control MP2, MN2, MN3 to perform or not operation, that is, output

Method 2: When the input signal is 0 and the bit line signal is 1, a logic AND operation is performed on the first P-type transistor MP1, the first N-type transistor MN1 and the fourth N-type transistor MN4, so that the calculation unit outputs the inverse signal 1 of the output signal; and a logic OR operation is performed on the second P-type transistor MP2, the second N-type transistor MN2 and the third N-type transistor MN3, so that the calculation unit outputs the output signal 0.

As an example, in FIG3, when IN=0, BL=Q=1 is set, then BLB＝QB＝0; further, MP1, MN1, and MN4 can be controlled to perform logical AND and NOT operations, that is, output And control MP2, MN2, MN3 to perform OR operation, that is, output

Method 3: When the input signal is 1 and the bit line signal is 0, a logic AND operation is performed on the first P-type transistor MP1, the first N-type transistor MN1 and the fourth N-type transistor MN4, so that the calculation unit outputs the inverse signal 1 of the output signal; and a logic OR operation is performed on the second P-type transistor MP2, the second N-type transistor MN2 and the third N-type transistor MN3, so that the calculation unit outputs the output signal 0.

As an example, in FIG3, when IN=1, BL=Q=0 is set, then BLB＝QB＝1; further control MP1, MN1, MN4 to perform logical AND operation, that is, output Control MP2, MN2, MN3 to perform OR operation, that is, output

Method 4: When the input signal is 1 and the bit line signal is 1, a logic AND operation is performed on the first P-type transistor MP1, the first N-type transistor MN1 and the fourth N-type transistor MN4, so that the calculation unit outputs the inverse signal 0 of the output signal; and a logic OR operation is performed on the second P-type transistor MP2, the second N-type transistor MN2 and the third N-type transistor MN3, so that the calculation unit outputs the output signal 1.

As an example, in FIG3, when IN=1, BL=Q=1 is set, then BLB＝QB＝0; further control MP1, MN1, MN4 to perform logical AND operation, that is, output Control MP2, MN2, MN3 to perform OR operation, that is, output

Based on this, the above four control logic methods that can realize the calculation unit of the SRAM to output the output signal and the inverse signal of the output signal at the same time can be summarized as the contents in Table 1.

Table 1 Comparison table of output signals and inverse signals of output signals output by the computing unit at the same time for different input conditions under the control logic of the computing unit

Furthermore, when the SRAM performs a holding operation, a read operation, a write operation, and other SRAM normal operations, it is the same as a normal SRAM.

1. Keep operating

The cell is in hold operation. In the hold operation, the word line WL is kept at a low level, MN7 and MN8 are turned off, Q and QB are not connected to the bit line, neither the signal can be read nor written, the cell storage node is not coupled with the external signal, and the cell can stably hold the data.

2. Read operation

Before the read operation, BL and BLB are precharged to a high level. When performing a read operation, WL remains at a high level, so that transistors MN7 and MN8 are turned on. When reading "1", Q is "1" and QB is "0". A low-resistance path is formed between the bit line BLB and GND through MN7, generating a read current, while MN8 is turned off, and there is no read current on the BL side. The bit line voltage is then amplified and output to the full swing through the sense amplifier to achieve a read operation. The same applies to reading "0".

3. Write operation

In the write operation mode, the voltages of BL and BLB are converted into corresponding high and low levels according to the write data input by the input module. BL is 0, BLB is 1, WL is turned on, the internal node Q starts to discharge through BL, and BLB charges QB, forming positive feedback. When Q discharges below the flip level of the coupled inverter, the data stored in the cell will flip, the QB node becomes 1, and Q is 0, completing the write operation; since the storage array is a completely symmetrical structure, when Q and QB are 0 and 1 respectively, the read and write operations are similar to the above process and will not be repeated.

Based on this, the present invention proposes an in-memory computing method that can be applied to an in-memory computing device provided in the first aspect. By adding computing units to the SRAM array and configuring input signals and their inverse signals, the logical AND function and the logical OR function can be realized. During its operation, the function of simultaneously outputting the output signal and its inverse signal can be realized, and no additional inverter is required, and there will be no problems of circuit delay and increased power consumption; at the same time, the number of transistors in the circuit is saved, and the use cost of transistors is reduced.

Although the present invention is described herein in conjunction with various embodiments, in the process of implementing the claimed invention, those skilled in the art may understand and implement other variations of the disclosed embodiments by viewing the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "one" or "an" does not exclude multiple situations. A single processor or other unit may implement several functions listed in the claims. Certain measures are recorded in different dependent claims, but this does not mean that these measures cannot be combined to produce good results.

Although the present invention has been described in conjunction with specific features and embodiments thereof, it is apparent that various modifications and combinations may be made thereto without departing from the spirit and scope of the present invention. Accordingly, this specification and the accompanying drawings are merely exemplary illustrations of the present invention as defined by the appended claims and are deemed to cover any and all modifications, variations, combinations or equivalents within the scope of the present invention. Obviously, those skilled in the art may make various modifications and variations to the present invention without departing from the spirit and scope of the present invention. Thus, the present invention is intended to include such modifications and variations if they fall within the scope of the claims of the present invention and their equivalents.

Claims (10)

1. An in-memory computing device, characterized in that the in-memory computing device comprises a plurality of in-memory computing columns, the in-memory computing columns comprise a computing unit and a plurality of storage units, the computing unit is connected to the plurality of storage units; The computing unit comprises a first computing subunit and a second computing subunit; the first computing subunit is connected to the second computing subunit; The first calculation subunit includes a first input terminal and a first output terminal; the first input terminal is used to receive a first input signal, and the first output terminal is used to output an inverse signal of the first output signal; The second calculation subunit includes a second input terminal and a second output terminal; the second input terminal is used to receive the inverse signal of the first input signal, and the second output terminal is used to output the first output signal. 2. The device according to claim 1, wherein the first computing subunit comprises a first P-type transistor, a first N-type transistor and a fourth N-type transistor; The source of the first P-type transistor is connected to the power supply terminal, the drain of the first P-type transistor is connected to the drain of the first N-type transistor, and the drain of the first P-type transistor is connected to the first output terminal; the gate of the first N-type transistor is connected to the bit line of the in-memory computing device, the source of the first N-type transistor is connected to the drain of the fourth N-type transistor; the source of the fourth N-type transistor is grounded, and the gate of the fourth N-type transistor is connected to the first input terminal. 3. The device according to claim 2, wherein the second computing subunit comprises a second P-type transistor, a second N-type transistor and a third N-type transistor; The source of the second P-type transistor is connected to the power supply terminal, the drain of the second P-type transistor is connected to the drain of the second N-type transistor, the drain of the second P-type transistor is connected to the gate of the first P-type transistor, the gate of the second P-type transistor is connected to the drain of the first P-type transistor, and the drain of the second P-type transistor is connected to the second output terminal; The gate of the second N-type transistor is connected to the second input terminal, and the source of the second N-type transistor is grounded; The drain of the third N-type transistor is connected to the drain of the second N-type transistor, the gate of the third N-type transistor is disconnected from the bit line of the in-memory computing device, and the source of the third N-type transistor is grounded. 4. The device of claim 1, wherein the memory cell comprises a third P-type transistor, a fifth N-type transistor and an eighth N-type transistor; The source of the third P-type transistor is connected to the power supply terminal, the drain of the third P-type transistor is connected to the drain of the fifth N-type transistor, and the gate of the third P-type transistor is connected to the gate of the fifth N-type transistor; the drain of the fifth N-type transistor is connected to the drain of the eighth N-type transistor, and the source of the fifth N-type transistor is grounded; the source of the eighth N-type transistor is connected to the bit line of the in-memory computing device, and the gate of the eighth N-type transistor is connected to the word line of the in-memory computing device. 5. The device of claim 4, wherein the storage unit comprises a fourth P-type transistor, a sixth N-type transistor and a seventh N-type transistor; The source of the fourth P-type transistor is connected to the power supply terminal, the drain of the fourth P-type transistor is connected to the drain of the sixth N-type transistor, the gate of the fourth P-type transistor is connected to the drain of the third P-type transistor, the drain of the fourth P-type transistor is connected to the gate of the third P-type transistor, and the gate of the fourth P-type transistor is connected to the gate of the sixth N-type transistor; the drain of the seventh N-type transistor is connected to the drain of the sixth N-type transistor, the gate of the seventh N-type transistor is connected to the word line of the in-memory computing device, and the source of the seventh N-type transistor is not connected to the bit line of the in-memory computing device. 6. An in-memory computing method, characterized in that the in-memory computing method is applied to an in-memory computing device; the in-memory computing device includes a plurality of in-memory computing columns, the in-memory computing columns include a computing unit and a plurality of storage units; the method comprises: The calculation unit receives an input signal, an inverse signal of the input signal, and a bit line signal and a bit line inverse signal sent by a plurality of the storage units through a bit line; Based on the input signal, the inverted signal of the input signal, the bit line signal and the bit line inverted signal, a NAND operation and a NOR operation are performed using preset transistors, so that the calculation unit simultaneously outputs an output signal and an inverted signal of the output signal. 7. The method according to claim 6, wherein the preset transistors include a first P-type transistor, a second P-type transistor, a first N-type transistor, a second N-type transistor, a third N-type transistor, and a fourth N-type transistor; The method of using a preset transistor to perform a NAND operation and a NOR operation based on the input signal, the inverted signal of the input signal, the bit line signal, and the bit line inverted signal, so that the calculation unit simultaneously outputs an output signal and an inverted signal of the output signal, includes: When the input signal is 0 and the bit line signal is 0, a logic AND operation is performed on the first P-type transistor, the first N-type transistor and the fourth N-type transistor, so that the calculation unit outputs an inverse signal 1 of the output signal; And, a logic OR operation is performed on the second P-type transistor, the second N-type transistor and the third N-type transistor, so that the calculation unit outputs the output signal 0. 8. The method according to claim 7, wherein the step of performing a NAND operation and a NOR operation using a preset transistor based on the input signal, the inverted signal of the input signal, the bit line signal, and the bit line inverted signal, and outputting an output signal and an inverted signal of the output signal at the same time, comprises: When the input signal is 0 and the bit line signal is 1, a logic AND operation is performed on the first P-type transistor, the first N-type transistor and the fourth N-type transistor, so that the calculation unit outputs an inverse signal 1 of the output signal; And, a logic OR operation is performed on the second P-type transistor, the second N-type transistor and the third N-type transistor, so that the calculation unit outputs the output signal 0. 9. The method according to claim 7, wherein the step of performing a NAND operation and a NOR operation on a preset transistor based on the input signal, the inverted signal of the input signal, the bit line signal, and the bit line inverted signal, and outputting an output signal and an inverted signal of the output signal at the same time, comprises: When the input signal is 1 and the bit line signal is 0, a logic AND operation is performed on the first P-type transistor, the first N-type transistor and the fourth N-type transistor, so that the calculation unit outputs an inverse signal 1 of the output signal; And, a logic OR operation is performed on the second P-type transistor, the second N-type transistor and the third N-type transistor, so that the calculation unit outputs the output signal 0. 10. The method according to claim 7, wherein the step of performing a NAND operation and a NOR operation using a preset transistor based on the input signal, the inverted signal of the input signal, the bit line signal, and the bit line inverted signal, and outputting an output signal and an inverted signal of the output signal at the same time, comprises: When the input signal is 1 and the bit line signal is 1, a logic AND operation is performed on the first P-type transistor, the first N-type transistor and the fourth N-type transistor, so that the calculation unit outputs an inverse signal 0 of the output signal; And, a logic OR operation is performed on the second P-type transistor, the second N-type transistor and the third N-type transistor, so that the calculation unit outputs the output signal 1.