CN118468775A - Circuit system, method, device, medium and program product for scan test - Google Patents

Abstract

Embodiments of the present disclosure provide circuitry, methods, apparatus, devices, storage media, and program products for scan testing, relating to the field of chip design tools. The provided circuitry includes a first scan cell and an observation cell in series with the first scan cell in a scan chain. The first scanning unit is configured to generate a first shift value based on at least a portion of the test vector. The observation unit includes a signal combiner and a second scanning unit. The signal combiner is configured to generate, in a shift capture mode, a first combined value at a first output of the signal combiner based on a combination of a value at an observation point in a circuit under test and the first shift value output by the first scan unit. The second scanning unit is configured to generate a scanning observation based on the first combined value in the shift capture mode. In this way, with a scan chain composed of a normal scan unit and an observation unit, the value at the observation point can be captured during shifting, thereby improving the test efficiency.

Description

Circuit system, method, device, medium and program product for scan test

Technical Field

Embodiments of the present disclosure generally relate to the field of chip design tools. More specifically, embodiments of the present disclosure relate to circuit systems, methods, devices, apparatuses, computer-readable storage media, and computer program products for scan testing.

Background Art

Electronic design automation (EDA) software is widely used in chip design. With the help of various EDA software, engineers can easily carry out chip design, such as architecture design and register transfer level (RTL) code design, synthesis, design for test (DFT), physical development and signoff.

As an important part of the chip design and manufacturing process, chip testing can be used to select chips with defects due to problems such as process and materials during the manufacturing and packaging process. Chip testing can be performed efficiently using EDA tools. Usually, DFT structures such as scan chains can be added to the chip during the design phase. In the test phase, a test vector generator can be used to generate a test pattern to input into the chip to be tested. The chip can be tested by comparing whether the test response of the chip under test is consistent with the expected response. With the continuous improvement of chip integration and complexity, the difficulty of chip testing has also increased. Therefore, an efficient chip testing solution is expected to reduce the time and cost of chip testing.

Summary of the invention

In view of the above problems, an embodiment of the present disclosure provides a solution for scan testing.

In a first aspect of the present disclosure, a circuit system for scan testing is provided. The circuit system includes: a first scan unit and an observation unit connected in series with the first scan unit in a scan chain. The first scan unit is configured to generate a first shift value based on at least a portion of a test vector. The observation unit includes a signal combiner and a second scan unit. The signal combiner is configured to generate a first combination value at a first output of the signal combiner based on a combination of a value at an observation point in a circuit to be tested and the first shift value output by the first scan unit in a shift capture mode. The second scan unit is configured to generate a scan observation value based on the first combination value in the shift capture mode. In this way, using a scan chain composed of a normal scan unit and an observation unit, the value at the observation point can be captured during the shift process, thereby improving the test efficiency.

In some embodiments of the first aspect, the signal combiner is further configured to generate a second combination value at the first output of the signal combiner based on the first shift value output by the first scanning unit in a shift mode; and the second scanning unit is further configured to generate a second shift value based on the second combination value in the shift mode, and the second shift value is the same as the first shift value output by the first scanning unit.

In some embodiments of the first aspect, the signal combiner is further configured to generate, in a capture mode, a third combined value at a second output of the signal combiner based on a value at the observation point or a combination of the value at the observation point and a value at a functional logic connection point in the circuit under test; and the second scanning unit is further configured to generate, in the capture mode, a captured value identical to the third combined value based on the third combined value.

In some embodiments of the first aspect, the signal combiner includes: an AND gate configured to receive an enable signal of the shift capture mode and the value at the observation point; and a first XOR gate configured to generate a value at the first output of the signal combiner based on an output of the AND gate and the first shift value.

In some embodiments of the first aspect, the signal combiner further comprises a second XOR gate configured to generate a value at a second output of the signal combiner based on an output of the AND gate and a value at a functional logic connection point in the circuit under test. In this way, ordinary scan units in a scan chain can be reused, thereby saving hardware cost and area overhead.

In some embodiments of the first aspect, in the shift mode, the observation unit in a current clock cycle outputs a value based on the first shift value output by the first scanning unit in a previous clock cycle.

In some embodiments of the first aspect, in the shift capture mode, the observation unit in the current clock cycle outputs a value based on the exclusive OR of the first shift value output by the first scanning unit in the previous clock cycle and the value at the observation point captured in the current clock cycle.

In some embodiments of the first aspect, in the capture mode, the observation unit in a current clock cycle outputs a value based on a value at the observation point captured in the current clock cycle.

In some embodiments of the first aspect, in the capture mode, the observation unit in a current clock cycle outputs a value based on an exclusive OR of a value at the observation point captured in the current clock cycle and a value at the functional logic connection point.

In some embodiments of the first aspect, circuitry for testing a circuit comprises a plurality of scan chains including the scan chain, wherein the plurality of scan chains are in a compressed scan mode or a non-compressed scan mode.

In some embodiments of the first aspect, the observation unit is located in the middle or tail of the scan chain. In some embodiments of the first aspect, the sum of the connection distance between the observation unit and the observation point and the connection distance between the observation unit and the first scanning unit is less than a predetermined threshold. In this way, the observation unit can be flexibly arranged, thereby reducing the difficulty of wiring.

In a second aspect of the present disclosure, a circuit system for scan testing is provided. The circuit system includes: a first scan unit; and an observation unit, which is connected in series with the first scan unit in a scan chain, and the observation unit includes: a signal combiner, which is configured to generate a first combination value at a first output of the signal combiner based on a combination of a value at an observation point in the circuit to be tested and at least a part of a test vector in a shift capture mode; and a second scan unit, which is configured to generate a scan observation value based on the first combination value in the shift capture mode. The first scan unit is configured to generate a first shift value based on the scan observation value in the shift capture mode. In this way, by using a scan chain composed of a normal scan unit and an observation unit, the value at the observation point can be captured during the shift process, thereby improving the test efficiency.

In some embodiments of the second aspect, the signal combiner is further configured to generate a second combined value at the first output of the signal combiner based on at least a portion of the test vector in a shift mode; the second scanning unit is further configured to generate a second shift value based on the second combined value in the shift mode, the second shift value being the same as the at least a portion of the test vector; and the first scanning unit is further configured to generate a third shift value based on the second shift value in the shift mode, the third shift value being the same as the second shift value.

In some embodiments of the second aspect, the signal combiner is further configured to generate a third combined value at a second output of the signal combiner in a capture mode based on the value at the observation point or a combination of the value at the observation point and the value at a first functional logic connection point in the circuit under test; the second scanning unit is further configured to generate a captured value identical to the third combined value in the capture mode based on the third combined value; and the first scanning unit is further configured to generate at least a portion of a test response in the capture mode based on the value at the second functional logic connection point in the circuit under test.

In some embodiments of the second aspect, the signal combiner includes: an AND gate configured to receive an enable signal of the shift capture mode and a value at the observation point; and a first XOR gate configured to generate a value at the first output of the signal combiner based on an output of the AND gate and at least a portion of the test vector.

In some embodiments of the second aspect, the signal combiner further comprises a second XOR gate configured to generate a value at a second output of the signal combiner based on an output of the AND gate and a value at a functional logic connection point in the circuit under test.

In some embodiments of the second aspect, the observation unit is located at the head of the scan chain.

In a third aspect of the present disclosure, a method for testing a circuit to be tested is provided. The method includes: shifting a test vector into a scan chain in a shift capture mode; and generating a scan observation value based on at least a portion of the test vector and a value at an observation point in the circuit to be tested in the shift capture mode. The scan chain is configured to include: a first scan unit configured to generate a first shift value based on the at least a portion of the test vector; and an observation unit connected in series with the first scan unit, and the observation unit includes: a signal combiner configured to generate a first combination value based on a combination of the value at the observation point and the first shift value output by the first scan unit in the shift capture mode; and a second scan unit configured to generate the scan observation value based on the first combination value in the shift capture mode.

In some embodiments of the third aspect, the method also includes shifting the test vector into the scan chain in a shift mode, wherein: the signal combiner is further configured to generate a second combination value at the first output of the signal combiner based on the first shift value output by the first scan unit in the shift mode; and the second scan unit is further configured to generate a second shift value based on the second combination value in the shift mode, and the second shift value is the same as the first shift value output by the first scan unit.

In some embodiments of the third aspect, the method also includes obtaining a captured value in a capture mode, wherein: the signal combiner is further configured to generate a third combined value at a second output of the signal combiner in the capture mode based on the value at the observation point or a combination of the value at the observation point and the value at a functional logic connection point in the circuit under test; and the second scanning unit is further configured to generate the captured value that is the same as the third combined value in the capture mode based on the third combined value.

In a fourth aspect of the present disclosure, a method for testing a circuit under test is provided. The method includes: shifting a test vector into a scan chain in a shift capture mode; and generating a scan observation value based on at least a portion of the test vector and a value at an observation point in the circuit under test in the shift capture mode, wherein the scan chain is configured to include: a first scan unit configured to generate a first shift value based on at least a portion of the test vector; and an observation unit connected in series with the first scan unit, and the observation unit includes: a signal combiner configured to generate a first combination value based on a combination of the value at the observation point and the first shift value output by the first scan unit in the shift capture mode; and a second scan unit configured to generate the scan observation value based on the first combination value in the shift capture mode.

In some embodiments of the fourth aspect, the method also includes shifting the test vector into the scan chain in a shift mode, wherein: the signal combiner is further configured to generate a second combination value at the first output of the signal combiner based on at least a portion of the test vector in the shift mode; the second scan unit is further configured to generate a second shift value based on the second combination value in the shift mode, the second shift value being the same as the at least a portion of the test vector; and the first scan unit is further configured to generate a third shift value based on the second shift value in the shift mode, the third shift value being the same as the second shift value.

In some embodiments of the fourth aspect, the method also includes obtaining a captured value in a capture mode, wherein: the signal combiner is further configured to generate a third combined value at a second output of the signal combiner in the capture mode based on the value at the observation point or a combination of the value at the observation point and the value at a first functional logic connection point in the circuit under test; the second scanning unit is further configured to generate the captured value identical to the third combined value in the capture mode based on the third combined value; and the first scanning unit is further configured to generate at least a part of a test response in the capture mode based on the value at the second functional logic connection point in the circuit under test.

In a fifth aspect of the present disclosure, a device is provided, comprising: a shift unit configured to shift a test vector into a scan chain in a shift capture mode; and a capture unit configured to generate a scan observation value based on at least a portion of the test vector and a value at an observation point in the circuit to be tested in the shift capture mode, wherein the scan chain is configured to include: a first scan unit configured to generate a first shift value based on at least a portion of the test vector; and an observation unit connected in series with the first scan unit, and the observation unit includes: a signal combiner configured to generate a first combination value based on a combination of the value at the observation point and the first shift value output by the first scan unit in the shift capture mode; and a second scan unit configured to generate the scan observation value based on the first combination value in the shift capture mode.

In a sixth aspect of the present disclosure, a device is provided, comprising: a shift unit configured to shift a test vector into a scan chain in a shift capture mode; and a capture unit configured to generate a scan observation value based on at least a portion of the test vector and a value at an observation point in a circuit to be tested in the shift capture mode, wherein the scan chain is configured to include: a first scan unit; and an observation unit connected in series with the first scan unit in the scan chain, and the observation unit includes: a signal combiner configured to generate a first combination value at a first output of the signal combiner based on a combination of the value at the observation point in the circuit to be tested and the at least a portion of the test vector in the shift capture mode; and a second scan unit configured to generate the scan observation value based on the first combination value in the shift capture mode; and wherein the first scan unit is configured to generate a first shift value based on the scan observation value in the shift capture mode.

In the seventh aspect of the present disclosure, an electronic device is provided, comprising: at least one computing unit; and at least one memory, wherein the at least one memory is coupled to the at least one computing unit and stores instructions for execution by the at least one computing unit, and when the instructions are executed by the at least one computing unit, the device implements the method provided in the third aspect or the fourth aspect.

In an eighth aspect of the present disclosure, a computer-readable storage medium is provided, on which a computer program is stored, wherein the computer program is executed by a processor to implement the method provided in the third aspect or the fourth aspect.

In a ninth aspect of the present disclosure, a computer program product is provided, comprising computer executable instructions, which implement part or all of the steps of the method of the third aspect or the fourth aspect when the instructions are executed by a processor.

It can be understood that the apparatus of the fifth and sixth aspects, the electronic device of the seventh aspect, the computer storage medium of the eighth aspect, or the computer program product of the ninth aspect provided above are all used to execute the method provided by the third aspect or the fourth aspect. The explanation or description of the first aspect or the second aspect also applies to the third aspect, the fourth aspect, the fifth aspect, the sixth aspect, the seventh aspect, the eighth aspect, and the ninth aspect. In addition, the beneficial effects that can be achieved by the third aspect, the fourth aspect, the fifth aspect, the sixth aspect, the seventh aspect, the eighth aspect, and the ninth aspect can refer to the beneficial effects in the corresponding circuit system, which will not be repeated here.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other features, advantages and aspects of the embodiments of the present disclosure will become more apparent with reference to the following detailed description in conjunction with the accompanying drawings. In the accompanying drawings, the same or similar reference numerals represent the same or similar elements, wherein:

FIG1 shows a flow chart of the chip design and manufacturing process;

FIG2 shows a schematic diagram of an example environment in which various embodiments of the present disclosure can be implemented;

FIG3 shows a schematic diagram of an observation unit according to some embodiments of the present disclosure;

FIG4 shows a first example schematic diagram of an observation unit according to some embodiments of the present disclosure;

FIG5 shows a schematic diagram of a second example of an observation unit according to some embodiments of the present disclosure;

FIG6 is a schematic diagram showing control signals and clock signals in a scan test according to some embodiments of the present disclosure;

FIG7 shows a schematic diagram of a circuit system for scan testing according to some embodiments of the present disclosure;

FIG8 is a schematic diagram showing a circuit system for scan testing using test compression technology according to some embodiments of the present disclosure;

FIG9 is a schematic block diagram showing an example process of a method for scan testing according to some embodiments of the present disclosure;

FIG10 shows a schematic block diagram of an apparatus for scan testing according to some embodiments of the present disclosure; and

FIG. 11 illustrates a block diagram of a computing device capable of implementing various embodiments of the present disclosure.

DETAILED DESCRIPTION

Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although certain embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be construed as being limited to the embodiments described herein, which are instead provided for a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are only for exemplary purposes and are not intended to limit the scope of protection of the present disclosure.

In the description of the embodiments of the present disclosure, the term "including" and similar terms should be understood as open inclusion, that is, "including but not limited to". The term "based on" should be understood as "based at least in part on". The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The terms "first", "second", etc. may refer to different or the same objects. Other explicit and implicit definitions may also be included below.

It should be understood that in the technical solutions provided by the embodiments of the present application, some repetitions may not be repeated in the introduction of the following specific embodiments, but these specific embodiments should be regarded as having been referenced to each other and can be combined with each other.

As briefly described above, in the process of chip testing using EDA tools or software, a test circuit can be constructed to test the circuit to be tested in the same chip. The test circuit can include a testability design such as a scan chain. The scan chain includes a plurality of "shift registers (also called scan cells)" connected by triggers in a sequential circuit, and the input and output of each shift register can be observed separately. Using the scan chain, the test of a complex sequential circuit can be converted into a test of a combinational circuit.

Specifically, each scanning unit may include a data input port D, a shift input port SI, a shift enable input port SE and one output port Q. Except for the scanning units at the head and tail of the scan chain, each scanning unit may be connected to the output port Q of the previous scanning unit through its shift input port SI. Based on the control of the shift enable (SE) signal, the scanning unit may have a shift mode and a capture mode.

In shift mode, whenever the clock signal (clk) jumps, the test vector is input from the shift input port SI of the scan unit and shifted on the scan chain through the first connected scan unit. The output port Q of the scan unit drives the combinational logic in the circuit under test, and the combinational logic outputs the corresponding value through the data input port D of the scan unit connected to it.

When the test vector shift is completed, each scan unit can enter the capture mode. In the capture mode, each time the clock signal jumps, the scan unit will capture the value of the current data input port D. After that, each scan unit enters the shift mode again. In the shift mode, these captured values are shifted out from the output port of the scan chain one by one for comparison with the preset correct value. If the combinational logic has a fault and is stimulated by the current test vector, the fault can be detected by the difference between the shifted value and the correct value.

However, in this scan test scheme, it is necessary to capture the value in the combinational logic after the test vector is completely shifted into the scan chain, and the captured value needs to be shifted out of the scan chain one by one for comparison with the correct value. Considering that the shift process takes much longer than the capture process, most of the chip test time is spent in the shift process, making the test efficiency low. For example, if it takes N cycles (N is greater than or equal to the maximum chain length) to shift the test vector into the entire scan chain, and a single capture scan test that only takes one cycle is performed, the fault test time only accounts for about 1/N of the total test time. Therefore, the traditional scan test scheme has a long test time and low test efficiency.

In order to at least partially solve the above problems and other potential problems, various embodiments of the present disclosure provide a scheme for scan testing. According to various embodiments described herein, a circuit system for scan testing is provided. The circuit system includes a first scan unit and an observation unit connected in series with the first scan unit in a scan chain. The first scan unit is configured to generate a first shift value based on at least a portion of a test vector. The observation unit includes a signal combiner and a second scan unit. The signal combiner is configured to generate a first combined value at a first output of the signal combiner based on a combination of a value at an observation point in the circuit to be tested and the first shift value output by the first scan unit in a shift capture mode. The second scan unit is configured to generate a scan observation value based on the first combined value in the shift capture mode.

By using the solution of the present disclosure, the scan chain can be configured to operate in a shift capture mode. Specifically, in the shift capture mode, the observation unit can obtain a combination of a value at an observation point in the circuit under test and an output value of the first scanning unit during a shift cycle. In this way, it is possible to determine whether there is a fault in the circuit under test by observing the value at the observation point in the circuit under test during the shift process, thereby improving the efficiency of chip testing.

Various exemplary embodiments of the present disclosure are described below with reference to the accompanying drawings.

FIG. 1 shows a flow chart of a chip design and manufacturing process 100. The design and manufacturing process 100 begins with specification formulation 110. At the stage of specification formulation 110, the requirements for the functions and performances that the integrated circuit needs to achieve are determined. At the stage of chip design 120, circuit design is performed with the aid of EDA software to obtain, for example, a layout file for chip manufacturing. Based on the difference in circuits (e.g., digital circuits or analog circuits), the design 120 may include different design links. At the stage of manufacturing 140, integrated circuits are formed on wafers through processes such as photolithography, etching, ion implantation, thin film deposition, and polishing. At the stage of packaging 150, the wafer is cut to obtain a bare die, and the bare die is packaged to obtain a chip through processes such as pasting, welding, and mold sealing. The obtained chip is tested at the stage of testing 160 to ensure that the performance of the finished chip meets the requirements determined in the specification formulation 110. The chip 170 that passes the test can be delivered to the customer. It can be understood that the above process is only illustrative and does not limit the scope of the present disclosure. In some cases, the design and manufacturing process of the chip may be different. For example, tape-out may be performed before manufacturing 140. A small number of chips obtained from the tape-out may be used for testing to verify whether the chip design meets expectations. If it does not meet expectations, this indicates that the tape-out has failed and the chip design may need to be adjusted or redesigned.

In some embodiments, the design 120 of the digital circuit may exemplarily include an architecture design 121, an RTL design 123, a functional simulation 125, a synthesis 127, a timing analysis 129, a DFT 131, a verification check 133, a layout 135, a design rule check (DRC) 137, and a layout generation 139. The architecture design 121 includes, for example, designing the architecture of the chip. For example, EDA software may be used to determine the categories and quantities of components or subcircuits included in the chip system, as well as the functions, connections, and interactions of each component or subcircuit. In the stage of RTL design 123, a hardware programming language such as Verilog or VHDL may be used to describe the determined chip architecture in code at the RTL level. Functional simulation 125 is also referred to as RTL-level behavioral simulation or front-end simulation. The purpose of functional simulation is to analyze the correctness of the logical relationship of the design circuit. Synthesis 127 may convert RTL into a gate-level netlist. Synthesis 127 may include, for example, translation, optimization, and mapping. In one embodiment, the EDA software used for synthesis may first convert the RTL code into a general Boolean equation and compile it. The netlist may be optimized according to the constraints imposed by the designer, such as delay and area, and then the RTL netlist may be mapped to the process library to generate a gate-level netlist.

Timing analysis 129 is usually static timing analysis, which mainly involves timing calculation and prediction of digital circuits. Timing analysis is performed on the paths in the digital circuit to determine whether timing convergence is achieved, thereby ensuring whether the timing of various circuits meets various timing requirements. The verification of such digital circuits is usually completed statically and does not require simulation of digital logic. At the stage of DFT 131, various hardware logics for improving chip testability (including controllability and observability) can be embedded in the design. By using this part of logic, test vectors can be generated to achieve the purpose of testing large-scale digital circuits. DFT can, for example, include a test method based on a scan chain or a built-in self-test circuit (BIST). At the stage of verification check 133, the circuit can be formally verified and/or equivalence checked. Formal verification can use mathematical methods to prove its correctness or incorrectness based on one or more formal specifications or attributes. Formal verification can, for example, include abstract interpretation, formal model checking (also known as characteristic checking) and theorem prover. Equivalence checking can be used to verify whether the register transfer level design is consistent with the gate-level netlist, and between the gate-level netlist and the gate-level netlist.

In the stage of layout and routing 135, the chip circuit can be laid out (placement) and routed (routing). The layout can reasonably arrange the gate-level netlist generated by logic synthesis 127 in a rectangular area corresponding to the chip based on considerations such as area, critical path delay length, and power consumption. After this, the various components or sub-circuits that have been laid out can be routed to connect them. Routing generally expects the total routing to be short, the routing delay to meet the timing requirements, and to comply with the routing rules in the process (such as routing density). Although layout and routing are described separately here, this is only illustrative and does not limit the scope of the present disclosure. In some cases, layout and routing can be performed simultaneously or alternately to achieve optimization of layout and routing.

At the DRC 137 stage, the layout can be checked for potential open circuits, short circuits or adverse effects caused by violations of design rules. After passing the DRC, a file representing the layout, such as a GDSII file, can be generated 139 by the EDA software. It can be understood that the above steps are only exemplary and not intended to limit the scope of the present disclosure. In the actual design process, the above steps can be added, deleted or modified according to design needs. In addition, some of the above steps can be implemented by different EDA software or integrated in one or more EDA software. The present disclosure does not limit this.

FIG. 2 shows a schematic diagram of an example environment 200 in which various embodiments of the present disclosure can be implemented. As shown in FIG. 2 , in the environment 200, scan chains 201, 202, 203, and 204 can be used to test a circuit under test (not shown). Each scan chain may include a plurality of scan units, such as scan unit 210. In FIG. 2 , a group of scan units connected in series is shown as a rectangle, such as a first group of scan units 211 and a second group of scan units 212. Each scan chain also includes one or more observation units connected in series with the scan unit, such as observation units 220, 221, 222, and 223.

The observation unit includes a signal combiner and a scanning unit, and the output of the signal combiner is connected to the input of the scanning unit. For example, the observation unit 220 includes a signal combiner 231 and a scanning unit 232. The first input of the signal combiner is connected to the output of the previous scanning unit, and the second input of the signal combiner is connected to the observation point in the circuit to be tested. The position of the observation point is usually selected to observe the faults in the circuit to be tested that are difficult to observe through the scanning unit. The faults in the circuit to be tested can be transmitted from the observation point to the signal combiner through the logic cone to detect the faults that are difficult to detect by the scanning unit, thereby improving the test coverage.

Compared with the ordinary scanning unit (scanning unit in the non-observation unit) in the scan chain, the output of the scanning unit in the observation unit may not drive the circuit to be tested during the shift process. In other words, the scan chain according to the embodiment of the present disclosure includes two types of scanning units. In some embodiments, the output of the ordinary scanning unit during the shift process drives the circuit to be tested, while the output of the scanning unit in the observation unit during the shift process does not drive the circuit to be tested. Alternatively, the output of the scanning unit in the observation unit during the shift process may also drive the circuit to be tested.

As shown in FIG2 , the observation unit can be located at the beginning, the middle or the end of the chain in the scan chain. For example, the observation unit 220 and the observation unit 221 are located at the middle of the scan chain 201. The observation unit 223 is located at the end of the scan chain 205. The observation unit 224 is located at the beginning of the scan chain 203. In this way, the observation unit can be flexibly arranged in the scan chain so that the position of the observation unit is close to the position of the observation point and/or the position of the observation unit is close to other scanning units in the scan chain, thereby reducing the difficulty of wiring. In other words, the observation unit can be arranged so that the sum of the connection distance between the observation point and the connection distance between the adjacent scanning units is less than a predetermined threshold.

In some embodiments, the scan chain may further include a clock gating device (not shown), wherein a first input of the clock gating device is connected to a clock signal, a second input of the clock gating device is connected to a clock gating signal for controlling whether the scan chain receives the clock signal, and an output of the clock gating device is connected to clock input ports of a plurality of scan units in the scan chain.

It should be understood that the environment 200 shown in Figure 2 is merely exemplary and does not constitute a limitation on the scope of the present disclosure. For example, the number of scan chains may be any suitable value, and the number of observation units in each scan chain may be any suitable value.

FIG3 shows a schematic diagram of an observation unit 300 according to some embodiments of the present disclosure. The observation unit 300 may be a specific implementation of the observation units 220, 221, 222, 223, and 224. As shown in FIG3, the observation unit 300 may include a signal combiner 310 and a scan unit 320. The first input of the signal combiner 310 may be connected to an observation point in the circuit to be tested, and the second input may be connected to the last timing gate shifted by the scan chain or the test vector initially shifted in. The first output and the second output of the signal combiner 310 are respectively connected to the corresponding inputs of the scan unit 320. The scan unit 320 may include a D terminal associated with the value at the observation point, an SI terminal associated with the output of the previous scan unit or the test vector shifted in, an SE terminal associated with the enable signal of the shift capture mode, and a Q terminal.

The observation unit 300 is configured to operate in a (traditional) shift mode, a (traditional) capture mode, a shift capture mode, and a circuit operation mode. In the shift capture mode, the signal combiner 310 is configured to generate a first combined value at the first output (the output corresponding to the SI terminal) of the signal combiner 310 based on the value at the observation point in the circuit to be tested and the combination of the first shift value output by a previous scan unit or the value of the test vector shifted in. The scan unit 320 is configured to generate a scanned observation value based on the first combined value to be output from the Q terminal. By shifting the scanned observation value out of the scan chain and comparing it with the preset correct value, it is possible to detect whether there is a fault in the circuit to be tested.

In other words, the observation unit 300 can generate a scan observation value based on a combination of a shift value shifted out by a previous scan unit (which can be a common scan unit or a scan unit in another observation unit) (corresponding to the case where the observation unit is in the middle or tail position of the scan chain) or the value of the test vector initially shifted in (corresponding to the case where the observation unit is at the head position of the scan chain) and the value captured at the observation point. In this way, the value of a previous scan unit in the scan chain or the value of the test vector initially shifted in can be shifted in the shift cycle, and the value at the observation point in the circuit to be tested can be obtained at the same time, so as to realize the function of observing circuit faults during shifting.

When the observation unit 300 is in the middle or tail position of the scan chain, in the shift mode, the signal combiner 310 is configured to generate a second combination value at the first output (the output corresponding to the SI terminal) of the signal combiner 310 based on the first shift value output by the previous scan unit. The scan unit 320 is configured to generate a second shift value based on the second combination value, and the second shift value is the same as the first shift value output by the previous scan unit.

In the capture mode, the signal combiner 310 is configured to generate a third combined value at the second output (the output corresponding to the D terminal) of the signal combiner based on the value at the observation point or the combination of the value at the observation point and the first shift value. The scanning unit 320 is configured to generate a capture value identical to the third combined value based on the third combined value.

When the observation unit 300 is at the head position of the scan chain, in the shift mode, the signal combiner 310 is configured to generate a second combination value at the first output (the output corresponding to the SI terminal) of the signal combiner 310 based on at least a portion of the test vector. The scanning unit 320 is configured to generate a second shift value based on the second combination value, and the second shift value is the same as at least a portion of the test vector. In addition, the ordinary scanning unit connected after the observation unit 300 can generate a shift value that is the same as the second shift value based on the second shift value.

In the capture mode, the signal combiner 310 is configured to generate a third combination value at the second output (the output corresponding to the D terminal) of the signal combiner based on the value at the observation point or the combination of the value at the observation point and the value at the functional logic connection point in the circuit under test. The scanning unit 320 is configured to generate a capture value that is the same as the third combination value based on the third combination value. In addition, the ordinary scanning unit connected after the observation unit 300 can generate at least a part of the test response based on the value at the functional logic connection point in the circuit under test corresponding to the ordinary scanning unit.

The details of the operation of the observation unit 300 in the above-mentioned respective modes will be described below with reference to FIGS. 4 to 6 .

FIG4 shows a schematic diagram of a first example of an observation unit 400 according to some embodiments of the present disclosure. The observation unit 400 may be a specific example of the observation unit 300. As shown in FIG4 , the signal combiner in the observation unit 400 may include an AND gate 401 and an XOR gate 402. The observation unit 400 may also include a scanning unit 450. In an embodiment of the present disclosure, unlike a common scanning unit, the output of the scanning unit in the observation unit 400 does not drive the circuit under test during the shifting process.

The observation unit 400 may include a plurality of input ports and an output port. As shown in the figure, the observation unit 400 may include a shift capture enable port en for receiving an enable signal of a shift capture mode, an observation input port od for receiving a value at an observation point, a shift input port si for receiving a previous timing gate shifted by a scan chain or a test vector initially shifted in, a shift enable port se for receiving a shift enable signal, and a clock input port clk for receiving a clock signal. The observation unit 400 may also include a reset port rn for receiving a trigger reset signal and an output port q for output. The output of the observation unit 400 may be input to the next timing gate in the scan chain, such as the next scan unit or observation unit connected in series with the observation unit 400. If the observation unit 400 is located at the end of the chain, the output of the observation unit 400 may be shifted out through the main output port.

Table 1 shows information of ports of the observation unit 400 .

Table 1:

port direction effect en enter Receive shift capture mode enable signal od enter The value at the observation point in the receiving circuit si enter Receives the last sequential gate shifted by the scan chain or the test vector initially shifted in s enter Receive shift enable signal clk enter Receive clock signal rn enter Receive trigger reset signal q Output Output the value of the observation unit

As shown in FIG4 , the AND gate 401 is configured to receive the enable signal of the shift capture mode and the value at the observation point, and generate a value corresponding to the SI terminal of the scan unit 450. The XOR gate 402 is configured to generate a value corresponding to the SI terminal of the scan unit 450 based on the output of the AND gate 401 and the last timing gate shifted by the scan chain (for example, the first shift value shifted out of the previous scan unit) or the test vector initially shifted in. By controlling the signals at the en port and the se port, the observation unit 400 can be operated in the corresponding working mode. Table 2 shows the working mode of the observation unit 400.

Table 2:

When the input signals of the en terminal and the se terminal are both set to 1, the shift capture mode is turned on. In the shift capture mode, in the shift cycle, the observation unit 400 receives the value of the previous clock gate on the scan chain (for example, the shift value of the output of the previous scan unit) and captures the value at the observation point, so as to observe the circuit in the shift cycle, so that the fault that can only be captured in the capture process can also be captured in the shift cycle, thereby greatly improving the test efficiency.

FIG5 shows a schematic diagram of a second example of an observation unit 500 according to some embodiments of the present disclosure. The observation unit 500 may be a specific example of the observation unit 300. As shown in FIG5 , the signal combiner in the observation unit 500 may include an AND gate 501, an XOR gate 502, and an XOR gate 503. The observation unit 500 further includes a scanning unit 550.

Similar to the observation unit 400, the observation unit 500 may include a plurality of input ports and an output port. As shown in the figure, the observation unit 500 may include a shift capture enable port en, an observation input port od, a shift input port si, a shift enable port se, a clock input port clk, a reset port rn, and an output port q. The observation unit 500 also includes a test data input port fd for receiving the value at the functional logic connection point corresponding to the scan unit 550 contained in the circuit under test.

Table 3 shows information of the ports of the observation unit 500 .

Table 3:

port direction effect fd enter Receive the value at the function logic connection point corresponding to the scan unit en enter Receive shift capture mode enable signal od enter The value at the observation point in the receiving circuit si enter Receives the last sequential gate shifted by the scan chain or the test vector initially shifted in s enter Receive shift enable signal clk enter Receive clock signal rn enter Receive trigger reset signal q Output Output the value of the observation unit

As shown in Figure 5, AND gate 501 is configured to receive an enable signal of the shift capture mode and a value at an observation point. XOR gate 502 is configured to generate a value corresponding to the SI end of scan unit 550 based on the output of AND gate 501 and the last timing gate shifted by the scan chain (for example, the first shift value shifted out of the previous scan unit) or the test vector initially shifted in. XOR gate 503 is configured to generate a value corresponding to the D end of scan unit 550 based on the output of AND gate 501 and the value at the functional logic connection point in the circuit to be tested. By controlling the signals at the en port and the se port, the observation unit 500 can be operated in the corresponding working mode. Table 4 shows the working mode of the observation unit 500.

Table 4:

Compared with observation unit 400, observation unit 500 can reuse the existing scanning units in the circuit, allowing these existing scanning units to execute traditional capture mode and shift capture mode at the same time without affecting the functions of the scanning units in normal operation, thereby saving hardware costs and reducing area overhead.

Figure 6 shows a schematic diagram of control signals and clock signals in a scan test according to some embodiments of the present disclosure. Figure 6 shows the changes of the clock signal clk1 of the normal scan unit, the shift enable signal se, the enable signal en (at a high level) of the shift capture mode, and the clock signal clk2 of the observation unit.

As shown in FIG6 , in the shift cycle, the control signals en and se are both high level, and the scan chain operates in the shift capture mode. Specifically, the normal scan unit shifts in the test vector or the value of the previous timing gate, and outputs the value to drive the circuit to be tested. The observation unit captures the value at the observation point while shifting, and outputs the value to the next timing gate or the main output port. In the shift capture mode, the observation unit in the current clock cycle outputs a value based on the shift value output by the previous scan unit in the previous clock cycle (corresponding to the case where the observation unit is in the middle or end of the scan chain) or the value of the test vector initially shifted in (corresponding to the case where the observation unit is at the beginning of the scan chain) and the value at the observation point captured in the current clock cycle.

In the capture cycle, the control signal en is kept at a high level and the se signal is set to a low level, and the scan chain operates in the capture mode. Specifically, the ordinary scan unit obtains the test response from the circuit to be tested, and the observation unit also enters the traditional capture working mode to capture the value from the observation point of the circuit to be tested. In some embodiments, when the observation unit 400 is used, in the capture mode, the observation unit outputs a value in the current clock cycle based on the value at the observation point captured in the current clock cycle. Alternatively, when the observation unit 500 is used, the observation unit outputs a value in the current clock cycle based on the combination (e.g., XOR) of the value at the observation point captured in the current clock cycle and the value at the functional logic connection point.

Although not shown, when the control signal en is set to a low level, the scan chain can operate in a conventional shift mode and a capture mode, that is, a test vector is shifted in (or a test response is shifted out) or the value of a previous timing gate in a shift cycle, and a test response is captured from the circuit under test in the capture mode. Specifically, in the shift mode, the observation unit in the current clock cycle outputs a value based on a shift value output by a previous scan unit in a previous clock cycle or the value of the test vector initially shifted in.

FIG. 7 shows a schematic diagram of a circuit system 700 for scan testing according to some embodiments of the present disclosure. As shown in FIG. 7 , the circuit system 700 includes a plurality of scan chains, and the observation unit in each scan chain is arranged at the tail position of the chain. When the observation unit is at the tail position of the chain, the output value of the ordinary scan unit at the end of each scan chain will be XORed into the scan unit in the observation unit after each shift cycle and the value at the observation point in the circuit to be tested, and finally moved out of the scan chain for observation. In this way, there is no scan unit behind the observation unit that will drive the native circuit logic, thereby reducing the impact on the simulation time. In addition, compared with the case where the observation unit is at the head or middle position of the chain, since there is no ordinary scan unit behind the observation unit that will drive the native logic of the circuit, there is no need to consider the change of the test vector after passing through the observation unit, thereby reducing the difficulty of testing.

FIG8 shows a schematic diagram of a circuit system for scan testing using test compression technology according to some embodiments of the present disclosure. As shown in FIG8 , multiple scan chains in a scan system can utilize test compression technology. The test vectors input from a few ports can be expanded to a width equal to the number of scan chains by decompression by a decompressor 810 so as to be simultaneously input into each scan chain. In addition, the test response output from the scan chain can be compressed into an output value of a few port widths by a compressor 820, thereby reducing the number of test vector input and output ports required for testing.

Fig. 9 is a schematic block diagram of an example process of a method 900 for scan testing according to some embodiments of the present disclosure. The method 900 may be executed by any suitable processor, such as a processor implementing EDA software functions.

In block 910, a test vector is shifted into a scan chain in a shift capture mode. In block 920, a scan observation value is generated in the shift capture mode based on at least a portion of the test vector and a value at an observation point in the circuit to be tested. The scan chain is configured to include: a first scan unit configured to generate a first shift value based on the at least a portion of the test vector; and an observation unit connected in series with the first scan unit, and the observation unit includes: a signal combiner configured to generate a first combination value in the shift capture mode based on a combination of the value at the observation point and the first shift value output by the first scan unit; and a second scan unit configured to generate the scan observation value in the shift capture mode based on the first combination value.

In some embodiments, method 900 also includes shifting the test vector into the scan chain in a shift mode, wherein: the signal combiner is further configured to generate a second combination value at the first output of the signal combiner based on the first shift value output by the first scan unit in the shift mode; and the second scan unit is further configured to generate a second shift value based on the second combination value in the shift mode, and the second shift value is the same as the first shift value output by the first scan unit.

In some embodiments, method 900 also includes obtaining a capture value in a capture mode, wherein: the signal combiner is further configured to generate a third combination value at a second output of the signal combiner in the capture mode based on the value at the observation point or a combination of the value at the observation point and the value at a functional logic connection point in the circuit under test; and the second scanning unit is further configured to generate the capture value that is the same as the third combination value in the capture mode based on the third combination value.

In some embodiments, the signal combiner includes: an AND gate configured to receive an enable signal of the shift capture mode and the value at the observation point; and a first XOR gate configured to generate a value at the first output of the signal combiner based on an output of the AND gate and the first shift value.

In some embodiments, the signal combiner further comprises a second XOR gate configured to generate a value at a second output of the signal combiner based on an output of the AND gate and a value at a functional logic connection point in the circuit under test.

In some embodiments, the observation unit is located in the middle or at the end of the scan chain.

In some embodiments, a sum of a line distance between the observation unit and the observation point and a line distance between the observation unit and the first scanning unit is less than a predetermined threshold.

Although not shown, an embodiment of the present disclosure also provides a method for scan testing. The method includes: shifting a test vector into a scan chain in a shift capture mode; and generating a scan observation value based on at least a portion of the test vector and a value at an observation point in the circuit to be tested in the shift capture mode, wherein the scan chain is configured to include: a first scan unit configured to generate a first shift value based on at least a portion of the test vector; and an observation unit connected in series with the first scan unit, and the observation unit includes: a signal combiner configured to generate a first combination value based on a combination of the value at the observation point and the first shift value output by the first scan unit in the shift capture mode; and a second scan unit configured to generate the scan observation value based on the first combination value in the shift capture mode.

In some embodiments, the method also includes shifting the test vector into the scan chain in a shift mode, wherein: the signal combiner is further configured to generate a second combination value at the first output of the signal combiner based on the at least a portion of the test vector in the shift mode; the second scan unit is further configured to generate a second shift value based on the second combination value in the shift mode, the second shift value being the same as the at least a portion of the test vector; and the first scan unit is further configured to generate a third shift value based on the second shift value in the shift mode, the third shift value being the same as the second shift value.

In some embodiments, the method also includes obtaining a captured value in a capture mode, wherein: the signal combiner is further configured to generate a third combined value at a second output of the signal combiner in the capture mode based on the value at the observation point or a combination of the value at the observation point and the value at a first functional logic connection point in the circuit under test; the second scanning unit is further configured to generate the captured value identical to the third combined value in the capture mode based on the third combined value; and the first scanning unit is further configured to generate at least a part of a test response in the capture mode based on the value at a second functional logic connection point in the circuit under test.

In some embodiments, the signal combiner includes: an AND gate configured to receive an enable signal of the shift capture mode and a value at the observation point; and a first XOR gate configured to generate a value at the first output of the signal combiner based on an output of the AND gate and at least a portion of the test vector.

In some embodiments, the signal combiner further comprises a second XOR gate configured to generate a value at a second output of the signal combiner based on an output of the AND gate and a value at a functional logic connection point in the circuit under test.

In some embodiments, the observation unit is located at the head of the scan chain.

Example devices and equipment

FIG10 shows a block diagram of an apparatus 1000 for scan testing according to an embodiment of the present disclosure. Specifically, the apparatus 1000 may be an EDA software apparatus. The apparatus 1000 may include a plurality of modules for performing corresponding steps in the process 900 as discussed in FIG9 . As shown in FIG10 , the apparatus 1000 includes a shift unit 1010 configured to shift a test vector into a scan chain in a shift capture mode. The apparatus 1000 also includes a capture unit 1020 configured to generate a scan observation value based on at least a portion of the test vector and a value at an observation point in the circuit under test in the shift capture mode. The scan chain is configured to include: a first scan unit, configured to generate a first shift value based on at least a portion of the test vector; and an observation unit, connected in series with the first scan unit, and the observation unit includes: a signal combiner, configured to generate a first combination value based on a combination of a value at the observation point and the first shift value output by the first scan unit in the shift capture mode; and a second scan unit, configured to generate the scan observation value based on the first combination value in the shift capture mode.

In some embodiments, the signal combiner is further configured to generate a second combination value at the first output of the signal combiner based on the first shift value output by the first scanning unit in a shift mode; and the second scanning unit is further configured to generate a second shift value based on the second combination value in the shift mode, and the second shift value is the same as the first shift value output by the first scanning unit.

In some embodiments, the signal combiner is further configured to generate a third combined value at the second output of the signal combiner in a capture mode based on the value at the observation point or a combination of the value at the observation point and the first shift value; and the second scanning unit is further configured to generate a capture value identical to the third combined value in the capture mode based on the third combined value.

In some embodiments, the signal combiner includes: an AND gate configured to receive an enable signal of the shift capture mode and the value at the observation point; and a first XOR gate configured to generate a value at the first output of the signal combiner based on an output of the AND gate and the first shift value.

In some embodiments, the signal combiner further comprises a second XOR gate configured to generate a value at a second output of the signal combiner based on an output of the AND gate and a value at a functional logic connection point in the circuit under test.

In some embodiments, in the shift mode, the observation unit in a current clock cycle outputs a value based on the first shift value output by the first scanning unit in a previous clock cycle.

In some embodiments, in the shift capture mode, the observation unit in the current clock cycle outputs a value based on an exclusive OR of the first shift value output by the first scan unit in a previous clock cycle and the value at the observation point captured in the current clock cycle.

In some embodiments, in the capture mode, the observation unit in a current clock cycle outputs a value based on a value at the observation point captured in the current clock cycle.

In some embodiments, in the capture mode, the observation unit in a current clock cycle outputs a value based on an exclusive OR of a value at the observation point captured in the current clock cycle and a value at the functional logic connection point.

In some embodiments, the observation unit is located in the middle or at the end of the scan chain.

In some embodiments, circuitry for testing a circuit includes a plurality of scan chains including the scan chain, wherein the plurality of scan chains are in a compressed scan mode or a non-compressed scan mode.

In some embodiments, a sum of a line distance between the observation unit and the observation point and a line distance between the observation unit and the first scanning unit is less than a predetermined threshold.

Although not shown, an embodiment of the present disclosure also provides a device for scan testing. The device includes: a shift unit configured to shift a test vector into a scan chain in a shift capture mode; and a capture unit configured to generate a scan observation value based on at least a portion of the test vector and a value at an observation point in a circuit to be tested in the shift capture mode, wherein the scan chain is configured to include: a first scan unit; and an observation unit connected in series with the first scan unit in the scan chain, and the observation unit includes: a signal combiner configured to generate a first combination value at a first output of the signal combiner based on a combination of the value at the observation point in the circuit to be tested and the at least a portion of the test vector in the shift capture mode; and a second scan unit configured to generate the scan observation value based on the first combination value in the shift capture mode; and wherein the first scan unit is configured to generate a first shift value based on the scan observation value in the shift capture mode.

In some embodiments, the signal combiner is further configured to generate a second combined value at the first output of the signal combiner based on at least a portion of the test vector in a shift mode; the second scanning unit is further configured to generate a second shift value based on the second combined value in the shift mode, the second shift value being the same as the at least a portion of the test vector; and the first scanning unit is further configured to generate a third shift value based on the second shift value in the shift mode, the third shift value being the same as the second shift value.

In some embodiments, the signal combiner is further configured to generate a third combined value at a second output of the signal combiner in a capture mode based on the value at the observation point or a combination of the value at the observation point and the value at a first functional logic connection point in the circuit under test; the second scanning unit is further configured to generate a captured value identical to the third combined value in the capture mode based on the third combined value; and the first scanning unit is further configured to generate at least a portion of a test response in the capture mode based on the value at a second functional logic connection point in the circuit under test.

In some embodiments, the signal combiner includes: an AND gate configured to receive an enable signal of the shift capture mode and a value at the observation point; and a first XOR gate configured to generate a value at the first output of the signal combiner based on an output of the AND gate and at least a portion of the test vector.

In some embodiments, the signal combiner further comprises a second XOR gate configured to generate a value at a second output of the signal combiner based on an output of the AND gate and a value at a functional logic connection point in the circuit under test.

In some embodiments, the observation unit is located at the head of the scan chain.

FIG. 11 shows a schematic block diagram of an example device 1100 that can be used to implement an embodiment of the present disclosure. As shown, the device 1100 includes a computing unit 1101, which can perform various appropriate actions and processes according to computer program instructions stored in a random access memory (RAM) 1103 and/or a read-only memory (ROM) 1102 or computer program instructions loaded from a storage unit 1108 into the RAM 1103 and/or the ROM 1102. In the RAM 1103 and/or the ROM 1102, various programs and data required for the operation of the device 1100 can also be stored. The computing unit 1101 and the RAM 1103 and/or the ROM 1102 are connected to each other via a bus 1104. An input/output (I/O) interface 1105 is also connected to the bus 1104.

A number of components in the device 1100 are connected to the I/O interface 1105, including: an input unit 1106, such as a keyboard, a mouse, etc.; an output unit 1107, such as various types of displays, speakers, etc.; a storage unit 1108, such as a disk, an optical disk, etc.; and a communication unit 1109, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 1109 allows the device 1100 to exchange information/data with other devices through a computer network such as the Internet and/or various telecommunication networks.

The computing unit 1101 may be a variety of general and/or special processing components with processing and computing capabilities. Some examples of the computing unit 1101 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, digital signal processors (DSPs), and any appropriate processors, controllers, microcontrollers, etc. The computing unit 1101 performs the various methods and processes described above, such as process 900. For example, in some embodiments, the process 900 may be implemented as a computer software program, specifically an EDA program, which is tangibly contained in a machine-readable medium, such as a storage unit 1108. In some embodiments, part or all of the computer program may be loaded and/or installed on the device 1100 via RAM and/or ROM and/or communication unit 1109. When the computer program is loaded into RAM and/or ROM and executed by the computing unit 1101, one or more steps of the process 900 described above may be performed. Alternatively, in other embodiments, the computing unit 1101 may be configured to perform the process 900 in any other appropriate manner (eg, by means of firmware).

In the above embodiments, the method flow can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented by software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a server or terminal, the process or function described in the embodiment of the present application is generated in whole or in part. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website site, computer, server or data center to another website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that can be accessed by a server or terminal or a data storage device such as a server or data center that includes one or more available media integrated. The available medium can be a magnetic medium (such as a floppy disk, a hard disk and a tape, etc.), an optical medium (such as a digital video disk (digital video disk, DVD), etc.), or a semiconductor medium (such as a solid state drive, etc.).

In addition, although each operation is described in a specific order, this should be understood as requiring such operation to be performed in the specific order shown or in a sequential order, or requiring that all illustrated operations should be performed to obtain desired results. Under certain circumstances, multitasking and parallel processing may be advantageous. Similarly, although some specific implementation details are included in the above discussion, these should not be interpreted as limiting the scope of the present disclosure. Some features described in the context of a separate embodiment can also be implemented in a single implementation in combination. On the contrary, the various features described in the context of a single implementation can also be implemented in multiple implementations individually or in any suitable sub-combination mode.

Although the subject matter has been described in language specific to structural features and/or methodological logical actions, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described above. On the contrary, the specific features and actions described above are merely example forms of implementing the claims.

Claims (25)

1. Circuitry for scan testing, comprising:

a first scanning unit configured to generate a first shift value based on at least a portion of the test vector; and

An observation unit connected in series with the first scanning unit in a scan chain, and comprising:

A signal combiner configured to generate, in a shift capture mode, a first combined value at a first output of the signal combiner based on a combination of a value at an observation point in a circuit under test and the first shift value output by the first scanning unit; and

A second scanning unit configured to generate a scanning observation based on the first combined value in the shift capture mode.

2. The circuitry of claim 1, wherein:

the signal combiner is further configured to generate, in a shift mode, a second combined value at the first output of the signal combiner based on the first shift value of the first scan cell output; and

The second scanning unit is further configured to generate, in the shift mode, a second shift value based on the second combined value, the second shift value being the same as the first shift value output by the first scanning unit.

3. The circuitry of claim 1 or 2, wherein:

The signal combiner is further configured to generate, in a capture mode, a third combined value at a second output of the signal combiner based on a combination of the value at the observation point or the value at the observation point and a value at a functional logic connection point in the circuit under test; and

The second scanning unit is further configured to generate, in the capture mode, a capture value that is the same as the third combined value based on the third combined value.

4. A circuit system according to any one of claims 1 to 3, wherein the signal combiner comprises:

an and gate configured to receive an enable signal of the shift capture mode and a value at the observation point; and

A first exclusive-or gate configured to generate a value at the first output of the signal combiner based on an output of the and gate and the first shift value.

5. The circuitry of claim 4, wherein the signal combiner further comprises a second exclusive-or gate configured to generate a value at a second output of the signal combiner based on the output of the and gate and a value at a functional logic connection point in the circuit under test.

6. The circuitry of any of claims 1 to 5, wherein the observation unit is at a position in a chain or a chain tail of the scan chain.

7. The circuitry of any of claims 1-6, comprising a plurality of scan chains including the scan chain, wherein the plurality of scan chains are in a compressed scan mode or a non-compressed scan mode.

8. The circuitry of any of claims 1 to 7, wherein a sum of a link distance between the observation unit and the observation point and a link distance between the observation unit and the first scanning unit is less than a predetermined threshold.

9. Circuitry for scan testing, comprising:

A first scanning unit; and

An observation unit connected in series with the first scanning unit in a scan chain, and comprising:

A signal combiner configured to generate, in a shift capture mode, a first combined value at a first output of the signal combiner based on a combination of a value at an observation point in a circuit under test and at least a portion of a test vector; and

A second scanning unit configured to generate a scanning observation value based on the first combined value in the shift capture mode; and

Wherein the first scanning unit is configured to generate a first shift value based on the scan observations in the shift capture mode.

10. The circuitry of claim 9, wherein:

the signal combiner is further configured to generate, in a shift mode, a second combined value at the first output of the signal combiner based on the at least a portion of the test vector;

the second scanning unit is further configured to generate, in the shift mode, a second shift value based on the second combined value, the second shift value being the same as the at least a portion of the test vector; and

The first scanning unit is further configured to generate, in the shift mode, a third shift value based on the second shift value, the third shift value being the same as the second shift value.

11. The circuitry of claim 9 or 10, wherein:

The signal combiner is further configured to generate, in a capture mode, a third combined value at a second output of the signal combiner based on a combination of the value at the observation point or the value at the observation point and the value at a first functional logic connection point in the circuit under test;

the second scanning unit is further configured to generate, in the capture mode, a capture value that is the same as the third combined value based on the third combined value; and

The first scan cell is further configured to generate at least a portion of a test response based on a value at a second functional logic connection point in the circuit under test in the capture mode.

12. The circuitry of any of claims 9 to 11, wherein the signal combiner comprises:

an and gate configured to receive an enable signal of the shift capture mode and a value at the observation point; and

A first exclusive-or gate configured to generate a value at the first output of the signal combiner based on the output of the and gate and the at least a portion of the test vector.

13. The circuitry of claim 12, wherein the signal combiner further comprises a second exclusive-or gate configured to generate a value at a second output of the signal combiner based on the output of the and gate and a value at a functional logic connection point in the circuit under test.

14. The circuitry of any of claims 9 to 13, wherein the observation unit is in a chain head position of the scan chain.

15. A method for testing a circuit under test, comprising:

shifting test vectors into the scan chain in a shift capture mode; and

Generating a scan observation in the shift capture mode based on at least a portion of the test vector and a value at an observation point in the circuit under test, wherein the scan chain is configured to include:

A first scanning unit configured to generate a first shift value based on the at least a portion of the test vector; and

An observation unit connected in series with the first scanning unit, and comprising:

a signal combiner configured to generate a first combined value based on a combination of a value at the observation point and the first shift value output by the first scanning unit in the shift capture mode; and

A second scanning unit configured to generate the scanning observation based on the first combined value in the shift capture mode.

16. The method of claim 15, further comprising shifting the test vector into the scan chain in a shift mode, wherein:

The signal combiner is further configured to generate, in the shift mode, a second combined value at the first output of the signal combiner based on the first shift value output by the first scan cell; and

The second scanning unit is further configured to generate, in the shift mode, a second shift value based on the second combined value, the second shift value being the same as the first shift value output by the first scanning unit.

17. The method of claim 15 or 16, further comprising acquiring a capture value in a capture mode, wherein:

The signal combiner is further configured to generate, in the capture mode, a third combined value at a second output of the signal combiner based on a combination of the value at the observation point or the value at the observation point and a value at a functional logic connection point in the circuit under test; and

The second scanning unit is further configured to generate, in the capture mode, the capture value that is the same as the third combined value based on the third combined value.

18. A method for testing a circuit under test, comprising:

shifting test vectors into the scan chain in a shift capture mode; and

Generating a scan observation in the shift capture mode based on at least a portion of the test vector and a value at an observation point in the circuit under test, wherein the scan chain is configured to include:

A first scanning unit; and

An observation unit connected in series with the first scanning unit in the scan chain, and comprising:

A signal combiner configured to generate, in the shift capture mode, a first combined value at a first output of the signal combiner based on a combination of a value at the observation point in the circuit under test and the at least a portion of the test vector; and

A second scanning unit configured to generate the scanning observation based on the first combined value in the shift capture mode; and

Wherein the first scanning unit is configured to generate a first shift value based on the scan observations in the shift capture mode.

19. The method of claim 18, further comprising shifting the test vector into the scan chain in a shift mode, wherein:

The signal combiner is further configured to generate, in the shift mode, a second combined value at the first output of the signal combiner based on the at least a portion of the test vector;

the second scanning unit is further configured to generate, in the shift mode, a second shift value based on the second combined value, the second shift value being the same as the at least a portion of the test vector; and

The first scanning unit is further configured to generate, in the shift mode, a third shift value based on the second shift value, the third shift value being the same as the second shift value.

20. The method of claim 18 or 19, further comprising acquiring a capture value in a capture mode, wherein:

The signal combiner is further configured to generate, in the capture mode, a third combined value at a second output of the signal combiner based on a combination of the value at the observation point or the value at the observation point and the value at a first functional logic connection point in the circuit under test;

the second scanning unit is further configured to generate, in the capture mode, the capture value that is the same as the third combined value based on the third combined value; and

The first scan cell is further configured to generate at least a portion of a test response based on a value at a second functional logic connection point in the circuit under test in the capture mode.

21. An apparatus, comprising:

A shift unit configured to shift a test vector into the scan chain in a shift capture mode; and

A capture unit configured to generate a scan observation based on values at an observation point in a circuit under test and at least a portion of the test vector in the shift capture mode, wherein the scan chain is configured to include:

A first scanning unit configured to generate a first shift value based on the at least a portion of the test vector; and

An observation unit connected in series with the first scanning unit, and comprising:

a signal combiner configured to generate a first combined value based on a combination of a value at the observation point and the first shift value output by the first scanning unit in the shift capture mode; and

A second scanning unit configured to generate the scanning observation based on the first combined value in the shift capture mode.

22. An apparatus, comprising:

A shift unit configured to shift a test vector into the scan chain in a shift capture mode; and

A capture unit configured to generate a scan observation based on values at an observation point in a circuit under test and at least a portion of the test vector in the shift capture mode, wherein the scan chain is configured to include:

A first scanning unit; and

An observation unit connected in series with the first scanning unit in the scan chain, and comprising:

A signal combiner configured to generate, in the shift capture mode, a first combined value at a first output of the signal combiner based on a combination of a value at the observation point in the circuit under test and the at least a portion of the test vector; and

A second scanning unit configured to generate the scanning observation based on the first combined value in the shift capture mode; and

Wherein the first scanning unit is configured to generate a first shift value based on the scan observations in the shift capture mode.

23. An electronic device, comprising:

at least one computing unit;

At least one memory coupled to the at least one computing unit and storing instructions for execution by the at least one computing unit, the instructions when executed by the at least one computing unit, cause the electronic device to perform the method of any one of claims 15-20.

24. A computer readable storage medium having stored thereon a computer program which when executed by a processor implements the method according to any of claims 15-20.

25. A computer program product comprising computer executable instructions which when executed by a processor implement the method of any of claims 15-20.