CN118444129A

CN118444129A - Method and device for testing serial deserializing chip

Info

Publication number: CN118444129A
Application number: CN202410530398.3A
Authority: CN
Inventors: 王宝鹏; 任刚
Original assignee: Shouchuan Microelectronics Changzhou Co ltd
Current assignee: Shouchuan Microelectronics Changzhou Co ltd
Priority date: 2024-04-29
Filing date: 2024-04-29
Publication date: 2024-08-06

Abstract

The invention discloses a serial deserializing chip testing method and a device, wherein the method comprises the following steps: s1, a serial chip carries out serial connection on pseudo-random binary sequence signal streams generated by the serial chip; s2, the channel conversion device transmits the serial data to the deserializing chip; s3, the deserializing chip deserializes the received serial data; s4, the switch chip is in communication connection with the receiving interface of the serial chip through controlling any one of the transmitting interfaces of the deserializing chip, so that the serial chip receives the data after deserializing of the deserializing chip, the serial chip judges whether the received data after deserializing is consistent with the data of the pseudo-random binary sequence signal stream, and after finishing a judging process, any other transmitting interface of the deserializing chip is in communication connection with the receiving interface of the serial chip through the switch chip until the transmitting interface of the deserializing chip is in communication connection with the receiving interface of the serial chip at least once. The problem of the scheme design complicacy when carrying out AC test and DC test simultaneously is solved.

Description

Method and device for testing serial deserializing chip

Technical Field

The present invention relates to the field of chip testing, and in particular, to a method and apparatus for testing a serial deserialized chip.

Background

With the continuous development of the new energy intelligent automobile market, the number of vehicle cameras is increased, the data transmission requirements of the cameras are increased, the resolution requirements of the cameras are higher and higher in ADAS (advanced driving assistance system) application, ADAS (ADVANCED DRIVER ASSISTANCE SYSTEMS) is a generic term of a series of vehicle-mounted devices, a large amount of data transmission needs to depend on a vehicle-mounted serial chip and a de-serial chip, the vehicle-mounted serial chip and the de-serial chip are applied in pairs, besides the cameras, screen display in a seat cabin is also applied, wherein the interfaces of the cameras are MIPI C-PHY and MIPID-PHY, C-PHY and D-PHY are physical layer interface standards, C-PHY is a composite physical layer, D-PHY is a digital physical layer, and the digital-PHY is initiated by MIPI alliance and is a sub-protocol of a mobile industry processor interface (Mobile Industry Processor Interface, MIPI for short).

In mass production of vehicle-mounted chips, zero defect requirements need to be met, a certain test coverage rate needs to be met, an AC test and a DC test need to be performed, the AC test is also called an actual test (at-SPEED TESTING) or a fast test (fast test), and the test frequency is the same as the actual working frequency of the chips. In the scan test, it may be referred to as AC SCAN TEST or at-SPEED SCAN TEST. The AC test method mainly comprises the steps of directly connecting a power chip to be tested to an AC source with a load, detecting the ripple performance of the power chip to be tested by measuring the waveform and amplitude of direct-current output voltage or current, and the DC test is a process of verifying whether the electrical performance of the chip meets the design requirements by measuring the direct-current characteristic parameters (such as current, voltage and resistance) of the chip. In DC testing, a power chip to be tested is directly connected to a DC source with a load, and by measuring the waveform and amplitude of the DC output voltage or current, the stability and ripple performance of the power chip to be tested are detected, and especially, AC testing and DC testing are accomplished at the expense of testing cost like a high-speed MIPI interface or a serial chip interface and a deserializing chip interface, which typically requires 4 serial chips to dock 1 deserializing chip, as shown in fig. 1.

The peripheral interface of the serial chip is a receiving interface and a serial interface, as shown in fig. 2, the deserializing chip generally integrates 4 deserializing interfaces and 2 transmitting interfaces, as shown in fig. 3, if the high-speed signals are to be covered completely, the hardware scheme is, for example, FPGA (Field Programmable GATE ARRAY, i.e. field programmable gate array, which is a digital logic circuit with its internal logic circuit structure configured by a user through a specific programming manner), etc., for example, CN115980553a relates to the technical field of mass production testing of ATE testers, and in particular, a mass production testing method based on a digital ATE tester includes: z1: determining the model of an ATE tester according to the test requirement of the chip and initializing the FPGA chip; z2: confirming SYNC FRAME chips through an interface of the FPGA, decoding Serdes signals output by SYNC FRAME chips, and performing PRBS test; z3: after the test is passed, the FPGA is used for collecting data of the ADC and converting the data of the ADC, the ATE and the FPGA carry out handshake interaction, a test completion signal is fed back to the FPGA, and the FPGA returns to an initialization waiting state. FIG. 4 is a flow chart of a method of mass production testing based on a digital ATE tester; FIG. 5 is a control chart of FPGA test flow of mass production test based on a digital ATE tester, and FIG. 6 is a test hardware structure diagram of mass production test based on a digital ATE tester; fig. 7 is a test structure diagram of a mass production test based on a digital ATE tester. ATE tester, automatic Test Equipment, is an automation device specially used for chip testing, SYNC FRAME chip is usually referred to as a chip for implementing a data synchronization function, which can ensure accurate transmission and synchronization of data between different devices or systems, ADC (Analog-to-Digital Converter) is an abbreviation of Analog-to-digital converter, its function is to convert continuous Analog signals into discrete digital signals, PRBS (Pseudo-Random Binary Sequence) is a binary sequence with specific statistical properties, PRBS (Pseudo-Random Binary Sequence) is a binary sequence with specific statistical properties, serDes is an abbreviation of English SERILIzer/DESerializer (deserializer) is a mainstream serial communication technology of Time Division Multiplexing (TDM) and point (P2P). It can be seen that the hardware scheme is very complex, the number of used devices is large, and the cost is increased to a certain extent.

Disclosure of Invention

The invention aims to overcome the defect of complex design of a scheme when AC test and DC test are simultaneously carried out in the prior art, and provides a serial deserializing chip test method and device.

In order to achieve the above object, the present invention provides the following technical solutions:

A serial deserializing chip testing method comprises the following steps:

s1, a serial chip carries out serial connection on pseudo-random binary sequence signal streams generated by the serial chip;

S2, the channel conversion device transmits data which are serial in the serial chip to the deserializing chip through communication connection between the serial interface of the serial chip and the deserializing interface of the deserializing chip at the same time or in a time sharing mode, wherein 1 serial chip has only 1 serial interface and 1 receiving interface, the number of the deserializing interfaces of 1 deserializing chip is M, the number of the transmitting interfaces of 1 deserializing chip is X, and M and X are integers larger than 1;

S3, the deserializing chip deserializes the received data which are serial in the serial chip;

S4, the switch chip is in communication connection with the receiving interface of the serial chip by controlling any one of the transmitting interfaces of the deserializing chip, so that the serial chip receives the data deserialized by the deserializing chip, the serial chip judges whether the received data deserialized by the deserializing chip is consistent with the data of the pseudo-random binary sequence signal stream, and after finishing a judging process, any other transmitting interface of the deserializing chip is in communication connection with the receiving interface of the serial chip through the switch chip until the transmitting interface of the deserializing chip is in communication connection with the receiving interface of the serial chip at least once.

Preferably, in step S2, the channel conversion device transmits the data after being serially connected in the serial chip to the deserializing chip through the communication connection between the serial interface of the serial chip and the deserializing interface of the deserializing chip, where the channel conversion device is a power divider, the output interfaces of the power divider are communicatively connected with any N deserializing interfaces of the deserializing chip, the number of the output interfaces of the power divider is N, N is an integer greater than 1, M is greater than or equal to N, the data after being serially connected in the serial chip received by the power divider is simultaneously transmitted to the deserializing chip through the output interfaces of the power divider, and the data output by each output interface of the power divider is identical to the data after being serially connected in the serial chip received by the power divider.

Preferably, in step S2, the channel conversion device transmits the data after being serially connected in the serial chip to the deserializing chip through the communication connection between the serial interface of the serial chip and the deserializing interface of the deserializing chip, and if the channel conversion device is a high-speed switch, the high-speed switch connects the serial interface of the serial chip with any one of the deserializing interfaces of the deserializing chip in a communication manner, so as to realize that the deserializing chip receives the data after being serially connected in the serial chip, and after finishing a process of judging whether the data after being deserialized by the deserializing chip received by the serial chip is consistent with the data of the pseudo-random binary sequence signal stream itself, the serial interface of the serial chip is connected with any one of the other deserializing interfaces of the deserializing chip in a communication manner through the high-speed switch until any of the deserializing chip is connected with the serial interface of the serial chip in a communication manner at least once.

Preferably, in step S1, the serial chip serializes the pseudo-random binary sequence signal stream generated by the serial chip, and the serial chip converts the pseudo-random binary sequence signal stream from parallel data A1 to serial data B1 through the serial chip.

Preferably, in step S3, the deserializing chip deserializes the received data after being serialized in the serial chip, and the deserializing chip converts the serial data B1 back into parallel data A2.

Preferably, in step S4, the deserializing chip includes a pseudo-random binary sequence signal stream discriminating module, configured to receive the parallel data A2 transmitted to the serial chip through the deserializing chip, and determine whether the parallel data A2 received by the serial chip is consistent with the parallel data A1.

A serial de-serial chip testing device is used for a serial de-serial chip testing method and comprises a serial chip, a channel conversion device, a switch chip and a de-serial chip,

The serial chip includes a serial interface and a receiving interface,

The deserializing chip comprises a deserializing interface and a transmitting interface,

The serial interface of the serial chip is in communication with the channel changing device,

The channel conversion device is in communication connection with a deserializing port of the deserializing chip,

The transmitting interface of the deserializing chip is in communication connection with the switch chip,

The switch chip is in communication connection with the receiving interface of the serial chip,

The serial chip is used for carrying out serial operation on the pseudo-random binary sequence signal stream generated by the serial chip, the deserializing chip is used for deserializing the data after the serial operation of the serial chip,

The channel conversion device is used for transmitting the data after being serial in the serial chip to the deserializing chip through the communication connection of the serial interface of the serial chip and the deserializing interface of the deserializing chip at the same time or in a time sharing way,

The switch chip is used for controlling the communication connection between any one of the transmitting interfaces of the deserializing chip and the receiving interface of the serial chip to realize that the serial chip receives the data deserialized by the deserializing chip, the serial chip is also used for judging whether the data deserialized by the deserializing chip is consistent with the data of the pseudo-random binary sequence signal stream generated by the serial chip,

The serial chip comprises 1 serial interface and 1 receiving interface, wherein the number of the deserializing interfaces of the deserializing chip is M, the number of the receiving interfaces of the deserializing chip is X, and M and X are integers larger than 1.

Preferably, the channel conversion device comprises a power divider and a high-speed switch, when the channel conversion device is the power divider, a serial interface of the serial chip is in communication connection with an input interface of the power divider, an output interface of the power divider is in communication connection with a deserializing port of the deserializing chip, the number of the output interfaces of the power divider is smaller than or equal to the number of the deserializing interfaces of the deserializing chip, a transmitting interface of the deserializing chip is in communication connection with the switch chip, and the switch chip is in communication connection with a receiving interface of the serial chip.

Preferably, the serial chip includes a pseudo-random binary sequence discriminating module, which is communicatively connected with the receiving interface of the serial chip, and is used for judging whether the data of the deserialized chip received by the receiving interface of the serial chip is consistent with the data of the pseudo-random binary sequence signal stream generated by the serial chip.

Compared with the prior art, the invention has the beneficial effects that:

The invention sets a switch chip between the serial chip and the deserializing chip, and the serial chip and the deserializing chip are connected with each other as the test chip to form a signal loop-back test, so that all interfaces of the serial chip and the deserializing chip can be tested, DC test and AC test of the chip are realized, and the invention also sets a channel conversion device between the serial chip and the deserializing chip, which can realize that data after serial of the serial chip is respectively sent to the deserializing chip for deserializing through different deserializing ports of the deserializing chip at the same time or in a time-sharing way, and realize that the serial interface of one serial chip is connected with a plurality of deserializing ports of the deserializing chip in a communication way, thereby reducing the setting quantity of the deserializing chip, and reducing the complexity of design scheme and further reducing the cost when the DC test and the AC test of the chip are required to be completed.

Drawings

FIG. 1 is a diagram of a typical on-board serial chip deserializing chip connection scheme;

FIG. 2 is a serial chip interface block diagram;

FIG. 3 is a block diagram of a deserializing chip interface;

FIG. 4 is a flow chart of a method of mass production testing based on a digital ATE tester;

FIG. 5 is a control chart of FPGA test flow based on mass production testing of a digital ATE tester;

FIG. 6 is a block diagram of test hardware for mass production testing based on a digital ATE tester;

FIG. 7 is a test structure diagram of a mass production test based on a digital ATE tester;

FIG. 8 is a block diagram of a serial de-serial chip test method;

FIG. 9 is a block diagram of a serial deserializing chip testing apparatus;

FIG. 10 is a block diagram of a loop-back test scheme;

FIG. 11 is a flow chart of a pseudo-random binary sequence signal flow;

FIG. 12 is a block diagram of a loop-back test scheme for serial chip 1-to-4-dock De-serial chip;

fig. 13 is a block diagram of a loop-back test scheme for serial chip 2-to-4-dock De-serial chip.

Detailed Description

The present invention will be described in further detail with reference to test examples and specific embodiments. It should not be construed that the scope of the above subject matter of the present invention is limited to the following embodiments, and all techniques realized based on the present invention are within the scope of the present invention.

Example 1

Considering that the connection relationship between the serial chip and the deserializing chip is that the 4 serial chips are abutted against 1 deserializing chip, as shown in fig. 1, if the combination is adopted, in the ATE multi-station carrier board, especially in the mass production test of the deserializing chip, for example, 16 serial chips are required as accompanying tests for the 4-station deserializing chip, the hardware scheme is very complicated, in order to continuously reduce the complexity of the scheme or the device, the connection relationship between the serial chip and the deserializing chip is considered to be switched by using a channel conversion device on the connection of the serial chip and the deserializing chip, the data transmission of the serial chip and the deserializing chip is not affected, and in addition, in order to realize the full coverage of the interface between the deserializing chip and the serial chip, that is, the connection relationship between the interface between the deserializing chip and the switch chip is switched by using the switch chip is introduced for completing the AC test and the DC test, therefore, the AC test and the DC test of the chip are completed for satisfying the design simple scheme, as shown in fig. 8, the serial deserializing chip test method comprises the following steps:

S1, a serial chip carries out serial on a pseudo-random binary sequence signal stream generated by the serial chip, wherein the serial chip is a Ser chip, namely a seriizer chip, and Chinese is a Serializer chip; the serial chip carries out serial on the pseudo-random binary sequence signal stream generated by the serial chip, and the serial chip converts the pseudo-random binary sequence signal stream into serial data B1 from parallel data A1 through the serial chip;

S2, the channel conversion device transmits data which are serial in the serial chip to the deserializing chip through communication connection between the serial interface of the serial chip and the deserializing interface of the deserializing chip at the same time or in a time sharing way, wherein 1 serial chip has only 1 serial interface and 1 receiving interface, the deserializing interfaces of 1 deserializing chip are 4, the transmitting interfaces of 1 deserializing chip are X, M and X are integers which are larger than 1, the serial interface of Ser chip is Serail interface, and the Chinese of Serail interface is actually the serial interface;

S3, the deserializing chip deserializes the received data which are serial in the serial chip, specifically, the deserializing chip converts the serial data B1 back to the parallel data A2, the deserializing chip is a De-Ser chip, the De-serizer chip is used for Chinese, a Deserializer interface of the De-Ser chip is used for Chinese translation, and the Chinese translation is used for the Deserializer interface;

S4, the switch chip is in communication connection with the receiving interface of the serial chip through controlling any one of the transmitting interfaces of the deserializing chip, so that the serial chip receives the deserialized data of the deserializing chip, the serial chip judges whether the received deserialized data is consistent with the data of the pseudo-random binary sequence signal flow, after finishing a judging process, any one of the other transmitting interfaces of the deserializing chip is in communication connection with the receiving interface of the serial chip through the switch chip until the transmitting interface of the deserializing chip is in communication connection with the receiving interface of the serial chip at least once, the transmitting interface of the De-Ser chip is generally 3 MIPI C-PHY TX interfaces or 2 MIPI C-PHY TX interfaces or MIPID-PHY TX interfaces, the MIPI C-PHY and MIPID-PHY are a physical layer interface standard, the C-PHY is a composite physical layer, the D-PHY is initiated by the MIPI alliance and is a sub-protocol interface (Mobile Industry Processor Interface, namely a Transmitter-Receiver interface of the mobile industry processor, namely a Receiver-Receiver interface of the RX MIPID. The deserializing chip comprises a pseudo-random binary sequence signal flow judging module which is used for receiving the parallel data A2 transmitted to the serial chip through the deserializing chip and judging whether the parallel data A2 received by the serial chip is consistent with the parallel data A1.

The number of the receiving interfaces of the serial chip and the number of the transmitting interfaces of the deserializing chip are asymmetric, so that the interfaces can be fully covered through the switch chip, the serial chip and the deserializing chip are provided with the switch chip, the serial chip and the deserializing chip are connected with each other to form a signal loop-back test, so that all the interfaces of the serial chip and the deserializing chip can be tested, DC test and AC test of the chips are realized, the main function of the switch chip is as a middleware or bridge, switching or conversion is performed between different interfaces, the interface connection between a processor and other components can be dynamically connected or disconnected according to the needs of a system, so that data transmission and control can be realized, and the serial data of the serial chip can be simultaneously or time-division transmitted to the deserializing chip through different deserializing interfaces of the deserializing chip to realize the communication connection of a plurality of the deserializing chip, so that the number of the serial interfaces of the serial chip and the deserializing chip is reduced, the design cost of the chip is reduced, and the complexity of testing scheme is reduced when the design of the AC is completed.

Example 2

The power divider is selected as a channel conversion device on the basis of the embodiment 1, the output interfaces of the power divider are in communication connection with any N deserializing ports of the deserializing chip, the number of the output interfaces of the power divider is N, N is an integer larger than 1, M is larger than or equal to N, data after serial connection of serial chips received by the power divider are simultaneously transmitted to the deserializing chip through the output interfaces of the power divider, and data output by each output interface of the power divider is identical with data after serial connection of serial chips received by the power divider. The serial interface of 1 serial chip is communicatively connected to the power divider, the power divider is divided into 4 paths of communication connections to the deserializing interface of the deserializing chip, as shown in fig. 12, the serial interfaces of 2 serial chips can also be respectively communicatively connected with 1 power divider, and are divided into 4 paths of communication connections to 1 De-Ser chip, as shown in fig. 13, the power divider has the function of signal distribution, i.e. 1 input signal is divided into 2 or more output signals, so that 1 signal can be conveniently transmitted to multiple receiving devices or systems at the same time, the requirement of multichannel signal distribution is met, and the input port is usually composed of 1 input port and multiple output ports, and receives signals from the source. In the invention, the input port of the power amplifier receives the data after the serial chip is serial, and then the distributed data is sent to the deserializing chip through the deserializing port of the deserializing chip by the output ports, and the data of the output ports are consistent with the data of the input ports. The complexity of scheme design is reduced, the number of devices is reduced, the cost is further reduced, and the method has popularization.

Example 3

The power divider of the embodiment 2 is replaced by a high-speed switch, the high-speed switch is respectively in communication connection with the serial chip and the deserializing chip, specifically, the high-speed switch is used for enabling the serial interface of the serial chip to be in communication connection with any deserializing port in the deserializing chip, so that the deserializing chip can receive data after the serial chip is serial, after finishing a process of judging whether the data after the deserializing chip is deserialized and received by the serial chip is consistent with the data of the pseudo-random binary sequence signal stream, the serial interface in the serial chip is in communication connection with any other deserializing port in the deserializing chip through the high-speed switch until any deserializing interface of the deserializing chip is in communication connection with the serial interface of the serial chip at least once. The communication connection relation between the serial interface of the high-speed switch switching serial chip and the deserializing interface of the deserializing chip is realized by sending a control instruction through an external control device, and the external control device switches the control instruction sent by the high-speed switch when detecting that the judgment process is completed once. The complexity of scheme design is reduced, the number of devices is reduced, the cost is further reduced, and the method has popularization.

Example 4

As shown in fig. 9, a serial de-serial chip testing apparatus for implementing a serial de-serial chip testing method includes a serial chip, a channel conversion device, a switching chip and a de-serial chip,

The serial chip comprises a serial interface and a receiving interface, the deserializing chip comprises a deserializing interface and a transmitting interface, the serial interface of the serial chip is connected with the channel conversion device in a communication way,

A serial chip for serializing the pseudo-random binary sequence signal stream generated thereby,

The deserializing chip is used for deserializing the data after the serial chip is used for serial,

The channel conversion device is used for transmitting the data after being serial in the serial chip to the deserializing chip through the communication connection of the serial interface of the serial chip and the deserializing interface of the deserializing chip simultaneously or in a time-sharing way,

The switch chip is used for controlling the communication connection between any one of the transmitting interfaces of the deserializing chip and the receiving interface of the serial chip to realize that the serial chip receives the data deserialized by the deserializing chip,

The serial chip is also used for judging whether the data after the deserializing of the deserializing chip is consistent with the data of the pseudo-random binary sequence signal stream generated by the serial chip,

The 1 serial chip has only 1 serial interface and 1 receiving interface, the number of the de-serial interfaces of the 1 de-serial chip is M, the number of the receiving interfaces of the 1 de-serial chip is X, and M and X are integers larger than 1.

The serial chip is a Ser chip, the serial interface of the serial chip is Serail interfaces, the receiving interface of the serial chip is MIPID-PHY RX interface, the deserializing chip is De-Ser chip, the deserializing interface of the De-Ser chip is Deseriizer interface, the transmitting interface of the De-Ser chip is MIPI C-PHY TX interface or MIPID-PHY TX interface, the types of channel conversion devices comprise power dividers and high-speed switches, and as shown in figure 10, the types of switch chips comprise MIPI SWITCH chips.

The MIPI SWITCH chip comprises a GPIO port for receiving and outputting control signals, and realizes the communication connection between any MIPI C-PHY TX interface or MIPID-PHY TX interface of the De-Ser chip and the MIPIDPHY RX interface of the Ser chip.

The power divider comprises an input interface and an output interface, the serial chip interface is in communication connection with the input interface of the power divider, the output interface of the power divider is in communication connection with a Deserializer interface, the number of the output interfaces of the power divider is smaller than or equal to that of the Deserializer interfaces, the MIPI C-PHY TX interface or MIPID-PHY TX interface is in communication connection with a MIPI SWITCH chip, and the MIPI SWITCH chip is in communication connection with the MIPI C-PHY TX interface or MIPID-PHY RX interface.

The serial chip comprises a pseudo-random binary sequence judging module which is in communication connection with the MIPID-PHY RX interface of the Ser chip and is used for judging whether the data of the De-Ser chip which is received by the MIPID-PHY RX interface of the Ser chip after deserializing is consistent with the data of the pseudo-random binary sequence signal stream generated by the Ser chip.

The scheme comprises generating pseudo-random binary sequence signal flow in Ser chip, transmitting the data to MIPID-PHY RX interface of Ser chip by Ser chip, verifying pseudo-random binary sequence signal flow generated by Ser chip by integrated pseudo-random binary sequence judging module in Ser chip by high-speed switch or power divider, transmitting the serial pseudo-random binary sequence signal flow to De-Ser chip, controlling received pseudo-random binary sequence signal flow by De-Ser chip, and switching over the pseudo-random binary sequence signal flow with the pre-random binary sequence signal flow generated by Ser chip by means of De-Ser chip MIPI C-PHY TX interface or MIPID-PHY TX interface to the MIPID-PHY RX interface of Ser chip, verifying pseudo-random binary sequence signal flow generated by Ser chip by integrated pseudo-random binary sequence judging module in Ser chip by high-speed switch or power divider, controlling communication connection of De-Ser chip by means of MIPI SWITCH chip to the pre-random binary sequence judging module by means of direct-Ser chip with the MIPID-PHY RX interface of Ser chip, and switching over the pseudo-random binary sequence signal flow generated by De-Ser chip by direct-Ser chip to the direct-current switch circuit of De-Ser chip by direct-Ser chip at least once, and verifying that the chip is connected with the chip by direct-Ser chip at least one time of direct-current switch 35 to make communication interface of De chip with the chip by direct-Ser chip, and direct communication interface of De chip by direct communication with the chip, and direct communication interface of De chip, wherein the chip is connected with the chip to realize communication function of direct communication interface with the chip, after the pseudo-random binary sequence discriminating module completes the verification of the pseudo-random binary sequence signal flow after one time of deserialization and the pseudo-random binary sequence signal generated by the Ser chip, the MIPI SWITCH chip switches the communication connection between the MIPID-PHY TX interface of the De-Ser chip and the MIPID-PHY RX interface of the Ser chip according to the control instruction, and the Ser chip only has 1 MIPID-PHY RX interface, so that the MIPID-PHY RX interface is only in communication connection with 1 of the MIPI C-PHY TX interfaces or MIPID-PHY TX interfaces of the De-Ser chip at a time until the MIPID-PHY RX interface of the Ser chip is connected with the MIPI C-PHY TX interfaces or MIPID-PHY TX interfaces of the De-Ser chip at least once, and the De-Ser chip generally has 2 MIPID-PHY TX interfaces or 3 MIPI C-PHY TX interfaces, so that the flow direction of the complete pseudo-random binary sequence signal flow is shown in figure 11.

The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather is intended to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the invention.

Claims

1. The serial deserializing chip testing method is characterized by comprising the following steps of:

S4, the switch chip is in communication connection with the receiving interface of the serial chip by controlling any one of the transmitting interfaces of the deserializing chip, so that the serial chip receives the data deserialized by the deserializing chip, the serial chip judges whether the received data deserialized by the deserializing chip is consistent with the data of the pseudo-random binary sequence signal stream, and after finishing a judging process, any one of the other transmitting interfaces of the deserializing chip is in communication connection with the receiving interface of the serial chip through the switch chip until any one of the transmitting interfaces of the deserializing chip is in communication connection with the receiving interface of the serial chip at least once.

2. The method for testing a serial deserializing chip according to claim 1, wherein in step S2, the channel conversion device transmits the data after being serially connected in the serial chip to the deserializing chip through the communication connection between the serial interface of the serial chip and the deserializing interface of the deserializing chip, and the channel conversion device is a power divider, the output interfaces of the power divider are in communication connection with any N number of deserializing interfaces of the deserializing chip, the number of the output interfaces of the power divider is N, N is an integer greater than 1, M is greater than or equal to N, the data after being serially connected in the serial chip received by the power divider is simultaneously transmitted to the deserializing chip through the output interfaces of the power divider, and the data output by each output interface of the power divider is identical to the data after being serially connected in the serial chip received by the power divider.

3. The method according to claim 1, wherein in step S2, the channel conversion device transmits the data after being serially connected in the serial chip to the deserializing chip through the communication connection between the serial interface of the serial chip and the deserializing interface of the deserializing chip, and the channel conversion device is a high-speed switch, and the high-speed switch communicatively connects the serial interface of the serial chip and any one of the deserializing interfaces of the deserializing chip, so as to realize that the deserializing chip receives the data after being serially connected in the serial chip, and after ending a process of judging whether the data after being serially connected in the deserializing chip received by the serial chip is consistent with the data of the pseudo-random binary sequence signal stream itself, the serial interface of the serial chip is communicatively connected with any one of the other deserializing interfaces of the deserializing chip through the high-speed switch until any one of the deserializing interfaces of the deserializing chip is communicatively connected with the serial interface of the serial chip at least once.

4. The method according to claim 1, wherein in step S1, the serial chip performs serial connection on the pseudo-random binary sequence signal stream generated by the serial chip, and the serial chip converts the pseudo-random binary sequence signal stream from parallel data A1 to serial data B1 through the serial chip.

5. The method according to claim 4, wherein in step S3, the deserializing chip deserializes the received data after being serialized in the serial chip, and the deserializing chip converts the serial data B1 back to parallel data A2.

6. The method according to claim 5, wherein in step S4, the deserializing chip includes a pseudo-random binary sequence signal stream discriminating module for receiving the parallel data A2 transmitted to the serial chip through the deserializing chip and judging whether the parallel data A2 received by the serial chip is identical to the parallel data A1.

7. A serial deserializing chip testing apparatus for implementing the method of any of claims 1 to 6, comprising a serial chip, a channel conversion device, a switching chip and a deserializing chip,

The serial chip includes a serial interface and a receiving interface,

8. The serial deserializing chip testing device according to claim 7, wherein the channel conversion device comprises a power divider and a high-speed switch, wherein when the channel conversion device is the power divider, a serial interface of the serial chip is in communication connection with an input interface of the power divider, an output interface of the power divider is in communication connection with a deserializing port of the deserializing chip, the number of the output interfaces of the power divider is smaller than or equal to the number of deserializing interfaces of the deserializing chip, a transmitting interface of the deserializing chip is in communication connection with the switch chip, and the switch chip is in communication connection with a receiving interface of the serial chip.

9. The device for testing a serial deserializing chip of claim 7, wherein the serial chip comprises a pseudo-random binary sequence judging module in communication connection with the receiving interface of the serial chip for judging whether the data of the deserializing chip received by the receiving interface of the serial chip is consistent with the data of the pseudo-random binary sequence signal stream generated by the serial chip.