CN118434152A - Reconfigurable ferroelectric transistor memory and preparation method thereof - Google Patents

Abstract

The invention provides a reconfigurable ferroelectric transistor memory, which comprises a storage end electrode, a storage end dielectric layer, a programming end electrode, a dielectric layer, a source end electrode, a drain end electrode, an ultrathin channel layer, a silicon dioxide layer and a silicon substrate, wherein the storage end electrode is connected with the programming end electrode; the threshold voltage of the channel is regulated and controlled by applying pulse signals to the storage end electrode, so that the storage state is changed, and the transistor has an information storage function; the channel carriers are controlled through a plurality of grid electrodes of a programming end and a storage end, and the bipolar of a Schottky barrier is utilized to realize the dynamic switching of N type and P type of the FeFET on the same device, so that the FeFET memory has reconfigurable characteristics. The invention uses the nonvolatile memory characteristic of the memory end dielectric layer, regulates and controls the charge stored in the ultrathin channel layer by using a pulse signal, and regulates and controls the type and the concentration of the conductive charge in the ultrathin channel layer by using a direct current signal, so that a single transistor has an information storage function.

Description

A reconfigurable ferroelectric transistor memory and a method for manufacturing the same

Technical Field

The present invention relates to the field of semiconductor technology, and in particular to a reconfigurable ferroelectric transistor memory and a preparation method thereof.

Background technique

The traditional von Neumann architecture faces a development bottleneck due to the physical separation of storage units and computing units. The more energy-efficient non-von Neumann architecture has become a new circuit paradigm. Integrated circuits of non-von Neumann architecture urgently need embedded storage and computing integrated memory units as basic building blocks. The current RFET has the potential to become a standardized module for future reconfigurable and multifunctional circuits in terms of CMOS logic devices. On the other hand, ferroelectric field effect transistors (FeFETs) as a new type of non-volatile memory are compatible with CMOS circuits in terms of read and write mechanisms and driving voltages, and are adapted to advanced CMOS processes. However, since the mobility of holes in silicon is usually 2 to 3 times lower than that of electrons, most research focuses on N-type FeFETs. The contradiction between the urgent need for P-type FeFETs and the less research on P-type FeFETs needs to be resolved. The demand for complementary FeFETs in CMOS in-memory computing circuits is becoming increasingly urgent.

By combining FeFET and RFET, the reconfigurable ferroelectric transistor memory constructed has the characteristics of composite reconfigurable multifunctionality. It can be used as a reconfigurable module of the multifunctional chip in the non-von Neumann architecture, realizing the functional density and energy efficiency upgrade of CMOS in-memory computing circuits, and developing a high-functional density, high-energy-efficiency "non-von" memory-computing integrated architecture, which is expected to become the basic unit of the ideal in-memory computing integrated circuit in the post-Moore era.

Summary of the invention

The purpose of the present invention is to meet the demand for ferroelectric transistor (FeFET) memory in CMOS in-memory computing, and propose a reconfigurable ferroelectric transistor memory and a preparation method thereof. Channel carriers are controlled by multiple gates, and the bipolarity of the Schottky barrier is fully utilized to achieve dynamic switching of the N-type and P-type FeFETs of this structure on the same device, so that the FeFET memory has reconfigurable characteristics.

In order to achieve the above object, the technical solution adopted by the present invention is:

A reconfigurable ferroelectric transistor memory comprises a storage terminal electrode, a storage terminal dielectric layer, a programming terminal electrode, a programming terminal dielectric layer, a source terminal electrode, a drain terminal electrode, an ultra-thin channel layer, a silicon dioxide layer and a silicon substrate;

The silicon substrate, silicon dioxide layer and ultra-thin channel layer are arranged in sequence, and the storage end dielectric layer, programming end dielectric layer, source end electrode and drain end electrode are arranged on a side of the ultra-thin channel layer away from the silicon dioxide layer;

The storage terminal electrode is arranged on a side of the storage terminal dielectric layer away from the ultra-thin channel layer, and the programming terminal electrode is arranged on a side of the programming terminal dielectric layer away from the ultra-thin channel layer;

The storage-end dielectric layer isolates the source-end electrode, the drain-end electrode and the programming-end electrode.

In one embodiment, the programming terminal electrode is located between the source terminal electrode and the drain terminal electrode, and the storage terminal electrode and the storage terminal dielectric layer are two locations, located between the programming terminal electrode and the source terminal electrode, and between the programming terminal electrode and the drain terminal electrode.

In one embodiment, the reconfigurable ferroelectric transistor memory further includes: a passivation layer; the passivation layer is arranged on a side of the ultra-thin channel layer away from the silicon dioxide layer, and the storage end dielectric layer and the programming end dielectric layer are arranged on a side of the passivation layer away from the ultra-thin channel layer.

In one embodiment, the material of the passivation layer is any one of Al ₂ O ₃ , SiO ₂ , SiON, HfON, TiON, and ZrON.

In one embodiment, the turn-on voltage of the reconfigurable ferroelectric transistor memory represents the charge storage state of the transistor;

The storage terminal electrode controls the threshold voltage of the ultra-thin channel layer and the switching of the device through charge storage, and the programming terminal electrode is responsible for regulating the type and concentration of the conduction charge in the ultra-thin channel layer;

The polarization state of the storage-end dielectric layer stores the information of the storage-end electrode and continuously regulates the working state of the device after the pulse ends;

The work functions of the metal and semiconductor of the source electrode and the drain electrode are similar, providing similar electron and hole tunneling barriers for Schottky contact.

In one embodiment, the ultra-thin channel layer is made of lightly doped or undoped semiconductor;

When the source electrode is grounded and the drain electrode is connected to a forward voltage, the device operating state is adjusted to N-FeFET: a forward voltage is applied to the programming electrode, and the channel region presents a low-resistance state. Under the combined effect of the forward voltage on the storage electrode, the device is turned on, thereby realizing the N-type operating mode of the reconfigurable ferroelectric transistor memory.

When the source electrode is grounded and the drain electrode is connected to a reverse voltage, the device operating state is adjusted to P-FeFET: a reverse voltage is applied to the programming electrode, the channel region presents a low-resistance state, and under the combined action of the reverse voltage on the storage electrode, the device is turned on, thereby realizing the P-type operating mode of the reconfigurable ferroelectric transistor memory.

In one embodiment, when performing a write operation on the N-FeFET, a positive pulse is applied to the storage terminal electrode, the storage terminal dielectric layer is polarized in a direction perpendicular to the inside of the channel, and the electrons in the ultra-thin channel layer respond to the polarized charge inside the storage terminal dielectric layer, so that the accumulation of electrons in the ultra-thin channel layer increases, so that the threshold voltage for turning on the device decreases, and the device storage state is 1; when performing an erase operation, a negative pulse is applied to the storage terminal electrode, so that the polarized charge in the storage terminal dielectric layer is reversed, and part of the electrons in the ultra-thin channel layer are repelled, so that the threshold voltage for turning on the device increases, and the device storage state is 0;

When the P-FeFET is written, a negative pulse is applied to the storage end electrode, the storage end dielectric layer is polarized in a direction perpendicular to the inside of the channel, and the holes in the ultra-thin channel layer respond to the polarized charges inside the storage end dielectric layer, so that the accumulation of holes in the ultra-thin channel layer increases, the threshold voltage for turning on the device decreases, and the device storage state is 1; when the erase operation is performed, a positive pulse is applied to the storage end electrode, the polarized charges in the storage end dielectric layer are reversed, part of the holes in the ultra-thin channel layer are repelled, the threshold voltage for turning on the device increases, and the device storage state is 0.

In one embodiment, the storage terminal electrode, programming terminal electrode, source terminal electrode, and drain terminal electrode are made of any one of metal tungsten, metal titanium, metal copper, metal aluminum, metal platinum, metal iridium, metal ruthenium, metal molybdenum, tungsten nitride, titanium nitride, tantalum nitride, iridium oxide, ruthenium oxide, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, and tantalum silicide; the ultra-thin channel layer is made of any one of Si, Ge, SiGe, GaN, GaAs, and SiC; the storage terminal dielectric layer is made of any one of AlScN, HYO, HZO, HSO, HAO, BFO, PZT, BST, ZrO ₂ , Al ₂ O ₃ , and ZnSnO ₃ ; the programming terminal dielectric layer is made of any one of HfO ₂ , SiO ₂ , SiON, Si ₃ N ₄ , TiO ₂ , HYO, HZO, HSO, HAO, BFO, PZT, BST, ZrO ₂ , Al ₂ O 3 _3. Any one of ZnSnO ₃ .

The present invention also provides a method for preparing the reconfigurable ferroelectric transistor memory, comprising the following steps:

Step 1, selecting a substrate consisting of an ultra-thin channel layer, a silicon dioxide layer and a silicon substrate in sequence, and etching an active area on the ultra-thin channel layer;

Step 2, depositing a programming end dielectric layer on the side of the ultra-thin channel layer away from the silicon dioxide layer, and depositing a metal material on the side of the programming end dielectric layer away from the ultra-thin channel layer by sputtering and etching to form a programming end electrode;

Step 3, using an etching process to remove the dielectric material of the source region and the drain region, using a sputtering process to deposit a thin layer of electrode material at both ends of the active region, and using a lift-off process to form a source terminal electrode and a drain terminal electrode;

Step 4, depositing ferroelectric material to form a storage end dielectric layer, growing a layer of metal electrode material on the side of the storage end dielectric layer away from the ultra-thin channel layer, etching the layer of metal electrode material and the storage end dielectric layer to form a programming end electrode, and completing the preparation of the reconfigurable ferroelectric transistor memory.

In one embodiment, the storage terminal electrode is formed on the basis of the programming terminal electrode, the source terminal electrode and the drain terminal electrode, and is filled in the gap between the programming terminal electrode and the source terminal electrode and the drain terminal electrode in a self-aligned manner.

Compared with the prior art, the present invention makes full use of the non-volatile storage characteristics of the storage-end dielectric layer, and regulates the storage state of the ultra-thin channel layer by changing the pulse signal applied to the storage-end electrode, thereby changing the threshold voltage, so that the transistor has an information storage function; the channel carriers are controlled by multiple gates at the programming end and the storage end, and the bipolarity of the Schottky barrier is utilized to realize the dynamic switching of the N-type and P-type of the FeFET of this structure on the same device, so that the FeFET memory has a reconfigurable characteristic; secondly, the present invention has stable durability characteristics, retention characteristics and synaptic characteristics, and can be used to develop a high-functional density, high-energy-efficiency "non-von" storage-computing integrated architecture, and is expected to become the basic unit of an ideal in-memory computing integrated circuit in the post-Moore era.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram of the structure of a reconfigurable ferroelectric transistor memory according to the present invention.

FIG. 2 is a cross-sectional view of A-A' in FIG. 1

FIG3 is a schematic diagram of the storage state of the reconfigurable ferroelectric transistor memory under different pulses and the corresponding energy band diagram, wherein the working state is N-FeFET and the storage state is 1.

FIG4 is a schematic diagram of the storage state of the reconfigurable ferroelectric transistor memory under different pulses and the corresponding energy band diagram, wherein the working state is N-FeFET and the storage state is 0.

FIG5 is a schematic diagram of the storage state of the reconfigurable ferroelectric transistor memory under different pulses and the corresponding energy band diagram, wherein the working state is P-FeFET and the storage state is 1.

FIG6 is a schematic diagram of the storage state of the reconfigurable ferroelectric transistor memory under different pulses and the corresponding energy band diagram, wherein the working state is P-FeFET and the storage state is 0.

FIG. 7 is a schematic diagram of the preparation process of a reconfigurable ferroelectric transistor memory.

In the figure: 1. storage end electrode, 2. storage end dielectric layer, 3. programming end electrode, 4. dielectric layer, 5. source end electrode, 6. drain end electrode, 7. ultra-thin channel layer, 8. silicon dioxide layer, 9. silicon substrate, 10. passivation layer.

Detailed ways

The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present invention.

As shown in Figures 1 and 2, it is a schematic diagram of the structure of the reconfigurable ferroelectric transistor memory of the present invention, which mainly includes a storage end electrode 1, a storage end dielectric layer 2, a programming end electrode 3, a programming end dielectric layer 4, a source end electrode 5, a drain end electrode 6, an ultra-thin channel layer 7, a silicon dioxide layer 8 and a silicon substrate 9.

In the present invention, the silicon substrate 9, the silicon dioxide layer 8 and the ultra-thin channel layer 7 are arranged in sequence. For the convenience of description, in the structures shown in Figures 1 and 2, it is considered that the three are arranged in sequence from bottom to top. The storage end dielectric layer 2, the programming end dielectric layer 4, the source end electrode 5 and the drain end electrode 6 are arranged on the side of the ultra-thin channel layer 7 away from the silicon dioxide layer 8, that is, its upper surface.

The storage terminal electrode 1 is arranged on a side of the storage terminal dielectric layer 2 away from the ultra-thin channel layer 7, that is, on its upper surface. The programming terminal electrode 3 is arranged on a side of the programming terminal dielectric layer 4 away from the ultra-thin channel layer 7, that is, on its upper surface. In addition, the storage terminal dielectric layer 2 isolates the source terminal electrode 5, the drain terminal electrode 6 and the programming terminal electrode 3. For example, the programming terminal electrode 3 is located between the source terminal electrode 5 and the drain terminal electrode 6. At this time, the storage terminal electrode 1 and the storage terminal dielectric layer 2 are two places, respectively located between the programming terminal electrode 3 and the source terminal electrode 5, and between the programming terminal electrode 3 and the drain terminal electrode 6.

In a further embodiment of the present invention, the reconfigurable ferroelectric transistor memory further comprises a passivation layer 10, which is disposed on a side of the ultra-thin channel layer 7 away from the silicon dioxide layer 8, i.e., the upper surface. The storage-end dielectric layer 2 and the programming-end dielectric layer 4 are disposed on the passivation layer 10, rather than on the ultra-thin channel layer 7.

In the present invention, the ultra-thin channel layer 7 refers to a channel layer with a relatively thin thickness, typically about 10 nm.

In the embodiment of the present invention, the storage terminal electrode 1, the programming terminal electrode 3, the source terminal electrode 5 and the drain terminal electrode 6 are all made of metal materials. Specifically, the materials of the storage terminal electrode 1, the programming terminal electrode 3, the source terminal electrode 5 and the drain terminal electrode 6 can be any one of metal tungsten, metal titanium, metal copper, metal aluminum, metal platinum, metal iridium, metal ruthenium, metal molybdenum, tungsten nitride, titanium nitride, tantalum nitride, iridium oxide, ruthenium oxide, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide and tantalum silicide.

The ultra-thin channel layer 7 may be made of intrinsic semiconductor, P-type lightly doped semiconductor or N-type lightly doped semiconductor. Specifically, the material of the ultra-thin channel layer 7 may be any one of Si, Ge, SiGe, GaN, GaAs and SiC.

The material of the storage end dielectric layer 2 may be any one of AlScN, HYO, HZO, HSO, HAO, BFO, PZT, BST, ZrO ₂ , Al ₂ O ₃ , and ZnSnO ₃ .

The material of the programming end dielectric layer 4 may be any one of HfO ₂ , SiO ₂ , SiON, Si ₃ N ₄ , TiO ₂ , HYO, HZO, HSO, HAO, BFO, PZT, BST, ZrO ₂ , Al ₂ O ₃ , and ZnSnO ₃ .

The material of the passivation layer 10 may be any one of Al ₂ O ₃ , SiO ₂ , SiON, HfON, TiON, and ZrON.

The threshold voltage of the reconfigurable ferroelectric transistor memory device of the present invention represents the charge storage state in the ultra-thin channel layer 7; the storage terminal electrode 1 controls the threshold voltage of the ultra-thin channel layer 7 and the switch of the device through charge storage, and the programming terminal electrode 3 is responsible for regulating the type and concentration of the conductive charge in the ultra-thin channel layer 7; the polarization state of the storage terminal dielectric layer 2 stores the information of the storage terminal electrode 1, and continuously regulates the charge concentration and series resistance state of the channel after the pulse ends, that is, continuously regulates the working state of the device. The source terminal electrode 5 and the drain terminal electrode 6 Schottky contact provide similar electron and hole tunneling barriers.

Figures 3, 4, 5 and 6 are schematic diagrams of the principle of the reconfigurable ferroelectric transistor memory under different pulse and DC input control, taking the ultra-thin channel layer 7 using lightly doped semiconductors as an example: 1) When the drain electrode 6 is connected to the power supply voltage and the source electrode 5 is grounded, the main carriers in the ultra-thin channel layer 7 are electrons. When performing a "write" operation, a positive pulse is applied to the storage terminal electrode 1, and the storage terminal dielectric layer 2 is polarized in the direction perpendicular to the inside of the channel, attracting electrons to gather. Under the action of polarization, the electrons are bound to the channel surface. At this time, the storage state of the reconfigurable ferroelectric transistor memory is "1"; when performing an "erase" operation, when the programming terminal electrode 3 is not connected to the voltage, a negative pulse is applied to the storage terminal electrode 1, and the polarized charge in the storage terminal programming terminal dielectric layer 4 is reversed, and the device storage state is "0"; (2) When the source terminal electrode 5 is connected to the power supply voltage and the drain terminal electrode 6 is grounded, the main carriers in the ultra-thin channel layer 7 are holes. When performing a "write" operation, a negative pulse is applied to the storage terminal electrode 1, and the storage terminal dielectric layer 2 is polarized in the direction perpendicular to the outside of the channel, attracting holes to gather. The holes are bound to the channel surface under the action of polarization, and the storage state of the reconfigurable ferroelectric transistor memory is "1"; when performing an "erase" operation, when the programming terminal electrode 3 is not connected to a voltage, a positive pulse is applied to the storage terminal electrode 1, and the polarization charge in the storage terminal programming terminal dielectric layer 4 is reversed, and the device storage state is "0". When the ultra-thin channel layer 7 uses an intrinsic semiconductor, the principle is the same as above.

According to the above structure and working mechanism, the reconfigurable ferroelectric transistor memory of the present invention can have the advantages of larger window voltage, stable endurance characteristics, retention characteristics and synaptic characteristics.

In summary, by applying a pulse signal to the storage terminal electrode 1, the threshold voltage of the ultra-thin channel layer 7 and the switching state of the device can be controlled, and the type and concentration of the conductive charge in the ultra-thin channel layer 7 can be regulated by a DC signal. At the same time, the charge storage state of a single transistor is characterized by the turn-on voltage characteristics of the device, so that a single transistor has an information storage function, and a single device can achieve a larger storage window, which has the significant advantage of being reconfigurable.

The present invention utilizes the non-volatile storage characteristics of the storage-end dielectric layer, and by applying a pulse signal to the storage-end electrode, the threshold voltage of the ultra-thin channel layer and the switching state of the device can be controlled, and the type and concentration of the conduction charge in the ultra-thin channel layer can be regulated by a DC signal, while the charge storage state of a single transistor is characterized by the turn-on voltage characteristics of the device, so that a single transistor has an information storage function; by controlling the channel carriers through multiple gates at the programming end and the storage end and utilizing the bipolarity of the Schottky barrier, the dynamic switching of the N-type and P-type of the FeFET of this structure on the same device is realized, so that the FeFET memory has a reconfigurable characteristic. Specifically:

When the source terminal electrode 5 is grounded and the drain terminal electrode 6 is connected to a forward voltage, the device operating state is adjusted to N-FeFET: a forward voltage is applied to the programming terminal electrode 3, the channel region presents a low resistance state, and under the combined action of the forward voltage on the storage terminal electrode 1, the device is turned on, thereby realizing the N-type working mode of the reconfigurable ferroelectric transistor memory. When performing a write operation on the N-FeFET, a positive pulse is applied to the storage terminal electrode 1, the storage terminal dielectric layer 2 is polarized in a direction perpendicular to the inside of the channel, and the electrons in the ultra-thin channel layer 7 respond to the polarized charges inside the storage terminal dielectric layer 2, so that the accumulation of electrons in the ultra-thin channel layer 7 increases, and the threshold voltage of the device turning on decreases, and the device storage state is 1; when performing an erase operation, a negative pulse is applied to the storage terminal electrode 1, so that the polarized charges in the storage terminal dielectric layer 2 are reversed, and some electrons in the ultra-thin channel layer 7 are repelled, so that the threshold voltage of the device turning on increases, and the device storage state is 0.

When the source terminal electrode 5 is grounded and the drain terminal electrode 6 is connected to a reverse voltage, the device working state is adjusted to P-FeFET: a reverse voltage is applied to the programming terminal electrode 3, the channel region presents a low resistance state, and under the joint action of the reverse voltage on the storage terminal electrode 1, the device is turned on, thereby realizing the P-type working mode of the reconfigurable ferroelectric transistor memory. When the P-FeFET is written, a negative pulse is applied to the storage terminal electrode 1, the storage terminal dielectric layer 2 is polarized in the direction perpendicular to the inside of the channel, and the holes in the ultra-thin channel layer 7 respond to the polarized charges inside the storage terminal dielectric layer 2, so that the accumulation of holes in the ultra-thin channel layer 7 increases, and the threshold voltage of the device turning on decreases, and the device storage state is 1; when the erase operation is performed, a positive pulse is applied to the storage terminal electrode 1, so that the polarized charges in the storage terminal dielectric layer 2 are reversed, and some holes in the ultra-thin channel layer 7 are repelled, so that the threshold voltage of the device turning on increases, and the device storage state is 0.

Secondly, the present invention has stable durability, retention and synaptic characteristics, and can be used to develop a high-functional density, high-energy-efficiency "non-von" integrated memory and computing architecture, and is expected to become the basic unit of an ideal in-memory computing integrated circuit in the post-Moore era.

Referring to FIG. 7 , the present invention also includes a method for preparing a reconfigurable ferroelectric transistor memory, comprising the following specific steps:

1) selecting a substrate consisting of an ultra-thin channel layer 7, a silicon dioxide layer 8 and a silicon substrate 9 in sequence, and etching an active area on the ultra-thin channel layer 7;

2) On the ultra-thin channel layer 7, a passivation layer 10 (if any) and a dielectric material are sequentially deposited as a programming end dielectric layer 4, a metal material is deposited as a metal electrode on the upper surface of the programming end dielectric layer 4 by a sputtering process, and the metal layer is etched to form a programming end electrode 3;

3) Using an etching process, the dielectric layer of the source region and the drain region is removed, using a sputtering process, a thin layer of electrode material is deposited at both ends of the active region, and using a lift-off process to form a source terminal electrode 5 and a drain terminal electrode 6;

4) Depositing ferroelectric material to generate a storage-end dielectric layer 2, growing a layer of metal electrode material on the storage-end dielectric layer 2, etching the layer and the storage-end dielectric layer 2 to form a storage-end electrode 1, and completing the preparation of the reconfigurable ferroelectric transistor memory. Specifically, in this step, based on the formed programming-end electrode 3, source-end electrode 5, and drain-end electrode 6, the gap position between the programming-end electrode 3 and the source-end electrode 5 and the drain-end electrode 6 is formed in a self-aligned manner.

Three specific embodiments of methods for preparing reconfigurable ferroelectric transistor memories based on different materials are given below.

Embodiment 1:

The storage end dielectric layer 2 is made of HZO, the P-type lightly doped Si is used as the ultra-thin channel layer, and metal tungsten is used as the material of the storage end electrode 1, the programming end electrode 3, the source end electrode 5 and the drain end electrode 6. The specific manufacturing method is as follows:

Step 1: Select a substrate consisting of an ultra-thin channel layer 7, a silicon dioxide layer 8 and a silicon substrate 9 in sequence, and etch an active area on the P-type lightly doped Si ultra-thin channel layer 7.

Step 2: deposit a passivation layer on the ultra-thin channel layer 7 using atomic layer deposition technology, and immediately deposit a dielectric material to form a programming end dielectric layer 4, sputter grow a metal electrode on the programming end dielectric layer 4, and perform an etching process on the metal layer to form a programming end electrode 3;

In this step, a reactive sputtering process is used to first evacuate the reaction chamber using a molecular pump or a cold pump until the vacuum pressure reaches 0.02 Torr, and then, under the conditions of a power of 350 W and an Ar pressure of 5 mTorr, metal W is selected as the target material to uniformly sputter the upper surface of the programming end dielectric layer 4 to deposit a layer of metal W on its surface, as shown in FIG. 3 , to form a programming end electrode 3.

Step 3: using an etching process to remove the dielectric layer of the source region and the drain region, using a sputtering process to deposit a thin layer of metal at both ends of the active region, and using a lift-off process to form a source electrode 5 and a drain electrode 6;

In this step, a reactive sputtering process is used to first evacuate the reaction chamber using a molecular pump or a cold pump until the vacuum pressure reaches 0.02 Torr, and then, under the conditions of a power of 350 W and an Ar pressure of 5 mTorr, metal W is selected as a target material to uniformly sputter the upper surface of the programming end dielectric layer 4 to deposit a layer of metal W on its surface, thereby forming a source electrode 5 and a drain electrode 6.

Step 4: using an atomic layer deposition process and a self-aligned process to deposit ferroelectric materials in sequence to generate a storage end dielectric layer 2 and a metal electrode material, etching the layer and the storage end dielectric layer 2 to form a storage end electrode 1, and completing the preparation of a reconfigurable ferroelectric transistor memory;

In this step, an atomic layer deposition process is used, with tetraethylmethylamino hafnium (TEMAHf) and tetraethylmethylamino zirconium (TEMAZR) as hafnium precursor sources and zirconium precursor sources, respectively, and ionized water as precursor oxygen source, and the deposition is performed at a reaction temperature of 573K; then, by adjusting the pulse ratio of the hafnium precursor source and the zirconium precursor source, a HZO ferroelectric material film is deposited on the passivation layer to form a storage end dielectric layer 2.

In this step, a reactive sputtering process is used to first evacuate the reaction chamber using a molecular pump or a cold pump until the vacuum pressure reaches 0.02 Torr, and then, under the conditions of a power of 350 W and an Ar pressure of 5 mTorr, metal W is selected as a target material to uniformly sputter the surface of the storage-end dielectric layer 2, depositing a layer of metal W on its surface to form a storage-end electrode 1, and completing the preparation of a reconfigurable ferroelectric transistor memory.

Embodiment 2:

The storage end dielectric layer 2 is made of HYO ferroelectric material, the N-type lightly doped Ge is used as the ultra-thin channel 7, and metal titanium is used as the material of the storage end electrode 1, the programming end electrode 3, the source end electrode 5 and the drain end electrode 6. The specific manufacturing method is as follows:

Step 1: Select a substrate consisting of an ultra-thin channel layer 7, a silicon dioxide layer 8 and a silicon substrate 9 in sequence, and etch an active area on the ultra-thin channel layer 7 with an N-type lightly doped semiconductor Ge.

Step 2: deposit a passivation layer on the ultra-thin channel layer 7 using atomic layer deposition technology, and immediately deposit a dielectric material to form a programming end dielectric layer 4, sputter grow a metal electrode on the programming end dielectric layer 4, and perform an etching process on the metal layer to form a programming end electrode 3;

In this step, a reactive sputtering process is used to first evacuate the reaction chamber using a molecular pump or a cold pump until the vacuum pressure reaches 0.02 Torr, and then, under the conditions of a power of 350 W and an Ar pressure of 5 mTorr, metal Ti is selected as a target material to uniformly sputter the upper surface of the programming end dielectric layer 4 to deposit a layer of metal Ti on its surface, as shown in FIG. 3 , to form a programming end electrode 3.

Step three: using an etching process to remove the dielectric layer of the source region and the drain region, using a sputtering process to deposit a thin layer of metal at both ends of the active region, and using a lift-off process to form a source electrode 5 and a drain electrode 6.

In this step, a reactive sputtering process is used to first evacuate the reaction chamber using a molecular pump or a cold pump until the vacuum pressure reaches 0.02 Torr, and then, under the conditions of a power of 350 W and an Ar pressure of 5 mTorr, metal Ti is selected as a target material to uniformly sputter the upper surface of the programming end dielectric layer 4 to deposit a layer of metal Ti on its surface, thereby forming a source electrode 5 and a drain electrode 6.

Step 4: using an atomic layer deposition process and a self-aligned process to deposit ferroelectric materials in sequence to generate a storage end dielectric layer 2 and a metal electrode material, etching the layer and the storage end dielectric layer to form a storage end electrode 1, and completing the preparation of a reconfigurable ferroelectric transistor memory;

By using a pulsed laser sputtering deposition process, a HYO material film is formed on the surface of the passivation layer 10 by alternately sputtering and depositing double targets (HfO ₂ ceramic target 99.99%, Y ₂ O ₃ ceramic target 99.99%), and then the HYO material is crystallized by an annealing process to form a storage end dielectric layer 2.

In this step, a reactive sputtering process is used to first evacuate the reaction chamber using a molecular pump or a cold pump until the vacuum pressure reaches 0.02 Torr, and then, under the conditions of a power of 350 W and an Ar pressure of 5 mTorr, metal Ti is selected as a target material to uniformly sputter the upper surface of the storage-end dielectric layer 2, depositing a layer of metal Ti on its surface to form a storage-end electrode 1, and completing the preparation of a reconfigurable ferroelectric transistor memory.

Embodiment 3:

The storage end dielectric layer 2 is made of PZT material, the semiconductor layer 2 is made of intrinsic Si substrate, and metal copper is used as the material of the storage end electrode 1, the programming end electrode 3, the source end electrode 5 and the drain end electrode 6. The specific manufacturing method is as follows:

Step 1: Select a substrate consisting of an ultra-thin channel layer 7, a silicon dioxide layer 8 and a silicon substrate 9 in sequence, and etch an active area on the intrinsic Si ultra-thin channel layer 7.

Step 2: deposit a passivation layer on the ultra-thin channel layer 7 using atomic layer deposition technology, and immediately deposit a dielectric material to form a programming end dielectric layer 4, sputter grow a metal electrode on the programming end dielectric layer 4, and perform an etching process on the metal layer to form a programming end electrode 3;

In this step, a reactive sputtering process is used to first evacuate the reaction chamber using a molecular pump or a cold pump until the vacuum pressure reaches 0.02 Torr, and then, under the conditions of a power of 350 W and an Ar pressure of 5 mTorr, metal Cu is selected as the target material, and the upper surface of the programming end dielectric layer 4 is uniformly sputtered to deposit a layer of metal Cu on its surface, as shown in FIG. 3 , to form a programming end electrode 3.

Step 3: using an etching process to remove the dielectric layer of the source region and the drain region, using a sputtering process to deposit a thin layer of metal at both ends of the active region, and using a lift-off process to form a source electrode 5 and a drain electrode 6;

In this step, a reactive sputtering process is used to first evacuate the reaction chamber using a molecular pump or a cold pump until the vacuum pressure reaches 0.02 Torr, and then, under the conditions of a power of 350 W and an Ar pressure of 5 mTorr, metal Cu is selected as a target material to uniformly sputter the upper surface of the programming end dielectric layer 4 to deposit a layer of metal Cu on its surface, thereby forming a source electrode 5 and a drain electrode 6.

Step 4: Using the atomic layer deposition process, the self-aligned process successively deposits the ferroelectric material to generate the storage end dielectric layer 2 and the metal electrode material, etches the layer and the storage end dielectric layer to form the storage end electrode 1, and completes the preparation of the reconfigurable ferroelectric transistor memory.

In this step, an atomic layer deposition process is used, with lead nitrate (Pb(NO ₃ ) ₂ ), titanium nitrate (Ti(NO ₃ ) ₄ ) and zirconium nitrate (Zr(NO ₃ ) ₄ ) as precursor sources of lead, titanium and zirconium, respectively, and ionized water as a precursor oxygen source, and the deposition is performed at a reaction temperature of 573K; then, by adjusting the pulse ratio of the precursor sources of lead, titanium and zirconium, a PZT ferroelectric material film is deposited on the passivation layer to form a storage end dielectric layer 2.

In this step, a reactive sputtering process is used to first use a molecular pump or a cold pump to evacuate the reaction chamber until the vacuum pressure reaches 0.02 Torr, and then under the conditions of a power of 350 W and an Ar pressure of 5 mTorr, metal Cu is selected as the target material, and the upper surface of the storage-end dielectric layer 2 is uniformly sputtered to deposit a layer of metal Cu on its surface to form a storage-end electrode 1, and the preparation of the reconfigurable ferroelectric transistor memory is completed.

The present invention is not limited to the above-mentioned optimal implementation mode. Anyone can derive other various forms of products under the inspiration of the present invention. However, no matter what changes are made in the shape or structure, all technical solutions that are the same or similar to those of the present application fall within the protection scope of the present invention.

Claims (10)

1. The reconfigurable ferroelectric transistor memory is characterized by comprising a storage end electrode (1), a storage end dielectric layer (2), a programming end electrode (3), a programming end dielectric layer (4), a source end electrode (5), a drain end electrode (6), an ultrathin channel layer (7), a silicon dioxide layer (8) and a silicon substrate (9);

The silicon substrate (9), the silicon dioxide layer (8) and the ultrathin channel layer (7) are sequentially arranged, and the storage end dielectric layer (2), the programming end dielectric layer (4), the source end electrode (5) and the drain end electrode (6) are arranged on one surface, far away from the silicon dioxide layer (8), of the ultrathin channel layer (7);

the storage end electrode (1) is arranged on one surface of the storage end medium layer (2) far away from the ultrathin channel layer (7), and the programming end electrode (3) is arranged on one surface of the programming end medium layer (4) far away from the ultrathin channel layer (7);

The storage end medium layer (2) isolates the source end electrode (5), the drain end electrode (6) and the programming end electrode (3);

And the threshold voltage of the ultrathin channel layer (7) is regulated and controlled by applying pulse signals to the storage terminal electrode (1), so that the storage state is changed, and the transistor has an information storage function.

2. The reconfigurable ferroelectric transistor memory according to claim 1, characterized in that the programming terminal electrode (3) is located between the source terminal electrode (5) and the drain terminal electrode (6), the memory terminal electrode (1) and the memory terminal dielectric layer (2) are in two places, between the programming terminal electrode (3) and the source terminal electrode (5), and between the programming terminal electrode (3) and the drain terminal electrode (6).

3. The reconfigurable ferroelectric transistor memory of claim 1, further comprising: a passivation layer (10); the passivation layer (10) is arranged on one surface, far away from the silicon dioxide layer (8), of the ultrathin channel layer (7), and the storage end medium layer (2) and the programming end medium layer (4) are arranged on one surface, far away from the ultrathin channel layer (7), of the passivation layer (10).

4. A reconfigurable ferroelectric transistor memory according to claim 3, characterized in that the material of the passivation layer (10) is any one of Al ₂O₃、SiO₂, siON, hfON, tiON, zrON.

5. The reconfigurable ferroelectric transistor memory of claim 1, wherein the turn-on voltage of the reconfigurable ferroelectric transistor memory is representative of the charge storage state of the transistor;

The storage end electrode (1) controls the threshold voltage of the ultrathin channel layer (7) and the switch of the device through charge storage, and the programming end electrode (3) is responsible for regulating and controlling the type and concentration of conducted charges in the ultrathin channel layer (7);

The polarization state of the storage end medium layer (2) stores information of the storage end electrode (1), and continuously regulates and controls the working state of the device after the pulse is ended;

the metal of the source end electrode (5) and the drain end electrode (6) has similar work functions with the semiconductor, and provides similar electron and hole tunneling barriers for Schottky contact.

6. Reconfigurable ferroelectric transistor memory according to claim 5, characterized in that the ultra thin channel layer (7) is chosen from lightly doped or undoped semiconductors;

When the source electrode (5) is grounded and the drain electrode (6) is connected with a forward voltage, the working state of the device is adjusted to be N-FeFET: applying a forward voltage to the programming terminal electrode (3), and enabling the channel region to be in a low-resistance state, and starting the device under the combined action of the forward voltage and the forward voltage on the storage terminal electrode (1), so that an N-type working mode of the reconfigurable ferroelectric transistor memory is realized;

when the source electrode (5) is grounded and the drain electrode (6) is connected with a reverse voltage, the working state of the device is adjusted to be P-FeFET: and a reverse voltage is applied to the programming terminal electrode (3), the channel region presents a low resistance state, and the device is started under the combined action of the reverse voltage and the storage terminal electrode (1), so that the P-type working mode of the reconfigurable ferroelectric transistor memory is realized.

7. The reconfigurable ferroelectric transistor memory according to claim 6, wherein upon writing the N-FeFET, a positive pulse is applied to the memory side electrode (1), the memory side dielectric layer (2) is polarized in a direction perpendicular to the inside of the channel, electrons in the ultra-thin channel layer (7) respond to polarized charges in the inside of the memory side dielectric layer (2), so that the increase in electron accumulation in the ultra-thin channel layer (7) reduces the threshold voltage for device turn-on, and the device memory state is 1; when the erasing operation is carried out, negative pulse is applied to the storage end electrode (1) to enable polarization charges in the storage end dielectric layer (2) to be overturned, partial electrons in the ultrathin channel layer (7) are repelled, so that the threshold voltage of the device opening is increased, and the storage state of the device is 0;

When the P-FeFET is subjected to writing operation, negative pulse is applied to the storage end electrode (1), the storage end dielectric layer (2) is polarized towards the direction of the inside of a vertical channel, holes in the ultrathin channel layer (7) respond to polarized charges in the inside of the storage end dielectric layer (2), so that the accumulation of holes in the ultrathin channel layer (7) is increased to reduce the threshold voltage of the device on, and the storage state of the device is 1; when the erasing operation is carried out, positive pulse is applied to the storage end electrode (1), so that polarized charges in the storage end dielectric layer (2) are turned over, partial holes in the ultrathin channel layer (7) are repelled, the threshold voltage of the device on is increased, and the storage state of the device is 0.

8. The reconfigurable ferroelectric transistor memory according to any one of claims 1 to 7, wherein the material of the memory terminal electrode (1), the programming terminal electrode (3), the source terminal electrode (5), the drain terminal electrode (6) is any one of metallic tungsten, metallic titanium, metallic copper, metallic aluminum, metallic platinum, metallic iridium, metallic ruthenium, metallic molybdenum, tungsten nitride, titanium nitride, tantalum nitride, iridium oxide, ruthenium oxide, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, and tantalum silicide; the ultrathin channel layer (7) adopts any one of Si, ge, siGe, gaN, gaAs and SiC; any one of AlScN, HYO, HZO, HSO, HAO, BFO, PZT, BST, zrO ₂、Al₂O₃、ZnSnO₃ is adopted as the material of the storage end medium layer (2); any one of HfO₂、SiO₂、SiON、Si₃N₄、TiO₂、HYO、HZO、HSO、HAO、BFO、PZT、BST、ZrO₂、Al₂O₃、ZnSnO₃ is adopted as the material of the programming end medium layer (4).

9. A method of manufacturing a reconfigurable ferroelectric transistor memory as claimed in any one of claims 1 to 7, comprising the steps of:

step 1, selecting a substrate which is composed of an ultrathin channel layer (7), a silicon dioxide layer (8) and a silicon substrate (9) in sequence, and etching the ultrathin channel layer (7) into an active region;

Step 2, a programming end dielectric layer (4) is deposited on one surface of the ultrathin channel layer (7) far from the silicon dioxide layer (8), and a metal material is deposited on one surface of the programming end dielectric layer (4) far from the ultrathin channel layer (7) by utilizing a sputtering process and etched to form a programming end electrode (3);

Step 3, removing dielectric materials of the source region and the drain region by utilizing an etching process, depositing thin layer electrode materials at two ends of the active region by utilizing a sputtering process, and forming a source end electrode (5) and a drain end electrode (6) by utilizing a stripping process;

And 4, depositing ferroelectric materials to generate a storage end dielectric layer (2), growing a layer of metal electrode material on one surface of the storage end dielectric layer (2) far away from the ultrathin channel layer (7), and etching the layer of metal electrode material and the storage end dielectric layer (2) to form a programming end electrode (1) to finish the preparation of the reconfigurable ferroelectric transistor memory.

10. The method according to claim 9, wherein the memory terminal electrode (1) fills in a self-aligned manner in a gap position between the programming terminal electrode (3) and the source terminal electrode (5) and the drain terminal electrode (6) on the basis of the formation of the programming terminal electrode (3), the source terminal electrode (5) and the drain terminal electrode (6).