CN118427146A

CN118427146A - Slave equipment, transmission system and transmission method based on I2C bus

Info

Publication number: CN118427146A
Application number: CN202410530790.8A
Authority: CN
Inventors: 毛林军; 王玉永
Original assignee: SG Micro Beijing Co Ltd
Current assignee: SG Micro Beijing Co Ltd
Priority date: 2024-04-29
Filing date: 2024-04-29
Publication date: 2024-08-02

Abstract

The invention discloses a transmission method based on an I2C bus, which is applied to slave equipment, and comprises the steps of respectively receiving a data signal and a clock signal from the master equipment through a serial data line and a serial clock line; filtering the data signal and the clock signal respectively to obtain a filtered data signal and a filtered clock signal; delaying the filtered data signal for a first time to obtain a delayed data signal, and asymmetrically delaying rising and falling edges of the filtered clock signal to obtain a delayed clock signal; sampling the delay clock signal according to the delay data signal, and determining a data transmission state between the master device and the delay clock signal according to the level state of the sampled delay clock signal; and when the data transmission state is a communication state, transmitting the data signal according to the level state of the delay clock signal, so that the transmission system based on the I2C bus can normally communicate at any transmission rate.

Description

Slave equipment, transmission system and transmission method based on I2C bus

Technical Field

The present invention relates to the field of device communications technologies, and in particular, to a slave device, a transmission system, and a transmission method based on an I2C bus.

Background

The I2C (Inter-INTEGRATED CIRCUIT) interface is a serial bus mode for connecting a microcontroller to peripheral devices. The I2C bus is a bus composed of two lines, SDA (SERIAL DATA LINE ) and SCL (Serial Clock Line, serial clock line), and can transmit and receive data, and devices connected to the I2C bus can effectively realize data transmission only through the two lines, so that the I2C bus is widely used in the field of inter-device communication. When the I2C bus transmits data, the sender needs to reply a response every time when transmitting a certain amount of data, the sender continuously transmits after observing the response from the I2C bus, and the sender terminates if no response, so that the effectiveness of data transmission is ensured.

Fig. 1 shows a schematic diagram of a prior art I2C bus based transmission system. Referring to fig. 1, the I2C bus-based transmission system includes a master (master) 10 and a slave (slave) 20, the master 10 having control of the I2C bus, the slave 20 being accessed by the master 10, the master 10 controlling the master 10 and the slave 20 to transmit data signals on the SDA by controlling a clock signal of the SCL on the I2C bus during data transmission by the master 10 and the slave 20 using the I2C bus. In the prior art, during the data transmission process between the master device 10 and the slave device 20, the analog circuit of the slave device 20 delays the data signal transmitted on the SDA, and then inputs the delayed signal to the digital circuit for communication.

The I2C bus can work in a three-speed mode, namely a standard mode, a fast mode and a high-speed mode, and the data transmission rate of the I2C bus in the three-speed mode is sequentially increased. The transmission mode in the prior art is not problematic in the standard mode and the fast mode, i.e. the highest transmission rate is 1MHZ, but in the high speed mode, i.e. the highest transmission rate is 3.4MHZ, communication errors are likely to occur in extreme cases, so a new I2C bus-based transmission system and transmission method have to be proposed to solve the above problems.

Disclosure of Invention

In view of the foregoing, it is an object of the present invention to provide a slave device, a transmission system and a transmission method based on an I2C bus, so that the I2C bus can correctly transmit data in all three rate modes.

According to an aspect of the present invention, there is provided an I2C bus-based transmission method applied to a slave device, the transmission method including: receiving a data signal and a clock signal from a master device through a serial data line and a serial clock line, respectively; filtering the data signal and the clock signal respectively to obtain a filtered data signal and a filtered clock signal; delaying the filtered data signal for a first time to obtain a delayed data signal, and asymmetrically delaying rising and falling edges of the filtered clock signal to obtain a delayed clock signal; sampling the delay clock signal according to the delay data signal, and determining a data transmission state between the master device and the delay clock signal according to the level state of the sampled delay clock signal; and transmitting the data signal according to the level state of the delay clock signal when the data transmission state is a communication state.

Optionally, the asymmetrically delaying the rising edge and the falling edge of the filtered clock signal to obtain the delayed clock signal includes delaying the filtered clock signal by a second time when the rising edge occurs in the filtered clock signal, and delaying the filtered clock signal by a third time when the falling edge occurs in the filtered clock signal, where the third time is less than the second time, and outputting the delayed clock signal.

Optionally, the third time is zero.

Optionally, the step of sampling the delayed clock signal according to the delayed data signal, and determining the data transmission state with the master device according to the sampled level state of the delayed clock signal includes sampling the delayed clock signal when a falling edge occurs in the delayed data signal, characterizing that the data transmission state is an initial state if the delayed clock signal is at a high level, characterizing that the data transmission state is a communication state if the delayed clock signal is at a low level, sampling the delayed clock signal when a rising edge occurs in the delayed data signal, characterizing that the data transmission state is a termination state if the delayed clock signal is at a high level, and characterizing that the data transmission state is a communication state if the delayed clock signal is at a low level.

Optionally, when the data transmission state is a communication state, transmitting the data signal according to the level state of the delay clock signal includes sampling the filtered data signal when a rising edge occurs in the delay clock signal, and outputting a data response signal to the master device when a falling edge occurs in the delay clock signal.

According to a second aspect of the present invention, there is provided an I2C bus based slave device comprising a first analog circuit for receiving a data signal from a master device over a serial data line and filtering it to obtain a filtered data signal; a first delay circuit for delaying the filtered data signal by a first time to obtain a delayed data signal; the second analog circuit is used for receiving the clock signal from the main equipment through the serial clock line and filtering the clock signal to obtain a filtered clock signal; the second delay circuit is used for asymmetrically delaying the rising edge and the falling edge of the filtering clock signal to obtain a delay clock signal; and the digital circuit is used for sampling the delay clock signal according to the delay data signal, determining a data transmission state between the digital circuit and the main equipment according to the level state of the sampled delay clock signal, and transmitting the data signal according to the level state of the delay clock signal when the data transmission state is a communication state.

Optionally, the second delay circuit is configured to delay the filtered clock signal by a second time when a rising edge occurs in the filtered clock signal, and delay the filtered clock signal by a third time when a falling edge occurs in the filtered clock signal, and output the delayed clock signal, wherein the third time is less than the second time.

Optionally, the second delay circuit is configured to set the third time to zero.

Optionally, the digital circuit includes: the detecting unit is used for sampling the delay clock signal when the delay data signal has a falling edge, representing that the data transmission state is an initial state if the delay clock signal has a high level, representing that the data transmission state is a communication state if the delay clock signal has a low level, and sampling the delay clock signal when the delay data signal has a rising edge, representing that the data transmission state is a termination state if the delay clock signal has a high level, and representing that the data transmission state is a communication state if the delay clock signal has a low level; the data receiving unit is used for sampling the filtered data signal when the rising edge of the delay clock signal occurs, and the data transmitting unit is used for outputting a data response signal to the master device when the falling edge of the delay clock signal occurs.

According to a third aspect of the present invention, there is provided an I2C bus-based transmission system comprising a master device for generating a data signal supplied to a serial data line, and for generating a clock signal supplied to a serial clock line; and a slave device as described above.

According to the slave device, the transmission system and the transmission method based on the I2C bus, which are provided by the invention, the rising edge and the falling edge of the filtering clock signal are asymmetrically delayed, so that the enough margins of the data signal holding time and the data signal establishing time are ensured, and the transmission system based on the I2C bus can normally communicate at any transmission rate.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the present invention with reference to the accompanying drawings, in which:

FIG. 1 shows a schematic diagram of a prior art I2C bus-based transmission system;

FIG. 2 shows a schematic diagram of a transmission system based on an I2C bus;

FIGS. 3 a-3 b are timing diagrams illustrating partial signals of the transmission system of FIG. 2;

FIG. 4 shows a timing diagram of the transmission system of FIG. 2 when operating in a non-high speed mode;

FIG. 5 shows a timing diagram of the transmission system of FIG. 2 operating in a high speed mode;

FIG. 6 shows a schematic diagram of a configuration of an I2C bus-based transmission system according to an embodiment of the invention;

FIGS. 7a-7 b are timing diagrams illustrating partial signals of a transmission system according to embodiments of the present invention;

Fig. 8 shows a timing diagram of a transmission system according to an embodiment of the invention;

Fig. 9 shows a flow diagram of a transmission method based on an I2C bus according to an embodiment of the invention.

Detailed Description

Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. The same elements or modules are denoted by the same or similar reference numerals in the various figures. For clarity, the various features of the drawings are not drawn to scale.

It should be appreciated that in the following description, a "circuit" may include a single or multiple combined hardware circuits, programmable circuits, state machine circuits, and/or elements capable of storing instructions for execution by the programmable circuits. When an element or circuit is referred to as being "connected to" another element or circuit is "connected between" two nodes, it can be directly coupled or connected to the other element or intervening elements may be present, the connection between the elements may be physical, logical, or a combination thereof. In contrast, when an element is referred to as being "directly coupled to" or "directly connected to" another element, it means that there are no intervening elements present between the two.

Also, certain terms are used throughout the description and claims to refer to particular components. It will be appreciated by those of ordinary skill in the art that a hardware manufacturer may refer to the same component by different names. The present patent specification and claims do not take the form of an element or components as a functional element or components as a rule.

Furthermore, it should be noted that relational terms such as first and second are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

Fig. 2 shows a schematic diagram of a configuration of a transmission system based on an I2C bus, and fig. 3 a-3 b show timing diagrams of partial signals of the transmission system in fig. 2.

Referring to fig. 2 and 3, the I2C bus-based transmission system includes a master device 30 and a slave device 40, and the master device 30 and the slave device 40 are connected through a Serial Clock Line (SCL) and a serial data line (SDA). Wherein, the SDA transmits data signal data, and the SCL transmits clock signal clk.

The master device 30 generates the clock signal clk provided to SCL and generates the data signal data provided to SDA. The slave device 40 comprises a first analog circuit 41, a delay circuit 42, a second analog circuit 43 and a digital circuit 44, wherein the digital circuit 44 comprises a detection unit 44a, a data receiving unit 44b and a data transmitting unit 44c.

The first analog circuit 41 is configured to receive the data signal data from the main device 30, and to filter the data signal data to output a filtered data signal data_in1. Wherein, when the I2C bus is operated in the high-speed mode, i.e., the highest transmission rate is 3.4MHZ, the filtering time of the data signal data by the first analog circuit 41 is 10ns, and when the I2C bus is operated in the low-speed mode or the standard mode, i.e., the highest transmission rate is 1MHZ, the filtering time of the data signal data by the first analog circuit 41 is 50ns.

The delay circuit 42 is connected to the first analog circuit 41, and is configured to receive the filtered data signal data_in1, delay it by 20ns, and output a delayed data signal data_in.

The second analog circuit 43 is configured to receive the clock signal clk from the host device 30, and filter the clock signal clk to output a filtered clock signal clk_in. The second analog circuit 43 filters the clock signal clk for 10ns when the I2C bus is in the high-speed mode, and for 50ns when the I2C bus is in the low-speed mode or the standard mode.

The detecting unit 44a is configured to receive the data signal data and the delayed data signal data_in, and sample the filtered clock signal clk_in on a falling edge of the delayed data signal data_in, where clk_in=1 indicates that a start condition of transmitting data by the I2C bus is satisfied, and the master device 30 and the slave device 40 start transmitting data, and clk_in=0 indicates that the master device 30 and the slave device 40 are in a communication state.

Further, the detecting unit 44a is further configured to sample the filtered clock signal clk_in at a rising edge of the data signal data, where clk_in=1 indicates that the termination condition of the I2C bus transmission data is satisfied, and the master device 30 and the slave device 40 terminate the transmission data, and clk_in=0 indicates that the master device 30 and the slave device 40 are in a communication state.

The data receiving unit 44b is configured to receive the filtered clock signal clk_in, and sample the delayed data signal data_in at a rising edge of the filtered clock signal clk_in, where the sampled value is the value of the data signal data sent by the master device 30.

The data transmitting unit 44c is configured to receive the filtered clock signal clk_in and output the data response signal data_out to the host device 30 on the falling edge of the filtered clock signal clk_in. The main device 30 continues transmitting the data signal data upon receiving the data response signal data_out.

Fig. 4 shows a timing diagram of the transmission system of fig. 2 when operating in a non-high speed mode. Table one shows a table of information for the I2C bus when operating in different speed modes.

List one

In fig. 4 and table one, t _SU:DAT represents the data signal setup time. t _HD:DAT characterizes the data signal hold time.

Referring to fig. 4 and table one, when the I2C bus is operating in a non-high speed mode, such as a standard mode, a fast pulse mode, etc., t _SU:DAT is a minimum of 50ns and t _HD:DAT is a minimum of 0ns. When the filtered data signal data_in1 and the data response signal data_out are provided to the digital circuit 44 after being delayed by 20ns, the minimum value of t _SU:DAT is 30ns and the minimum value of t _HD:DAT is 20ns in the communication state (Normal area, i.e., normal communication area after the start state and the end state are removed), and since t _SU:DAT and t _HD:DAT have enough margins, it can be ensured that the I2C bus is not erroneously recognized as the start condition or the end condition in the communication state. Thus, the I2C-based transmission system shown in fig. 2 can ensure accuracy of communication in a non-high speed mode.

Fig. 5 shows a timing diagram of the transmission system of fig. 2 when operating in a high-speed mode. Table two shows the information table when the I2C bus is operating in different speed modes.

Watch II

In fig. 5 and table two, t _SU:DAT represents the data signal setup time. t _HD:DAT characterizes the data signal hold time.

Referring to fig. 5 and table two, when the I2C bus is operating in the high speed mode, t _SU:DAT is a minimum of 10ns and t ^HD _: ^DAT is a minimum of 0ns. When the filtered data signal data_in1 and the data response signal data_out are supplied to the digital circuit 44 after being delayed by a constant time, the constant time is too large or too small to be erroneous in an extreme case. The constant time is too small, the minimum value of t _HD:DAT is too small, so that the normal communication time is easily recognized as the starting condition or the ending condition at the point a of the following diagram, the constant time is too large, the minimum value of t _SU:DAT is too small, the normal communication time is easily recognized as the starting condition or the ending condition at the point B of the following diagram, for example, the delay time is 8ns, the minimum value of t _SU:DAT is 2ns, the minimum value of t _HD:DAT is 8ns, the margin of t _SU:DAT is not large enough, and if the setup time (setup time) of the process library used by the chip exceeds 2ns, an error occurs in the communication process. In addition, the delay time is ideally 8ns, but in actual use, the delay time varies due to different Process (Process), voltage (Voltage) and Temperature (Temperature) conditions (collectively referred to as PVT conditions). Such deviations may result in a large gap between the actual delay time and the ideal value, further reducing the margin of the system design. The reduction of the margin not only increases the risk of communication errors, but may also affect the performance and stability of the entire chip.

Therefore, a new I2C bus-based transmission system and transmission method have been proposed to solve the above problems.

FIG. 6 shows a schematic diagram of a configuration of an I2C bus-based transmission system according to an embodiment of the invention; fig. 7 a-7 b show timing diagrams of partial signals of a transmission system according to an embodiment of the invention.

Referring to fig. 6, the master device 100 and the slave device 200 are connected through an I2C bus, which includes a serial data line (SDA) and a Serial Clock Line (SCL). The serial data line (SDA) is used to transmit the data signal data, and the Serial Clock Line (SCL) is used to transmit the clock signal clk.

It will be appreciated that although only two devices are shown in fig. 6, in actual use, the I2C bus may connect multiple devices. Only one of the devices may obtain control of the I2C bus by means of arbitration or the like, thereby becoming a master device, and the device accessed by the master device may be referred to as a slave device. The master device 100 and the slave device 200 in fig. 6 may each have a clock pin (not shown) connected to the SCL and a data pin (not shown) connected to the SDA.

Referring to fig. 6 and 7, the master device 100 generates a clock signal clk supplied to the SCL and generates a data signal data supplied to the SDA. The slave device 200 includes a first analog circuit 210, a first delay circuit 220, a second analog circuit 230, a second delay circuit 240, and a digital circuit 250.

The first analog circuit 210 is configured to receive the data signal data from the main device 100, and filter the data signal data to output a filtered data signal data_in1. Wherein, when the I2C bus is operated in the high-speed mode (the highest transmission rate is 3.4 MHZ), the filtering time of the data signal data by the first analog circuit 210 is 10ns, and when the I2C bus is operated in the non-high-speed mode (the highest transmission rate is 1 MHZ), the filtering time of the data signal data by the first analog circuit 210 is 50ns.

The first delay circuit 220 is connected to the first analog circuit 210, and is configured to receive the filtered data signal data_in1, delay the filtered data signal data_in1 for a first time, and then output a delayed data signal data_in. Wherein the first time is, for example, 20ns.

The second analog circuit 230 is configured to receive the clock signal clk from the master device 100, and filter the clock signal clk to output a filtered clock signal clk_in1. The second analog circuit 230 filters the clock signal clk for 10ns when the I2C bus is in the high-speed mode, and for 50ns when the I2C bus is in the non-high-speed mode.

The second delay circuit 240 is connected to the second analog circuit 230 for asymmetrically delaying the filtered clock signal clk_in1 at its rising and falling edges. Specifically, when the rising edge occurs on the filtered clock signal clk_in1, the delayed clock signal clk_in is output after delaying the filtered clock signal clk_in1 for a second time, and when the falling edge occurs on the filtered clock signal clk_in1, the delayed clock signal clk_in is output after delaying the filtered clock signal clk_in1 for a third time. Wherein the second time is, for example, 30ns and the third time is much smaller than the second time.

Preferably, the third time is zero.

It will be appreciated that in practical applications, the third time is not necessarily completely zero, but it is necessarily less than the second time, subject to PVT conditions.

The digital circuit 250 is configured to sample the delayed clock signal clk_in according to the delayed data signal data_in, determine a data transmission state between the master device 100 and the slave device 200 according to a level state of the delayed clock signal clk_in, and transmit the data signal data according to the delayed clock signal clk_in when the data transmission state between the master device 100 and the slave device 200 is a communication state.

The digital circuit 250 includes a detection unit 251, a data reception unit 252, and a data transmission unit 253.

The detecting unit 251 is configured to sample the delayed clock signal clk_in at a falling edge and a rising edge of the delayed data signal data_in, respectively, so as to determine a data transmission state between the master device 100 and the slave device 200 according to a level state of the delayed clock signal clk_in. At the falling edge of the delay data signal data_in, if the delay clock signal clk_in is at a high level, that is, clk_in=1, the start condition of the I2C bus transmission data is met, and the master device 100 and the slave device 200 can start to transmit data, where the data transmission state is the start state; if the delayed clock signal clk_in is at a low level, that is, clk_in=0, the master device 100 and the slave device 200 are indicated to normally communicate, and the data transmission state is a communication state at this time; at the rising edge of the delayed data signal data_in, if the delayed clock signal clk_in is at a high level, that is, clk_in=1, the condition that the termination condition of the I2C bus transmission data is satisfied is characterized, and the master device 100 and the slave device 200 terminate the transmission data, where the data transmission state is a termination state; if the delayed clock signal clk_in is low, i.e., clk_in=0, it indicates that the master device 100 and the slave device 200 are communicating normally, and the data transmission state is the communication state.

The data receiving unit 252 is configured to receive the delayed clock signal clk_in and sample the filtered data signal data_in1 at a rising edge of the delayed clock signal clk_in. Wherein the filtered data signal data_in1 has the same value as the data signal data.

The data transmitting unit 253 is configured to receive the delayed clock signal clk_in, and output a data response signal data_out to the master device 100 on a falling edge of the delayed clock signal clk_in, so that the master device 100 continues to output the data signal data.

Fig. 8 shows a timing diagram of a transmission system according to an embodiment of the invention.

Referring to fig. 8, in the transmission system based on the I2C bus provided by the embodiment of the present invention, when the rising edge or the falling edge of the delayed data signal data_in detects the delayed clock signal clk_in, if clk_in=0, the minimum value of the data signal setup time is t _SU:DAT =10-20+30=20 ns, the minimum value of the data signal hold time is t _HD:DAT =0+20=20 ns, and the margin is large enough, so that the situation of false recognition does not occur, and accurate communication can be ensured.

When the filtered data signal data_in1 is sampled at the rising edge of the delayed clock signal clk_in, if clk_in=0, the minimum value of the data signal setup time is t _SU:DAT =10+30=40 ns, and the minimum value of the data signal hold time is t _HD:DAT＝0+t_LOW -30=130 ns.

When the data response signal data_out is transmitted along the falling edge of the delayed clock signal clk_in, the transmitted data response signal data_out is delayed by 20ns when it is returned to the digital circuit 250 of the slave device 200 through the data pin of the slave device 200, so as to ensure that the transmitted data response signal data_out is not erroneously recognized as a start condition or an end condition by the slave device 200.

Therefore, the transmission system of the I2C bus according to the embodiment of the present invention can accurately communicate between the master device 100 and the slave device 200 regardless of the rate mode in which the I2C bus operates.

Based on the transmission system of the I2C bus provided by the embodiment of the present invention, the embodiment of the present invention further provides a transmission method of the I2C bus, which is applied to the slave device 200, and includes:

Step S1: receiving a data signal data and a clock signal clk from the main device 100 through a serial data line and a serial clock line, respectively;

step S2: respectively filtering the data signal data and the clock signal clk to obtain a filtered data signal data_in1 and a filtered clock signal clk_in1;

Step S3: delaying the filtered data signal data_in1 for a first time to obtain a delayed data signal data_in, and asymmetrically delaying the filtered clock signal clk_in1 at the rising edge and the falling edge of the filtered clock signal clk_in1 to obtain a delayed clock signal clk_in;

Step S4: sampling a delay clock signal clk_in according to the delay data signal data_in, and determining a data transmission state with the main device 100 according to the level state of the delay clock signal clk_in;

step S5: when the data transmission state is a communication state, the data signal data is transmitted according to the delay clock signal clk_in.

In step S3, asymmetrically delaying the filtered clock signal clk_in1 at the rising edge and the falling edge to obtain the delayed clock signal clk_in includes:

The delayed clock signal clk_in is output after delaying the filtered clock signal clk_in1 by a second time, for example 30ns, when a rising edge occurs in the filtered clock signal clk_in1, and the delayed clock signal clk_in is output after delaying the filtered clock signal clk_in1 by a third time, for example, when a falling edge occurs in the filtered clock signal clk_in1, the third time being substantially less than the second time.

Preferably, the third time is zero.

In step S4, sampling the delayed clock signal clk_in according to the delayed data signal data_in, and determining the data transmission state with the master device 100 according to the level state of the delayed clock signal clk_in includes:

Sampling the delay clock signal clk_in when the delay data signal data_in has a falling edge, wherein the data transmission state is a starting state if clk_in=1, and the data transmission state is a communication state if clk_in=0; and sampling the delayed clock signal clk_in when the delayed data signal data_in rises, wherein the data transmission state is a termination state if clk_in=1, and the data transmission state is a communication state if clk_in=0.

In step S5, when the data transmission state is the communication state, the transmission of the data signal data according to the delay clock signal clk_in includes:

sampling the filtered data signal data_in1 when a rising edge occurs in the delayed clock signal clk_in; the data response signal data_out is output to the main device 100 when the delayed clock signal clk_in has a falling edge, so that the main device 100 continues to output the data signal data.

According to the transmission system and the transmission method based on the I2C bus, the rising edge and the falling edge of the filtering clock signal clk_in1 are asymmetrically delayed, so that the enough margin between the data signal holding time and the data signal establishing time is ensured, and the transmission system based on the I2C bus can normally communicate at any transmission rate.

Embodiments in accordance with the present invention, as described above, are not intended to be exhaustive or to limit the invention to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various modifications as are suited to the particular use contemplated. The scope of the invention should be determined by the appended claims and their equivalents.

Claims

1. An I2C bus-based transmission method applied to a slave device, the transmission method comprising:

receiving a data signal and a clock signal from a master device through a serial data line and a serial clock line, respectively;

Filtering the data signal and the clock signal respectively to obtain a filtered data signal and a filtered clock signal;

Delaying the filtered data signal for a first time to obtain a delayed data signal, and asymmetrically delaying rising and falling edges of the filtered clock signal to obtain a delayed clock signal;

Sampling the delay clock signal according to the delay data signal, and determining a data transmission state between the master device and the delay clock signal according to the level state of the sampled delay clock signal; and

And when the data transmission state is a communication state, transmitting the data signal according to the level state of the delay clock signal.

2. The transmission method of claim 1, wherein asymmetrically delaying rising and falling edges of the filtered clock signal to obtain a delayed clock signal comprises:

And when the filter clock signal has a falling edge, delaying the filter clock signal by a third time and outputting the delay clock signal, wherein the third time is smaller than the second time.

3. The transmission method of claim 2, wherein the third time is zero.

4. The transmission method of claim 1, wherein the sampling the delayed clock signal according to the delayed data signal and determining the data transmission state with the master device according to the sampled level state of the delayed clock signal comprises:

Sampling the delay clock signal when the delay data signal has a falling edge, if the delay clock signal is at a high level, representing the data transmission state as an initial state, if the delay clock signal is at a low level, representing the data transmission state as a communication state,

And when the delay data signal has a rising edge, sampling the delay clock signal, if the delay clock signal is in a high level, representing that the data transmission state is in a termination state, and if the delay clock signal is in a low level, representing that the data transmission state is in a communication state.

5. The transmission method according to claim 4, wherein when the data transmission state is a communication state, transmitting the data signal according to the level state of the delay clock signal comprises:

Sampling the filtered data signal at the rising edge of the delayed clock signal,

And outputting a data response signal to the master device when the delay clock signal has a falling edge.

6. An I2C bus-based slave device, comprising:

The first analog circuit is used for receiving the data signal from the main equipment through the serial data line and filtering the data signal to obtain a filtered data signal;

a first delay circuit for delaying the filtered data signal by a first time to obtain a delayed data signal;

the second analog circuit is used for receiving the clock signal from the main equipment through the serial clock line and filtering the clock signal to obtain a filtered clock signal;

the second delay circuit is used for asymmetrically delaying the rising edge and the falling edge of the filtering clock signal to obtain a delay clock signal;

And the digital circuit is used for sampling the delay clock signal according to the delay data signal, determining a data transmission state between the digital circuit and the main equipment according to the level state of the sampled delay clock signal, and transmitting the data signal according to the level state of the delay clock signal when the data transmission state is a communication state.

7. The slave device of claim 6, wherein the second delay circuit is configured to delay the filtered clock signal by a second time when a rising edge occurs in the filtered clock signal and to output the delayed clock signal after delaying the filtered clock signal by a third time when a falling edge occurs in the filtered clock signal, wherein the third time is less than the second time.

8. The slave device of claim 7, wherein the second delay circuit is configured to set the third time to zero.

9. The slave device of claim 6, wherein the digital circuit comprises:

The detecting unit is used for sampling the delay clock signal when the delay data signal has a falling edge, representing that the data transmission state is an initial state if the delay clock signal has a high level, representing that the data transmission state is a communication state if the delay clock signal has a low level, and sampling the delay clock signal when the delay data signal has a rising edge, representing that the data transmission state is a termination state if the delay clock signal has a high level, and representing that the data transmission state is a communication state if the delay clock signal has a low level;

A data receiving unit for sampling the filtered data signal when a rising edge occurs in the delayed clock signal,

And the data transmitting unit is used for outputting a data response signal to the master device when the delay clock signal has a falling edge.

10. An I2C bus based transmission system comprising:

A master device for generating a data signal supplied to the serial data line and generating a clock signal supplied to the serial clock line; and

A slave device as claimed in any one of claims 6 to 9.