CN118426735B - Variable pipeline error correction and detection addition operation system and method - Google Patents

Abstract

The application discloses a variable pipeline error correction and detection addition operation system and a method, which belong to the technical field of addition operation systems, and each adder unit is connected with an operation detection unit by carrying out addition operation on addition operands from a bus and outputting an addition result and a carry; the method and the device can accurately acquire the adder unit with addition errors by utilizing the operation detection unit to detect the addition result of the adder unit connected with the adder unit, correct the adder unit with the error detected in the responsible area by utilizing the multiplexing error correction unit, and output the corrected result to the adder unit with the error in the addition result to realize quick error correction.

Description

A variable pipeline error correction and detection addition operation system and method

Technical Field

The present invention belongs to the technical field of addition operation systems, and in particular relates to a variable pipeline error correction and detection addition operation system and method.

Background Art

With the advancement of artificial intelligence technology, the complexity of its algorithm models and the amount of data have increased dramatically, which has put forward higher requirements for hardware performance. The types of hardware currently supporting these massive operations mainly include graphics processing units (GPUs), field programmable gate arrays (FPGAs), and application-specific integrated circuits (ASICs). Among them, GPUs and ASICs, which are high-performance applications, integrate a large number of adders. The huge amount of addition logic will significantly increase the error rate, and due to the lack of corresponding processing methods, silent errors will occur or the traceability after the error is poor, making it difficult to recover quickly.

Summary of the invention

The purpose of the present invention is to provide a variable pipeline error correction and detection addition operation system and method to overcome the problems of the prior art that silent errors or poor traceability after errors and poor reliability of massive addition operation logic are easily caused.

To achieve the above purpose, the technical solution adopted by the present invention is as follows:

A variable pipeline error correction and detection addition operation system, comprising an adder unit, an operation detection unit and a multiplexing error correction unit;

The adder unit is used to perform addition operation on the addition operands from the bus and output the addition result and the carry, and each adder unit is connected to an operation detection unit;

The operation detection unit is used to detect the addition result and carry of the adder unit connected thereto. If the addition result of the adder unit is wrong, the operation detection unit outputs an error flag signal to the multiplexing error correction unit;

The multiplexing error correction unit corrects the addition result detected as an error in its responsible area according to the error flag signal, and outputs the error-corrected result to the adder unit with the erroneous addition result.

Preferably, the addition operand of the adder unit includes at least two-bit operands.

Preferably, the operation detection unit and the adder unit connected thereto work in parallel and simultaneously obtain two identical operands from at least two operands.

Preferably, the operation detection unit uses Burger code for detection and verification, and the multiplexing error correction unit uses error correction code to correct errors in addition operations in the adder unit.

Preferably, a plurality of adder units and a plurality of operation detection units share a multiplexing error correction unit.

Preferably, the multiplexing error correction unit includes an error correction arbiter, a data register and an error processing circuit;

The data register is used to obtain and store all addition operands and addition results when errors occur in the area it is responsible for;

The error correction arbiter is used to confirm the priority of all addition operands and addition results when errors occur, and to sort the priorities;

The error processing circuit corrects the addition operations of the adder units with incorrect addition results in order of priority, and other adder units that have not been corrected are in a waiting state.

A variable pipeline error correction and detection addition operation method comprises the following steps:

The addition result and carry of the addition operation of the addition operand are detected. If the addition result of the addition operation is wrong, the addition result detected to be wrong is corrected, and the correction result is output to the adder unit.

Preferably, an adder unit is used to perform addition operation on the addition operands from the bus, and output the addition result and the carry, and each adder unit is correspondingly connected to an operation detection unit;

The operation detection unit is used to detect the addition result and carry of the adder unit connected thereto. If the addition result of the adder unit is wrong, the operation detection unit outputs an error flag signal to the multiplexing error correction unit;

The multiplexed error correction unit is used to correct the addition result detected as erroneous in the area it is responsible for, and the error-corrected result is output to the adder unit with the erroneous addition result.

Preferably, the operation detection unit uses Burger code for detection and verification, and the multiplexing error correction unit uses error correction code to correct errors in addition operations in the adder unit.

Preferably, the specific process of using the multiplexed error correction unit to correct the addition results detected in the area it is responsible for is: a priority sorting signal is generated for all addition operands when errors occur and the addition results obtained from the addition operands when errors occur;

The addition operations of the adder units with incorrect addition results are corrected in sequence according to the priority, and other adder units that have not been corrected are in a waiting state.

Compared with the prior art, the present invention has the following beneficial technical effects:

The present invention provides a variable pipeline error correction and detection addition operation system, which performs addition operation on addition operands from a bus and outputs addition results and carries, and each adder unit is connected to an operation detection unit; the operation detection unit is used to detect the addition results and carries of the adder units connected to it, so that the adder units with addition errors can be accurately obtained, and the multiplexing error correction unit is used to correct the addition results with errors detected in the area responsible for it, and the corrected results are output to the adder units with incorrect addition results, so as to realize fast error correction. The present application can realize error correction of addition operation by using the operation detection unit, does not need to introduce additional overhead, improves the reliability of the logic operation unit, and provides a preferred solution for practical application.

Preferably, the operation detection unit and the adder unit connected thereto work in parallel, obtain two operands at the same time, and directly correct the link where the error occurs. The traceability is strong, and the error detection logic is simpler than the addition operation logic and does not affect the critical path timing.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a schematic diagram of the structure of a variable pipeline error correction and detection addition operation system according to an embodiment of the present invention.

FIG. 2 is a schematic diagram of an application of a PE array in a variable pipeline error correction and detection addition operation system according to an embodiment of the present invention.

FIG. 3 is a circuit diagram of an operation detection unit in an embodiment of the present invention.

FIG4 is a block diagram of the structure principle of a multiplexing error correction unit in an embodiment of the present invention.

FIG5 is a circuit diagram of an error handling process in an embodiment of the present invention.

FIG6 is a schematic diagram of an error correction process in which only one PE unit is detected to have an incorrect addition result in the area that the multiplexing error correction unit is responsible for according to an embodiment of the present invention.

FIG. 7 is a schematic diagram of an error correction process for detecting that the addition results of multiple PE units in the area in which the multiplexing error correction unit is responsible are incorrect in an embodiment of the present invention.

FIG8 is a flow chart of a variable pipeline error correction and detection addition operation method according to an embodiment of the present invention.

DETAILED DESCRIPTION

In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

As shown in FIG1 , the present invention provides a variable pipeline error correction and detection addition operation system, including an adder unit, an operation detection unit and a multiplexing error correction unit;

The adder unit is arranged in the processor unit, and is used for performing addition operation on the addition operands from the bus, and outputting the addition result and the carry, and each adder unit is connected to an operation detection unit;

The operation detection unit is used to detect the addition result and carry of the adder unit connected thereto. If the addition result of the adder unit is wrong, the operation detection unit outputs an error flag signal to the multiplexing error correction unit;

The multiplexing error correction unit corrects the addition result detected as an error in its responsible area according to the error flag signal, and outputs the error-corrected result to the adder unit with the wrong addition result. The present application uses an operation detection unit to detect the addition operation of the adder unit, and at the same time uses the multiplexing error correction unit to correct the addition operation with the wrong addition result. The present application uses the operation detection unit to realize the error correction of the addition operation, and can realize the traceability after the addition operation is wrong, without introducing additional overhead, thereby improving the reliability of the logic operation unit, and providing a preferred solution for practical application.

In a specific embodiment of the present application, the adder unit is universal, including but not limited to a ripple carry adder, a square root carry select adder, and a carry lookahead adder.

In a specific implementation of the present application, the addition operands of the adder unit include at least a first operand A and a second operand B.

The operation detection unit and the adder unit connected thereto can work in parallel to obtain the first operand A and the second operand B at the same time.

In a specific embodiment of the present application, the operation detection unit adopts an operation detection structure circuit, and the detection method adopts Burger code for detection.

The operation detection unit proposed in the present application is independent of the implementation micro-architecture of the adder unit and has a wide range of applications.

The error correction operation of the multiplexed error correction unit belongs to a semi-hidden pipeline stage in the addition operation pipeline. Only when the error flag signal of the operation detection unit is valid, the error correction pipeline stage is activated and the multiplexed error correction unit performs error correction.

The operation detection unit uses Berger code for detection, and the multiplexing error correction unit uses error correction code to correct the error of the addition operation in the adder unit.

The error correction code of the multiplexing error correction unit specifically adopts Hamming code.

The operations of the operation detection unit and the adder unit can be executed in parallel, and the error detection is simpler than the addition operation logic and does not affect the critical path timing.

In the present application, multiple adder units and multiple operation detection units share a multiplexed error correction unit, minimizing the hardware resource overhead of error correction. When no error occurs in the adder unit, the error correction enable is not turned on and the error correction pipeline stage is not inserted. This semi-hidden error correction pipeline stage design can significantly reduce the additional overhead introduced by the error correction design.

In the specific implementation manner of the present application, the adder unit in the ALU (arithmetic logic unit) operation unit is taken as an example for explanation, as shown in Figure 2, the present application is combined with the PE (processor unit) unit array to explain an example in the present application and exemplarily illustrate a variable pipeline error correction and detection addition operation system.

For each PE, the adder unit in its ALU is connected in parallel to an operation detection unit; the error probability of the addition operation based on PE is relatively small, and the adder units connected to each column of PE share a multiplexing error correction unit. When the operation detection unit in one of the PEs detects an addition operation error of the adder unit connected to the operation detection unit, an error flag signal is generated and sent to the multiplexing error correction unit in its corresponding area, that is, the operation detection unit outputs an error flag signal to the multiplexing error correction unit, and the multiplexing error correction unit completes the error correction processing operation and returns the correct result to the adder unit with the addition operation error. Under normal conditions, the addition of the adder unit is completed through instruction fetch, decoding, execution, memory access and write-back operations. When an addition result error is detected, a first-level error correction pipeline is inserted; at this time, the addition operation is completed through instruction fetch, decoding, execution, error correction, memory access, and write-back operations; the present application directly corrects the link where the error occurs, has strong traceability, and the error detection logic is simpler than the addition operation logic, and does not affect the critical path timing.

In a specific implementation manner of the present application, the operation detection unit specifically adopts Berger code for verification. The specific detection circuit is shown in Figure 3. The inputs of the operation detection unit are respectively the first operand A and the second operand B from the bus, the addition result S from the adder unit, the output SE from the multiplexing error correction unit, and the intermediate carry C of the addition operation; the operation is performed using a multi-operand adder, and the Berger code prediction _{formula of the addition operation result is: S'b} ⁼ _Ab + _Bb + _Cn - _Cb - _C0 , wherein _C0 corresponds to the carry input of the addition operation, _Cn corresponds to the carry output of the addition operation, _Ab represents the _B0 encoding of A, _Bb represents the _B0 encoding of B, and _Cb represents the _B0 encoding of C.

The error detection principle of the operation detection unit is to compare whether the predicted code _S'b is consistent with the actual code _Sb . In this example, a combinational logic comparison method is provided. _The predicted ^{code S'b} and the actual code _Sb are subjected to a bitwise XOR operation to obtain an error flag signal EN: if _the predicted code ^S'b is consistent with the actual code _Sb , the addition result is selected by the two-to-one selector and outputted normally as _Sout ; otherwise, if the predicted code ^S'b is inconsistent with _{the actual code Sb ,} it indicates that the addition operation of the adder is incorrect, an error flag signal is generated, and the multiplexing error correction unit is activated; the error flag signal EN includes an n-bit error indication signal of PE, where n represents the number of PEs in the area that the multiplexing error correction unit is responsible for.

As shown in FIG4 , the multiplexed error correction unit includes an error correction arbiter, a data register and an error handling circuit; the data register is used to obtain and store all addition operands and addition results S when errors occur in its responsible area; the error correction arbiter is used to confirm the priority of all addition operands and addition results S when errors occur, and perform priority sorting; the error handling circuit corrects the addition operations of the adder units with incorrect addition results in turn according to the priority sorting, and other uncorrected adder units are in a waiting state.

In a specific embodiment of the present application, as shown in FIG6 , if only one PE in the area responsible for the multiplexed error correction unit is detected to have an incorrect addition result, the error correction arbiter directly activates the error handling circuit, inserts an error correction pipeline stage, and the error handling circuit obtains the operand being processed by the PE in the data register for error correction; as shown in FIG7 , when multiple addition results are incorrect at the same time in the area responsible for the multiplexed error correction unit, the error handling circuit corrects the addition operations of the adder units with incorrect addition results in order of priority.

As shown in FIG5 , the error handling circuit diagram in the multiplexing error correction unit of the present application includes an encoder, an error correction decoder, an error corrector, and an enable control structure. The enable control structure is used to receive and store the priority sorting signal result from the error correction arbitrator, which is the result obtained by the error correction arbitrator confirming the priority of all addition operands and addition results when errors occur, and performing priority sorting; the encoder obtains the check bit P _s of the Hamming code in the addition result according to the addition operand when an error occurs, and the error correction decoder compares the check bit P _s with the addition result S obtained by the addition operand when an error occurs to obtain the check result E _S , and the error corrector corrects the error position of the check result E _S and outputs the corrected result.

This application takes Hamming code to correct 4-bit data as an example. The (7,4) Hamming code has 4 information bits and 3 check bits. The 4 information bits are recorded as S ₀ , S ₁ , S ₂ , S ₃ , and the 3 check bits are recorded as P _S0 , P _S1 , P _S2 .

Let vector X = [A ₀ , A ₁ , A ₂ , A ₃ , B ₀ , B ₁ , B ₂ , B ₃ , C ₀ , C ₁ , C ₂ , C ₃ ] ^T , _PS = [ _PS0 , _PS1 , _PS2 ] ^T , where A ₀ , A ₁ , A ₂ , A ₃ in vector X represent the information bits of the first operand A respectively, B ₀ , B ₁ , B ₂ , B ₃ in vector X represent the information bits of the second operand B respectively, and C ₀ , C ₁ , C ₂ , C ₃ represent the carry in the addition operation of the adder unit respectively. The encoding formula of the encoder is as follows:

The input of the error correction decoder is the addition result S obtained by the addition operand when an error occurs and the check bit _Ps of the Hamming code in the addition result. Let the vector Y=[ _S0 , _S1 , _S2 , _S3 , _Ps0 , _Ps1 , _Ps2 ] ^T , then the error correction decoder outputs the check result E _S as:

The error corrector decodes the check result _Es obtained after the error correction decoder is decoded into a 7-bit error correction signal S E (only the lower 7-bit signal output by the decoder is valid _{). The bit line corresponding to the error-free bit in the error correction signal S E is} output as 0, and the bit line corresponding to the error bit is output as 1. The information bits S ₀ , S ₁ , S ₂ , S ₃ in the addition result S obtained by the addition operand when an error occurs are bitwise XORed with the lower 4 bits in the error correction signal S _E to obtain the corrected result data S _R , that is:

In another embodiment of the present invention, a variable pipeline error correction and detection addition operation method is provided, which specifically includes the following steps:

The addition result of the addition operation is detected for the addition operands. If the addition result of the addition operation is wrong, the wrong addition result is corrected and the corrected addition result is output.

As shown in FIG8 , in the above method, an adder unit is used to perform addition operation on the addition operands from the bus and output the addition result, and each adder unit is connected to a corresponding operation detection unit;

The operation detection unit is used to detect the addition result of the adder unit connected thereto. If the addition result of the adder unit is wrong, the operation detection unit outputs an error flag signal to the multiplexing error correction unit;

The multiplexed error correction unit is used to correct the addition result detected as erroneous in the area it is responsible for, and the error-corrected result is output to the adder unit with the erroneous addition result.

The present application utilizes an operation detection unit to implement error correction of addition operations without introducing additional overhead, thereby improving the reliability of the logic operation unit.

Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims (8)

1. A variable pipeline error correction and detection addition operation system, characterized in that it includes an adder unit, an operation detection unit and a multiplexing error correction unit; The adder unit is used to perform addition operation on the addition operands from the bus and output the addition result, and each adder unit is connected to an operation detection unit; The operation detection unit is used to detect the addition result of the adder unit connected thereto. If the addition result of the adder unit is wrong, the operation detection unit outputs an error flag signal to the multiplexing error correction unit. The operation detection unit and the adder unit connected thereto work in parallel and simultaneously obtain two identical operands from at least two operands. The multiplexing error correction unit corrects the addition result detected as an error in its responsible area according to the error flag signal, and outputs the error-corrected result to the adder unit with the erroneous addition result. 2. A variable pipeline error correction and detection addition operation system according to claim 1, characterized in that the addition operand of the adder unit includes at least two-bit operands. 3. A variable pipeline error correction and detection addition operation system according to claim 1, characterized in that the operation detection unit uses Burger code for detection, and the multiplexing error correction unit uses error correction code to correct the error of the addition operation in the adder unit. 4. The variable pipeline error correction and detection addition operation system according to claim 1 is characterized in that a plurality of adder units and a plurality of operation detection units share a multiplexing error correction unit. 5. A variable pipeline error correction and detection addition operation system according to claim 1, characterized in that the multiplexing error correction unit comprises an error correction arbiter, a data register and an error processing circuit; The data register is used to obtain and store all addition operands and addition results when errors occur in the area it is responsible for; The error correction arbiter is used to confirm the priority of all addition operands and addition results when errors occur, and to sort the priorities; The error processing circuit corrects the addition operations of the adder units with incorrect addition results in order of priority, and other adder units that have not been corrected are in a waiting state. 6. A variable pipeline error correction and detection addition operation method, characterized in that it comprises the following steps: The addition result of the addition operation is detected for the addition operands. If the addition result of the addition operation is wrong, the wrong addition result is corrected and the corrected addition result is output: Specifically: an adder unit is used to perform addition operation on the addition operands from the bus and output the addition result, and each adder unit is connected to a corresponding operation detection unit; The operation detection unit is used to detect the addition result of the adder unit connected thereto. If the addition result of the adder unit is wrong, the operation detection unit outputs an error flag signal to the multiplexing error correction unit. The operation detection unit and the adder unit connected thereto work in parallel and simultaneously obtain two identical operands from at least two operands. The multiplexed error correction unit is used to correct the addition result detected as erroneous in the area it is responsible for, and the error-corrected result is output to the adder unit with the erroneous addition result. 7. A variable pipeline error correction and detection addition operation method according to claim 6, characterized in that the operation detection unit uses Burger code for detection, and the multiplexing error correction unit uses error correction code to correct the error of the addition operation in the adder unit. 8. A variable pipeline error correction and detection addition operation method according to claim 6, characterized in that the multiplexed error correction unit is used to correct the error detected in the addition result in its responsible area. The specific process is: all the addition operands when errors occur and the addition results obtained by the addition operands when errors occur are prioritized; The addition operations of the adder units with incorrect addition results are corrected in sequence according to the priority, and other adder units that have not been corrected are in a waiting state.