CN118425723B - A leakage test structure of a transistor array and a generation method and storage medium thereof - Google Patents

Abstract

The application relates to a leakage test structure of a transistor array, a generation method thereof and a storage medium, wherein the method comprises the following steps: acquiring a transistor array; three transverse metal wires are paved on each row of transistors of the transistor array and are respectively connected with the grid electrode, the source electrode and the drain electrode of the transistors in the same row through connecting holes; connecting two adjacent rows of transverse metal wires connected with the same electrode of the transistor through longitudinal metal wires, and alternately paving the longitudinal metal wires on two sides of the transistor array to generate three metal wires of a serpentine wiring; the three metal windings are respectively used as a grid electrode, a source electrode and a drain electrode of the electric leakage test structure; the substrate of the transistor array is connected with a body electrode serving as a leakage test structure through a connecting hole and a first metal wire; and obtaining a grid electrode, a source electrode, a drain electrode and a body electrode of the electric leakage test structure, and completing the generation of the electric leakage test structure. By means of the application, it is achieved that the entire test structure is first layer metal-measurable.

Description

A leakage test structure of a transistor array and a generation method and storage medium thereof

Technical Field

The present application relates to the field of chip testing technology, and in particular to a leakage test structure of a transistor array, a generation method thereof, and a storage medium.

Background Art

The main semiconductor device of integrated circuits, especially ultra-large-scale integrated circuits, is the metal-oxide-semiconductor field-effect transistor (MOS transistor). With the continuous development of integrated circuit manufacturing technology, the technical nodes of semiconductor devices are constantly reduced, and the geometric size of transistors continues to shrink in accordance with Moore's Law. When the size of transistors is reduced to a certain extent, various secondary effects caused by the physical limits of transistors appear one after another, and it becomes increasingly difficult to scale down the characteristic size of transistors. Among them, in the field of transistor and semiconductor manufacturing, the continuous reduction in the thickness of the traditional gate dielectric layer causes large transistor leakage current.

At present, for low-power integrated chips, the leakage current of transistors has become a critical parameter, which directly affects the static power consumption of low-power integrated chips. As the integration of integrated chips is further improved, the power consumption of integrated chips will be further reduced, and the leakage current value of transistors will also tend to be smaller, making the leakage current of transistors more difficult to detect.

With the advancement of technology, the leakage current of a single transistor is getting smaller and smaller. The traditional method of testing the leakage current of a single transistor is also difficult to accurately measure the leakage current. Now most people use the method of testing the total value of the leakage current of transistor arrays of the same specifications, and then taking the average value to get the leakage current of a single transistor. This method is called Transistor Array Leakage.

In the existing transistor array leakage test structure, as shown in Figure 1, the parallel connection of the gate, source and drain all adopts a comb-shaped connection, the source and drain are vertical, and the gate is horizontal. This results in the parallel connection of the source and drain requiring the use of a second layer of metal and a through hole connecting the first and second layers of metal. The leakage test structure of the entire transistor array is a problem that can be measured by the second layer of metal.

Summary of the invention

In this embodiment, a leakage test structure of a transistor array and a generation method and storage medium thereof are provided to solve the problem in the prior art that the parallel connection of the source and the drain requires a second layer of metal and a through hole connecting the first and second layers of metal, and the leakage test structure of the entire transistor array is testable by the second layer of metal.

In a first aspect, a method for generating a leakage test structure of a transistor array is provided in this embodiment, the method comprising:

obtaining a transistor array;

Laying three transverse metal wires on each row of transistors in the transistor array, wherein the three transverse metal wires are respectively connected to the gate, source and drain of the transistors in the same row through connection holes;

Connecting two adjacent rows of transverse metal wires connecting the same electrodes of transistors through longitudinal metal wires, and alternately laying the longitudinal metal wires on both sides of the transistor array to generate three metal windings of serpentine routing;

The three metal windings are used as the gate, source and drain of the leakage test structure respectively;

Connecting the substrate of the transistor array to the body of the leakage test structure through a connection hole and a first metal wire;

The gate, source, drain and body of the leakage test structure are obtained to complete the generation of the leakage test structure.

In some embodiments, the acquisition transistor array comprises:

Get the map;

A plurality of target transistors to be tested are screened out in the layout to obtain the transistor array.

In some of the embodiments, the target transistor is a single-transistor transistor.

In some embodiments, the transverse metal lines are parallel to each other, and the longitudinal metal lines are parallel to each other or on the same straight line.

In some embodiments, the three metal windings for generating the serpentine routing include:

The metal wiring connects the gate, source or drain of the transistor array in parallel.

In some of the embodiments, the transverse metal lines, the longitudinal metal lines, the metal windings of the serpentine routing and the first metal lines are all metal lines of the same layer.

In some of the embodiments, the method for generating a leakage test structure of a transistor array further includes:

The gate, source, drain and body of the leakage test structure are connected to the test pads respectively.

In some of the embodiments, the transistor electrodes connected to the three lateral metal wires in two adjacent rows are arranged in the opposite order from top to bottom.

In some of the embodiments, the acquisition transistor array further comprises:

The plurality of target transistors are arranged in a matrix to form a matrix of m columns and n rows, thereby obtaining the transistor array; wherein m and n are integers greater than 1.

In some of the embodiments, screening out a plurality of target transistors to be tested in the layout includes:

The target transistors have the same doping type.

In some embodiments, the connection hole includes a contact hole and/or a through hole.

In a second aspect, a leakage test structure of a transistor array is provided in this embodiment, and the leakage test structure of the transistor array is a leakage test structure generated based on the method for generating a leakage test structure of a transistor array according to the first aspect.

According to a third aspect, a computer-readable storage medium is provided in the present embodiment, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the method for generating a leakage test structure of a transistor array according to the first aspect are implemented.

Compared with the prior art, the generation method and test structure of a leakage test structure of a transistor array provided in this embodiment connects the horizontal metal wires of the same electrodes of two adjacent rows of transistors through the vertical metal wires, and alternately lays the vertical metal wires on both sides of the transistor array to generate three metal windings of serpentine routing, and uses the three metal windings as the gate, source and drain of the leakage test structure respectively, and connects the substrate of the transistor array through the connection hole and the first metal wire as the body of the leakage test structure to obtain the gate, source, drain and body of the leakage test structure, and completes the generation of the leakage test structure, so that the entire test structure can be tested by the first layer of metal. The generation method and test structure of a leakage test structure of a transistor array provided in this embodiment creatively utilize the characteristics of the snake structure, and can complete the construction of the Transistor Array Leakage test structure under the premise of using only the first layer of metal. Compared with the structure with the second metal layer being testable, the problem in the prior art that the parallel connection of the source and the drain requires the use of a second metal layer and a through hole connecting the first and second metal layers is solved, thereby reducing the additional wiring resistance caused by the through hole and saving at least two layers of metal masks; at the same time, the fact that the first metal layer can be tested also allows the entire test structure to be tested earlier, shortening the test cycle.

Details of one or more embodiments of the present application are set forth in the following drawings and description to make other features, objects, and advantages of the present application more readily apparent.

BRIEF DESCRIPTION OF THE DRAWINGS

The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

FIG1 is a transistor array leakage test structure in the prior art;

FIG2 is a flow chart of a method for generating a leakage test structure of a transistor array according to an embodiment of the present application;

FIG3 is a schematic diagram of a transistor according to an embodiment of the present application;

FIG4 is a schematic diagram of a transistor array according to an embodiment of the present application;

FIG5 is a schematic diagram of a winding process of a leakage test structure according to an embodiment of the present application;

FIG6 is a schematic diagram of a winding process of a leakage test structure according to an embodiment of the present application;

7 is a schematic diagram of a winding process of a leakage test structure according to an embodiment of the present application;

FIG8 is a schematic diagram of a leakage test structure of a serpentine line according to an embodiment of the present application;

FIG9 is a schematic diagram of the serpentine routing of the M1 metal layer of the leakage test structure;

FIG. 10 is a structural block diagram of a device for generating a leakage test structure of a transistor array according to an embodiment of the present application.

DETAILED DESCRIPTION

In order to more clearly understand the purpose, technical solutions and advantages of the present application, the present application is described and illustrated below in conjunction with the accompanying drawings and embodiments.

Unless otherwise defined, the technical terms or scientific terms involved in this application shall have the general meaning understood by people with general skills in the technical field to which this application belongs. The words "one", "a", "the", "these" and the like in this application do not indicate a quantitative limitation, and they may be singular or plural. The terms "include", "comprise", "have" and any variants thereof involved in this application are intended to cover non-exclusive inclusions; for example, a process, method and system, product or device comprising a series of steps or modules (units) is not limited to the listed steps or modules (units), but may include unlisted steps or modules (units), or may include other steps or modules (units) inherent to these processes, methods, products or devices. The words "connect", "connected", "coupled" and the like involved in this application are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The "multiple" involved in this application refers to two or more. "And/or" describes the association relationship of associated objects, indicating that there may be three relationships, for example, "A and/or B" may mean: A exists alone, A and B exist at the same time, and B exists alone. Generally, the character "/" indicates that the objects associated with each other are in an "or" relationship. The terms "first", "second", "third", etc. in this application are only used to distinguish similar objects and do not represent a specific ordering of the objects.

This embodiment provides a method for generating a leakage test structure of a transistor array. FIG2 is a flow chart of a method for generating a leakage test structure of a transistor array according to an embodiment of the present application. As shown in FIG2, the method includes the following steps:

Step S210, obtaining a transistor array.

Specifically, the transistor array includes a plurality of transistors, and the plurality of transistors are arranged in rows and columns to form a transistor array. The number of transistors in each row of the transistor array may be the same or different, or the number of transistors in each column of the transistor array may be the same or different. For example, the transistor array includes L transistors, with a total of m rows and n columns, the first row has _N1 transistors, the second row has _N2 transistors, ..., the m-1th row has _Nm-1 transistors, and the mth row has _Nm transistors, wherein L= _N1 + _N2 +...+Nm _-1 + _Nm , _N1 , _N2 , ..., _Nm-1 , _Nm may be the same or different, that is, the number of transistors in each row of the transistor array may be the same or different. As shown in FIG3, each transistor includes an active region and a gate, the active region is distributed on both sides of the gate, and the active region may be a drain or a source. As shown in FIG4 , the transistor array has 3 rows and 6 columns, with 6 transistors in each row. It should be noted that the number of transistors in each row may also be different. For example, the number of transistors in 3 rows may be 4, 5, and 6 respectively. Another example is that the number of transistors in 3 rows may be 5, 6, and 2 respectively. No specific limitation is made here.

Step S220 , laying three transverse metal wires on each row of transistors in the transistor array, and the three transverse metal wires are respectively connected to the gate, source and drain of the transistors in the same row through connection holes.

Specifically, three horizontal metal wires are laid on each row of transistors in the transistor array, and the three horizontal metal wires are respectively connected to the gate, source and drain of the transistors in the same row through connection holes. Depending on the process, the connection hole here can be a contact hole or a through hole. The three horizontal metal wires here can be arranged in parallel. As shown in FIG5, taking a row of transistors as an example, three horizontal metal wires M1 are respectively connected to the source, gate and drain corresponding to the transistors in the same row through contact holes CT, and the three horizontal metal wires M1 are the first layer of metal wires (M1 layer). The same treatment is performed on the transistors in each row. As shown in FIG6, taking the transistor array formed by two rows of transistors as an example, the three horizontal metal wires M1 are respectively connected to the gate G, source S and drain D of the transistors in the same row through contact holes CT, and the three horizontal metal wires M1 are the first layer of metal wires.

Step S230 , connecting two adjacent rows of transverse metal wires connecting the same electrodes of transistors through longitudinal metal wires, and alternately laying longitudinal metal wires on both sides of the transistor array to generate three serpentine metal windings.

Specifically, the horizontal metal wires of the same electrodes of two adjacent rows of transistors are connected through the vertical metal wires, and the vertical metal wires are alternately laid on both sides of the transistor array to generate three metal windings of the serpentine routing. Here, the vertical metal wires are alternately laid on both sides of the transistor array, which can be understood as the vertical metal wires used to connect the horizontal metal wires of the first row of transistors and the second row of transistors are laid on the left side of the transistor array, the vertical metal wires used to connect the horizontal metal wires of the second row of transistors and the third row of transistors are laid on the right side of the transistor array, and the vertical metal wires used to connect the horizontal metal wires of the third row of transistors and the fourth row of transistors are laid on the left side of the transistor array, and so on, thereby generating three metal windings of the serpentine routing. As shown in FIG. 7, a transistor array formed by two rows of transistors is used as an example for explanation, and the vertical metal wire M1 of the horizontal metal wire M1 used to connect the first row of transistors and the second row of transistors is laid on the right side of the transistor array, and the horizontal metal wire M1 and the vertical metal wire M1 form three metal windings of the serpentine routing. As shown in FIG8 , a transistor array formed by four rows of transistors is used as an example for explanation. The longitudinal metal line M1 used to connect the transverse metal line M1 of the first row of transistors and the second row of transistors is laid on the right side of the transistor array, the longitudinal metal line M1 used to connect the transverse metal line M1 of the second row of transistors and the third row of transistors is laid on the left side of the transistor array, and the longitudinal metal line M1 used to connect the transverse metal line M1 of the third row of transistors and the fourth row of transistors is laid on the right side of the transistor array, thereby forming the leakage test structure of the serpentine routing shown in FIG8 . The leakage test structure of the serpentine routing in FIG8 utilizes the characteristics of the snake structure, and can complete the construction of the Transistor Array Leakage test structure under the premise of using only the first layer of metal. Compared with the structure in the prior art in FIG1 where the second layer of metal can be measured, the parallel connection of the source and the drain in the prior art requires the use of the second layer of metal and the through hole connecting the first and second layers of metal, reduces the additional routing resistance caused by the through hole, and saves at least two layers of metal mask; at the same time, the first layer of metal can be measured, which can also allow the entire test structure to be tested earlier, shortening the test cycle. FIG. 9 is a schematic diagram of the serpentine routing of the M1 metal layer of the leakage test structure.

Step S240, obtaining the gate, source, and drain of the leakage test structure.

Specifically, the three metal windings of the serpentine routing respectively determine the gate, source and drain of the leakage test structure. As shown in FIG8 , the three metal windings of the serpentine routing respectively serve as the gate G, source S and drain D of the leakage test structure.

Step S250: Connect the substrate of the transistor array through the connection hole and the first metal wire to form a body electrode of the leakage test structure.

Specifically, the connection hole here can be a contact hole or a through hole. The horizontal metal wire, the vertical metal wire, the metal winding wire of the serpentine routing and the first metal wire here are all metal wires of the same layer. Further, the horizontal metal wire, the vertical metal wire, the metal winding wire of the serpentine routing and the first metal wire are all first-layer metal wires.

Step S260, obtaining the gate, source, drain and body of the leakage test structure, and completing the generation of the leakage test structure.

Specifically, the gate, source, drain and body of the leakage test structure are obtained to complete the generation of the leakage test structure. Subsequently, the gate, source, drain and body can be connected to corresponding pads (PAD) for testing, and the leakage test of the transistor array can be performed according to the generated leakage test structure.

In this embodiment, the horizontal metal wires connecting the same electrodes of two adjacent rows of transistors are connected through the vertical metal wires, and the vertical metal wires are alternately laid on both sides of the transistor array to generate three metal windings of the serpentine routing, and the three metal windings are respectively used as the gate, source and drain of the leakage test structure, and the substrate of the transistor array is connected through the connection hole and the first metal wire as the body of the leakage test structure to obtain the gate, source, drain and body of the leakage test structure, and the generation of the leakage test structure is completed, so that the entire test structure is testable by the first layer of metal, which solves the problem that the parallel connection of the source and drain requires the use of the second layer of metal and the through hole connecting the first and second layers of metal in the prior art, and the entire test structure is testable by the second layer of metal, which wastes circuit resources. In this embodiment, contact holes, back-end metal routings and/or metal through holes that meet the design rules are quickly generated while retaining the front-end design of the layout, and together with the front-end circuit, they form a transistor array leakage (Transistor Array Leakage M1 testable) test circuit that is testable by the first layer of metal.

In some of the embodiments, step S210, obtaining a transistor array, includes: obtaining a layout; screening out a plurality of target transistors to be tested in the layout to obtain a transistor array.

Specifically, a layout is obtained, and according to the test requirements, a plurality of target transistors to be tested are screened out in the layout, and the plurality of target transistors are arranged to obtain a transistor array.

In some of the embodiments, the target transistor is a single-tube structure transistor. However, in different application scenarios, the transistor array may also be a plurality of transistors connected in parallel or a plurality of transistors connected in series, or even a transistor array may have at least two types of single-tube structure transistors, a plurality of transistors connected in parallel, and/or a plurality of transistors connected in series, which are not specifically limited in this application.

Specifically, a layout is obtained, a plurality of single-tube structure transistors to be tested are screened out in the layout, and the plurality of single-tube structure transistors are arranged to obtain a transistor array.

In some of the embodiments, the transverse metal lines are parallel to each other, and the longitudinal metal lines are parallel to each other or on the same straight line.

Specifically, referring to FIG. 7, FIG. 8 and FIG. 9, all the transverse metal lines M1 are parallel to each other, the three longitudinal metal lines M1 connecting the three transverse metal lines M1 of the transistors in two adjacent rows are parallel to each other, and the longitudinal metal lines M1 of the same electrode laid on the same side of the transistor array are on the same straight line. For example, referring to FIG. 8, the three transverse metal lines M1 connecting the gate G, source S and drain D of the transistor are parallel to each other, and the three longitudinal metal lines M1 connecting the three transverse metal lines M1 of the first row of transistors and the second row of transistors are parallel to each other. The transverse metal lines connecting the gates of the transistors in the same row are recorded as gate transverse metal lines, the transverse metal lines connecting the drains of the transistors in the same row are recorded as drain transverse metal lines, and the transverse metal lines connecting the sources of the transistors in the same row are recorded as source transverse metal lines. The longitudinal metal line M1 for connecting the gate transverse metal lines of the first row of transistors and the second row of transistors and the longitudinal metal line M1 for connecting the gate transverse metal lines of the third row of transistors and the fourth row of transistors are on the same straight line, the longitudinal metal line M1 for connecting the drain transverse metal lines of the first row of transistors and the second row of transistors and the longitudinal metal line M1 for connecting the drain transverse metal lines of the third row of transistors and the fourth row of transistors are on the same straight line, and the longitudinal metal line M1 for connecting the source transverse metal lines of the first row of transistors and the second row of transistors and the longitudinal metal line M1 for connecting the source transverse metal lines of the third row of transistors and the fourth row of transistors are on the same straight line.

In some of the embodiments, in step S230, after three metal windings of the serpentine routing are generated, the gates, sources or drains of the transistor array are connected in parallel.

Specifically, the metal wiring connects the gate, source or drain of the transistor array in parallel to generate three metal wirings of serpentine routing.

In some of the embodiments, the transverse metal line, the longitudinal metal line, the metal winding of the serpentine routing, and the first metal line are all metal lines of the same layer.

Specifically, the horizontal metal wires, the vertical metal wires, the metal windings of the serpentine routing and the first metal wires are all metal wires of the same layer, such as the first layer metal wire M1. This makes the entire test structure testable by the first layer metal, solving the problem in the prior art that the parallel connection of the source and the drain requires the use of the second layer metal and the through hole connecting the first and second layers of metal, and the entire test structure is testable by the second layer metal, wasting circuit resources.

In some of the embodiments, the method for generating the leakage test structure of the transistor array further includes: connecting the gate, source, drain and body of the leakage test structure to the test pads respectively.

Specifically, the gate, source, drain and body of the leakage test structure are connected to the test pads respectively to perform leakage test on the transistor array.

In some of the embodiments, the transistor electrodes connected to the three lateral metal wires in two adjacent rows are arranged in the opposite order from top to bottom.

Specifically, the longitudinal metal wires are alternately laid at the left and right ends of the transverse metal wires, and the transverse metal wires connecting the same electrode of the upper and lower rows of transistors are connected. Since the transverse metal wires connecting the three electrodes on the upper and lower rows of transistors are arranged in opposite order, the three longitudinal metal wires connecting the upper and lower rows are also parallel to each other. Three complete metal windings of mutually parallel serpentine lines are obtained, and the three electrodes on all transistors are connected in parallel. Referring to FIG8, the transistor electrodes connected by the three transverse metal wires of the first row of transistors are arranged in upper and lower order as the source, the drain and the gate, respectively; the transistor electrodes connected by the three transverse metal wires of the second row of transistors are arranged in upper and lower order as the gate, the drain and the source, respectively; the transistor electrodes connected by the three transverse metal wires of the third row of transistors are arranged in upper and lower order as the source, the drain and the gate, respectively; and the transistor electrodes connected by the three transverse metal wires of the fourth row of transistors are arranged in upper and lower order as the gate, the drain and the source, respectively. It should be noted that the upper and lower arrangements of the transistor electrodes connected by the three horizontal metal wires of each row of transistors here can also be drain, source and gate, or source, gate and drain. No specific limitation is made here. It is only necessary that the upper and lower arrangements of the transistor electrodes connected by the three horizontal metal wires in two adjacent rows are opposite. When the upper and lower arrangements of the transistor electrodes connected by the three horizontal metal wires in two adjacent rows are opposite, three complete metal windings of mutually parallel serpentine lines can be formed, and the three electrodes on all transistors are connected in parallel, so that the entire test structure can be measured by the first layer of metal, which solves the problem in the prior art that the parallel connection of the source and the drain requires the use of the second layer of metal and the through-holes connecting the first and second layers of metal, and the entire test structure can be measured by the second layer of metal, thereby wasting circuit resources.

In some of the embodiments, obtaining a transistor array further includes: arranging a plurality of target transistors in a matrix to form a matrix of m columns and n rows to obtain a transistor array; wherein m and n are integers greater than 1.

Specifically, a plurality of target transistors are arranged in a matrix to form a matrix of m columns and n rows, thereby obtaining a transistor array, wherein the number of transistors in each row of the transistor array is the same, and the number of transistors in each column of the transistor array is also the same.

In some embodiments, multiple target transistors to be tested are screened out in the layout, including: the target transistors have the same doping type. In this embodiment, since all transistors have the same doping type, they can share a substrate and be connected with a first metal line and a contact hole.

Specifically, since all transistors have the same doping type, they can share a substrate and be connected using the first metal wire M1 and the contact hole CT. Finally, the metal windings of the three serpentine traces are used as the gate, source, and drain, respectively, and the shared substrate is connected to the corresponding test pads for testing.

The present embodiment provides a leakage test structure of a transistor array. The leakage test structure of the transistor array is a leakage test structure generated based on the method for generating the leakage test structure of the transistor array in the foregoing embodiment.

This embodiment also provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the steps of the method for generating a leakage test structure of the transistor array are implemented.

It should be noted that the steps shown in the above process or the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

In this embodiment, a device for generating a leakage test structure of a transistor array is also provided, and the device is used to implement the above-mentioned embodiments and preferred implementation modes, and the descriptions that have been made will not be repeated. The terms "module", "unit", "sub-unit", etc. used below can implement a combination of software and/or hardware of predetermined functions. Although the devices described in the following embodiments are preferably implemented in software, the implementation of hardware, or a combination of software and hardware, is also possible and conceivable.

FIG. 10 is a structural block diagram of a device for generating a leakage test structure of a transistor array according to an embodiment of the present application. As shown in FIG. 10 , the device includes:

A first acquisition module 10, used for acquiring a transistor array;

A laying module 20 is used to lay three transverse metal wires on each row of transistors in the transistor array, and the three transverse metal wires are respectively connected to the gate, source and drain of the transistors in the same row through connection holes;

The first generating module 30 is used to connect the transverse metal wires of two adjacent rows connecting the same electrodes of the transistors through the longitudinal metal wires, and alternately lay the longitudinal metal wires on both sides of the transistor array to generate three metal windings of the serpentine routing;

The determination module 40 is used to respectively use the three metal windings as the gate, source and drain of the leakage test structure; and connect the substrate of the transistor array through the connection hole and the first metal wire as the body of the leakage test structure;

The second generation module 50 is used to obtain the gate, source, drain and body of the leakage test structure to complete the generation of the leakage test structure.

It should be noted that the above modules can be functional modules or program modules, and can be implemented by software or hardware. For modules implemented by hardware, the above modules can be located in the same processor; or the above modules can be located in different processors in any combination.

In this embodiment, an electronic device is further provided, including a memory and a processor, wherein a computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

Optionally, the electronic device may further include a transmission device and an input/output device, wherein the transmission device is connected to the processor, and the input/output device is connected to the processor.

Optionally, in this embodiment, the processor may be configured to perform the following steps through a computer program:

S1, obtain transistor array;

S2, laying three transverse metal wires on each row of transistors in the transistor array, wherein the three transverse metal wires are respectively connected to the gate, source and drain of the transistors in the same row through connection holes;

S3, connecting two adjacent rows of transverse metal wires connecting the same electrodes of transistors through longitudinal metal wires, and alternately laying the longitudinal metal wires on both sides of the transistor array to generate three metal windings of serpentine routing;

S4, using the three metal windings as the gate, source and drain of the leakage test structure respectively;

S5, connecting the substrate of the transistor array through a connection hole and a first metal wire to serve as a body electrode of the leakage test structure;

S6, obtaining the gate, source, drain and body of the leakage test structure, and completing the generation of the leakage test structure.

It should be noted that the specific examples in this embodiment can refer to the examples described in the above embodiments and optional implementation modes, and will not be repeated in this embodiment.

In addition, in combination with the method for generating a leakage test structure of a transistor array provided in the above embodiment, a storage medium can also be provided in this embodiment to implement the method. The storage medium stores a computer program; when the computer program is executed by a processor, the method for generating a leakage test structure of a transistor array in any of the above embodiments is implemented.

It should be understood that the specific embodiments described herein are only used to explain the application, rather than to limit it. Based on the embodiments provided in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the protection scope of this application.

Obviously, the drawings are only some examples or embodiments of the present application. For ordinary technicians in the field, the present application can also be applied to other similar situations based on these drawings without creative work. In addition, it is understandable that although the work done in this development process may be complicated and lengthy, for ordinary technicians in the field, certain changes in design, manufacturing or production based on the technical content disclosed in this application are only conventional technical means and should not be regarded as insufficient content disclosed in this application.

The term "embodiment" in this application refers to a specific feature, structure or characteristic described in conjunction with the embodiment that can be included in at least one embodiment of the present application. The appearance of this phrase in various locations in the specification does not necessarily mean the same embodiment, nor does it mean that it is mutually exclusive with other embodiments and is independent or optional. It is clearly or implicitly understood by those of ordinary skill in the art that the embodiments described in this application can be combined with other embodiments without conflict.

The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of patent protection. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the scope of protection of the present application. Therefore, the scope of protection of the present application shall be subject to the attached claims.

Claims (10)

1. A method for generating a leakage test structure for a transistor array, the method comprising:

Acquiring a transistor array;

Three transverse metal wires are paved on each row of transistors of the transistor array and are respectively connected with the grid electrode, the source electrode and the drain electrode of the transistors in the same row through connecting holes; the three transverse metal wires of two adjacent rows are connected with the upper and lower arrangement sequences of the transistor electrodes in opposite directions;

connecting two adjacent rows of transverse metal wires connected with the same electrode of the transistor through longitudinal metal wires, and alternately paving the longitudinal metal wires on two sides of the transistor array to generate three metal windings of a serpentine wiring;

The three metal wires are respectively used as a grid electrode, a source electrode and a drain electrode of the electric leakage test structure;

The substrate of the transistor array is connected with a body electrode serving as the electric leakage test structure through a connecting hole and a first metal wire; the transverse metal wire, the longitudinal metal wire, the metal winding of the serpentine wiring and the first metal wire are all metal wires in the same layer;

and obtaining a grid electrode, a source electrode, a drain electrode and a body electrode of the electric leakage test structure, and completing the generation of the electric leakage test structure.

2. The method for generating a leakage test structure for a transistor array according to claim 1, wherein the acquiring the transistor array comprises:

Obtaining a layout;

and screening a plurality of target transistors to be tested from the layout to obtain the transistor array.

3. The method of generating a leakage test structure for a transistor array according to claim 2, wherein the target transistor is a transistor of a single-tube structure.

4. The method of claim 1, wherein the lateral metal lines are parallel to each other and the longitudinal metal lines are parallel to each other or on the same line.

5. The method of claim 1, wherein the generating three metal windings of the serpentine trace comprises:

The metal wire connects the gate, source or drain of the transistor array in parallel.

6. The method of generating a leakage test structure for a transistor array according to claim 1, further comprising:

And connecting the grid electrode, the source electrode, the drain electrode and the body electrode of the electric leakage test structure to the test bonding pads respectively.

7. The method for generating a leakage test structure for a transistor array according to claim 2, wherein the acquiring the transistor array further comprises:

Arranging the target transistors in a matrix to form a matrix of m columns and n rows to obtain the transistor array; wherein m and n are integers greater than 1.

8. The method for generating a leakage test structure for a transistor array according to claim 2, wherein screening a plurality of target transistors to be tested in the layout comprises:

the doping types of the target transistors are the same.

9. A leakage test structure of a transistor array, wherein the leakage test structure of the transistor array is a generated leakage test structure based on the method for generating a leakage test structure of a transistor array according to any one of claims 1 to 8.

10. A computer readable storage medium having stored thereon a computer program, characterized in that the computer program when executed by a processor realizes the steps of the method of generating a leakage test structure of a transistor array according to any of claims 1 to 8.