CN118412291A - Semiconductor device and method of forming the same - Google Patents

Abstract

Embodiments provide a device structure and a method of forming a device structure that includes a fill structure to capture solder material within an opening of the fill structure. The metal posts of one device may penetrate the non-conductive film and contact the solder areas of the other device. No separate underfill is required. Embodiments of the present application also relate to semiconductor devices and methods of forming the same.

Description

Semiconductor device and method of forming the same

Technical Field

Embodiments of the present application relate to semiconductor devices and methods of forming the same.

Background

The semiconductor industry has experienced a rapid growth due to the ever-increasing integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). To a large extent, the improvement in integration density comes from the iterative reduction of minimum feature sizes, which allows more components to be integrated into a given area. As the demand for shrinking electronic devices increases, there is a need for smaller and more innovative semiconductor die packaging techniques.

Disclosure of Invention

Some embodiments of the present application provide a method of forming a semiconductor device, comprising: forming an under bump structure on a workpiece, the under bump structure being electrically coupled to a metal feature embedded in the workpiece; forming a solder bump on the under bump structure to form a solder structure; depositing a first support layer over and laterally surrounding the solder structure; planarizing the first support layer such that an upper surface of the solder structure is flush with an upper surface of the first support layer; depositing a non-conductive film over the first support layer and over the solder structure; and dividing the workpiece to release the die.

Other embodiments of the present application provide a method of forming a semiconductor device, comprising: providing a first workpiece comprising a metal post protruding from an upper surface of the first workpiece; aligning a eutectic connection of the die with the metal pillar, the die including a eutectic connection electrically coupled to a metal part of the die, a first film laterally surrounding the eutectic connection, and a second film disposed on the first film and on the eutectic connection; pressing the die to the first workpiece, the metal posts penetrating the second film and contacting the eutectic connection; and reflowing the eutectic connection to electrically and physically couple the die to the first workpiece.

Still further embodiments of the present application provide a semiconductor device including: a first workpiece comprising a metal post extending perpendicularly from an upper surface of the first workpiece; a second workpiece, which may include a metal pad along a lower surface of the second workpiece; a eutectic connection extending between and coupling the metal post and the metal pad; a first film abutting the lower surface of the second workpiece, the first film laterally sealing at least portions of the eutectic connection and the metal pad; and a second membrane adjoining the upper surface of the first workpiece and the lower surface of the first membrane, the second membrane laterally sealing the metal posts.

Drawings

The various aspects of the embodiments of the present disclosure are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that the various components are not drawn to scale according to standard practice in the industry. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1-10 illustrate intermediate stages in the formation of a package assembly having a fill structure and a non-conductive film according to some embodiments.

Fig. 11-18 illustrate intermediate stages in the formation of a package having a metal pillar of a package assembly surrounded by a non-conductive film that meets a solder region surrounded by a fill structure of another package assembly, according to some embodiments.

Fig. 19-20 illustrate other configurations of packages having metal posts of a package assembly surrounded by a non-conductive film that interfaces with solder regions surrounded by fill structures of another package assembly, according to some embodiments.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure embodiments. These are, of course, merely examples and are not intended to limit the disclosed embodiments. For example, in the following description, forming a first component over or on a second component may include embodiments in which the first component and the second component are formed in direct contact, and may also include embodiments in which additional components may be formed between the first component and the second component, such that the first component and the second component may not be in direct contact. Further, embodiments of the present disclosure may repeat reference numerals and/or characters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as "under …," "under …," "lower," "above …," "upper," and the like, may be used herein for ease of description to describe one element or component's relationship to another element(s) or component(s) as illustrated. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

In a System On Integrated Circuit (SOIC) device, integrated circuit devices (which may also be referred to as dies or chips) are attached together into a single system device package. Such SOIC devices may be formed by, for example, bonding die to a wafer in a die-on-wafer bonding process, and then dicing the wafer to form SOIC devices. One way to achieve this is to form solder connections extending between two metal connections, one on the die and one on the wafer. As solder connections become smaller in size and closer to each other to achieve greater connection densities to match device densities, the risk of connection failure is also increasing. For example, one common failure is connector bridging or connector collapse. When solder reflows to join two structures together, the solder may laterally squeeze between the two structures and bridge to adjacent connectors, resulting in device failure or unreliability, or the solder may collapse and fail to make any connection. These problems may be due to too much or too little solder, warpage of the device, misalignment, or other reasons.

Embodiments alleviate the problem of connector bridging or connector collapse by confining or sealing the solder to a particular joint window. The joint window encourages solder to stay within the lateral extent of the metal connector to which it is attached. In addition, embodiments use a process of forming solder, which results in a more uniform solder structure. The bonding technique also provides a mechanism for the metal connector to penetrate the solder prior to reflow, thereby significantly increasing the likelihood of good bonding. In addition, a compressible film is provided over the solder to effectively extend the solder window to the metal connection to which the solder is joined and to help reduce oxidation at the solder joint. In some embodiments, solder may be reflowed into the compressible film to surround the metal connection to provide an enlarged joint.

Fig. 1 is a cross-sectional view of a wafer 100, with a die area 105 defined within the wafer 100. In a subsequent process, die region 105 may be singulated into a plurality of integrated circuit dies. The type of die formed in each die region 105 is not limited. For example, die area 105 may be partitioned into logic die (e.g., central Processing Unit (CPU), graphics Processing Unit (GPU), system on a chip (SoC), application Processor (AP), microcontroller, etc.), memory die (e.g., dynamic Random Access Memory (DRAM) die, static Random Access Memory (SRAM) die, etc.), power management die (e.g., power Management Integrated Circuit (PMIC) die), radio Frequency (RF) die, sensor die, microelectromechanical system (MEMS) die, signal processing die (e.g., digital Signal Processing (DSP) die), front end die (e.g., analog Front End (AFE) die), etc., or a combination thereof.

An integrated circuit die may be formed in each die region 105 according to the applicable manufacturing process used to form the integrated circuit. For example, a die formed in die region 105 includes a semiconductor substrate 110, such as doped or undoped silicon, or an active layer of a semiconductor-on-insulator (SOI) substrate. Semiconductor substrate 110 may include other semiconductor materials such as germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor comprising SiGe, gaAsP, alInAs, alGaAs, gaInAs, gaInP and/or GaInAsP; or a combination thereof. Other substrates, such as multi-layer or gradient substrates, may also be used. The semiconductor substrate 110 has an active surface (e.g., the surface facing upward in fig. 1), sometimes referred to as the front side, and a passive surface (e.g., the surface facing downward in fig. 1), sometimes referred to as the back side.

The device is disposed at the active surface of the semiconductor substrate 110 in the device region 115. The device region 115 may include active devices (e.g., transistors, diodes, etc.), capacitors, resistors, etc. For example, the device region 115 may include a transistor including a gate structure and source/drain regions, wherein the gate structure is located on the channel region and the source/drain regions are adjacent to the channel region.

The interconnect 120 is disposed over an active surface of the semiconductor substrate 110. Interconnect 120 includes one or more dielectric layers, such as an inter-layer dielectric (ILD) or an inter-metal dielectric (IMD), in which one or more metallization patterns are disposed. Conductive vias may be used to connect the device regions 115 to the metallization patterns and to connect the metallization patterns to each other. The dielectric layer may be formed of a material such as phosphosilicate glass (PSG), borosilicate glass (BSG), boron doped phosphosilicate glass (BPSG), undoped Silicate Glass (USG), etc., which may be formed by a deposition process such as Chemical Vapor Deposition (CVD), atomic Layer Deposition (ALD), etc. Conductive vias may extend through the dielectric layer to electrically and physically couple contacts of devices in the device region 115. In some embodiments, the dielectric layer may be a low-k dielectric layer. The metallization pattern and vias may be formed in the dielectric layer 64 by a damascene process, such as a single damascene process, a dual damascene process, or the like. The metallization pattern and the conductive vias may be formed of suitable conductive materials such as copper, tungsten, aluminum, silver, gold, combinations thereof, and the like.

One or more passivation layers 122 are disposed on the interconnect structure 120. Passivation layer 122 may be formed of one or more suitable dielectric materials such as silicon oxynitride, silicon nitride, low-k dielectrics such as carbon doped oxides, very low-k dielectrics such as porous carbon doped silicon oxides, polymers such as polyimides, soldermasks, polybenzoxazoles (PBO), benzocyclobutene (BCB) based polymers, molding compounds, and the like, or combinations thereof. The passivation layer 122 may be formed by Chemical Vapor Deposition (CVD), spin coating, lamination, etc., or a combination thereof. In some embodiments, passivation layer 122 comprises a silicon oxynitride layer or a silicon nitride layer.

Fig. 2-9A and 9B are enlarged views of dashed box F2 in fig. 1 and illustrate a process of forming a connection on die area 105 according to an embodiment.

In fig. 2, an opening is formed in the passivation layer 122. The passivation layer 122 may be patterned using acceptable photolithography and etching techniques to form openings that expose conductive elements electrically coupled to the interconnect 120. For example, a photomask may be formed by spin coating or other deposition over passivation layer 122, exposed to a light pattern, and developed to form a pattern therein. The passivation layer 122 may be patterned by transferring a photomask pattern to the passivation layer 122 through an etching technique to form openings. The photomask may then be removed using any acceptable technique, such as ashing techniques.

In fig. 3, an Under Bump Metal (UBM) 124 is formed in the opening of the passivation layer 122. According to some embodiments of the present disclosure, UBM 124 is formed in contact with the metallization layer of interconnect structure 120. According to an alternative embodiment, additional conductive lines and possibly dielectric layers are formed over interconnect 120 under UBM 124. For example, metal pads may be formed over interconnect structure 120, and UBM 124 may be formed over the metal pads.

As an example of forming UBM 124, a seed layer (not specifically shown) may be deposited over passivation layer 122. The seed layer may comprise a multilayer structure and may comprise a first layer of titanium, titanium nitride, tantalum nitride, etc., and a second upper layer of copper or copper alloy. The seed layer may be a single layer, for example it may be a copper layer. Physical Vapor Deposition (PVD), plasma Enhanced CVD (PECVD), atomic layer deposition, etc. may be used to form the seed layer, as well as other suitable methods. The seed layer is a conformal layer that extends into the openings of the passivation layer 122 and contacts the metal features exposed by the openings. A plating mask 126 is formed over the seed layer and patterned to form openings corresponding to UBM 124. The plating mask 126 may be formed from photoresist by spin coating and patterned using acceptable photolithographic techniques. The openings in the plating mask 126 expose portions of the seed layer in the openings of the passivation layer 122. Patterning of the plating mask 126 may include an exposure process and a development process.

A plating process is performed to form UBM 124.UBM 124 may include one or more non-solder metal layers. For example, UBM 124 may include a copper-containing layer that includes copper or a copper alloy. UBM 124 may also include a metal cap layer (shown as part of UBM 124, as applicable) over the copper-containing layer. The metal cap layer may be a nickel-containing layer, a palladium-containing layer, a gold layer, and/or the like, or a composite layer including the foregoing layers. If a metal cap layer is used, it may be formed by plating on the copper-containing layer.

In fig. 4, a plating mask 126 is left in place for forming a solder region 128 on top of UBM 124, which solder region 128 may be formed by a plating process. The solder region 128 may be formed of a eutectic material, such as a Sn-Ag alloy, a Sn-Ag-Cu alloy, or the like, and may be lead-free or lead-containing. Alternatively, the solder regions 128 may be formed by a printing process that deposits solder paste on the UBM 124. In such an embodiment, the plating mask 126 may be used as a print mask, and solder paste may wipe across the plating mask 126 in the opening. The solder paste may then be reflowed to form solder regions 128.

In fig. 5, after plating the solder regions 128, the plating mask 126 is removed by a stripping process (such as by an ashing process). The plating mask 126 is removed exposing and exposing portions of the seed layer between UBM 124. Next, the exposed portions of the seed layer previously covered by the plating mask 126 are removed by etching. The portion of the seed layer covered by UBM 124 remains unremoved. Throughout this description, the remainder of the seed layer is considered to be an integral part of UBM 124. The resulting connector structure 130 includes UBM 124 and solder region 128.

Embodiments may utilize narrow pitch sets or wide pitch sets. For the purposes of this disclosure, a narrow pitch group is considered to be a pitch P1 between adjacent UBMs of between about 5 μm and about 15 μm. The wide pitch set may include a pitch P1 of between about 20 μm and 200 μm. In the narrow pitch group, the width W1 of each connector structure may be between about 0.5 μm and about 8 μm, and the spacing S1 between connector structures may be between about 3 μm and about 9 μm.

In fig. 6, a fill film 132 is deposited over the connector structures 132 and between the connector structures 132. The filler film 132 may be any suitable insulating film, such as polyimide, solder resist, polybenzoxazole (PBO), benzocyclobutene (BCB) based polymer, or polymer of molding compound. The fill film 132 may be deposited using any suitable process, such as by CVD, spin-coating, lamination, or the like, or a combination thereof. The filler film 132 may have a young's modulus between 2.8 and 3.5GPa for BCB films or polyimide films, or between about 5 and 5.4 for molding compound films. The filler film 132 may have a coefficient of thermal expansion of between about 20 and 70ppm/°c.

In fig. 7, a planarization process is performed such that the upper surface of the fill film 132 is flush with the upper surface of the solder regions 128 of the connector structure 130 to form the fill structure 134. The planarization process may include a mechanical grinding or polishing process, or may include a Chemical Mechanical Polishing (CMP) process. The upper surface of the structure of fig. 7, including the solder regions 128 and the fill structures 134, has good planarity over process variations due to the planarization process.

The fill structure 134 provides a constrained joint window that prevents the solder region 128 from spreading beyond the fill structure 134 or reduces the amount of solder that spreads beyond the fill structure 134. The fill structure 134 allows the joint window to expand wider because the risk of joint bridging is reduced or eliminated. In some embodiments, the width of the joint window may be between about 20% and 60% of the joint spacing, such as between about 40% and 60% of the joint spacing.

In fig. 8, an optional reflow process may be performed on the solder regions 128. A reflow process may be performed to melt the solder regions 128 and form the solder regions 128 into a dome shape. Upon reflow of the solder regions 128, the upper surfaces of the solder regions 128 may pull apart at the edges and recess below the upper surfaces of the fill structures 134, and the dome or circle shape of the solder regions 128 may extend above the upper surfaces of the fill structures 134. In this way, the sidewalls of the fill structure 134 may be exposed from the solder regions 128 at the uppermost portion thereof. The optional reflow process may be a convection reflow process, a laser reflow process, or the like.

In fig. 9A and 9B, a non-conductive film (NCF) 136 is deposited over the fill structure 134 and over the solder region 128. In fig. 9A, NCF 136 is deposited over the structure of fig. 7, and in fig. 9B, NCF 136 is deposited over the structure of fig. 8. The NCF 136 is used to aid in solder reflow and deoxidizing by containing flux to aid in coupling the solder regions 128. The NCF 136 may also be used to extend the tab window to a contact that is bonded to the solder region 128, as will be explained below. The NCF 136 may be of any suitable material composition. In some embodiments, the NCF 136 may be a coating adhesive with a flux or an epoxy with a filler and a flux. The NCF 136 may be a compressible film and may be formed by any suitable process, such as by lamination, spin coating, etc., and may be formed to a thickness of between about 5 μm and about 10 μm. In fig. 9B, NCF 136 may interface with solder region 128 and the inner sidewalls of fill structure 134. The NCF 136 may have a young's modulus between about 6 and 10GPa and may have a coefficient of thermal expansion between about 25 and 40ppm/°c.

In fig. 10, a wafer 100 is singulated in a singulation process 105 s. The singulation process may include a die sawing process, an etching process, a laser dicing process, and the like, or a combination thereof. The singulation is performed along scribe lines between die regions 105. The package assemblies 150 (see fig. 11), which may be device die, package substrate, interposer, package, etc., are thus separated from one another to form discrete package assemblies 150.

In fig. 11, a package assembly 200 is provided, which may be an interposer, package substrate, package, device die, printed circuit board, or the like. The package assembly 200 includes a substrate 210 and metal posts 215 protruding from the substrate 210. The metal posts 215 are disposed at the same pitch as the connector structures 130 of the package assembly 150. In some embodiments, the metal posts 215 may protrude from the substrate 210 between about 4 μm and 12 μm. According to some embodiments, the metal pillars 215 may have a width between about 0.2 μm and 1 μm smaller than the width W1. In other embodiments, the width of the metal pillar 215 may be greater than the width W1. The metal pillars 215 may be coupled to conductive features embedded in the substrate 210, which are not specifically shown, but may include interconnect structures similar to interconnect structure 120, device regions similar to device regions 115, or other conductive features. In some embodiments, the substrate 210 may be a wafer having the plurality of device regions 205 disposed therein, which may be singulated in a subsequent singulation process. Substrate 210 may include any candidate material such as those discussed above with respect to substrate 110.

Still referring to fig. 11, the package assembly 150 is aligned with selected metal posts 215. This alignment may be accomplished by a pick and place process. Although the package assembly 150 of fig. 9B is shown, it should be understood that the package assembly 150 of fig. 9A may be used instead. Although one package assembly 150 is shown, it should be understood that additional package assemblies including additional package assemblies 150 may be used. A dashed box F12 is provided in the enlarged view of fig. 12.

In fig. 12A and 12B, the package assembly 150 is brought to the package assembly 200, and is pressed to the package assembly 200. Fig. 12A shows the package assembly 150 of fig. 9A, and fig. 12B shows the package assembly 150 of fig. 9B. When the package assembly 150 is pressed to the package assembly 200, the metal posts 215 of the package assembly 200 penetrate the NCF 136 to contact the solder regions 128 of the package assembly 150. As the metal posts 215 of the package assembly 200 penetrate the NCF 136, the NCF 136 surrounds the metal posts 215, contacting the sidewalls of the metal posts 215. Dashed boxes F13A and F13B are provided in the enlarged views of fig. 13A and 13B.

Fig. 13A and 13B provide enlarged views of the conductive structure 130. Fig. 13A shows an embodiment in which the reflow process of fig. 8 is implemented, i.e., resulting from use of the package assembly 150 of fig. 9A. Fig. 13B shows an embodiment in which the reflow process of fig. 8 is not implemented, i.e., resulting from the use of the package assembly 150 of fig. 9B. As shown in fig. 13A and 13B, the metal posts 215 are brought to the surface of the solder region 128 and surrounded by the NCF 136. Because the NCFs 136 may be compressible films, when the height of the metal posts 215 is within about 0-2 μm of the thickness of the NCFs 136, the NCFs 136 may fill the spaces between the metal posts 215 and may contact the surface of the package assembly 200.

In fig. 14A and 14B, if the height of the metal posts 215 is greater than the thickness of the NCF 136, for example, between about 2 μm and about 8 μm greater than the thickness of the NCF 136, the metal posts 215 may penetrate or penetrate to the solder region 128 a penetration distance. The penetration distance may correspond to the height of the metal posts 215 minus the thickness of the NCF 136 minus the compressible distance of the NCF 136, e.g., between about 0 μm and about 6 μm. As shown in fig. 14A and 14B, in some embodiments, when the metal posts 215 are pierced into the solder regions 128, the solder regions 128 may be pressed toward the package assembly 200 and slightly expand beyond the lateral extent of the openings in the fill structure 134 corresponding to the solder regions 128.

After aligning and pressing the package assembly 150, the bonding process may be continued by performing a Thermal Compression Bonding (TCB) process. The combination of package assembly 150 and package assembly 200 may be heated to a peak temperature of at least 217 ℃ for a time between 15 seconds and 21 seconds to reflow the solder of region 128 while applying a pressure of about 0.5 to 1.5MPa to package assembly 150 toward package assembly 200. The combination of package assembly 150 and package assembly 200 may be placed in a pressure oven and baked at a temperature between 150 ℃ and 200 ℃ and a pressure between 1atm and 6atm for a time between 1 hour and 4 hours. Because the NCF 136 may contain flux, the NCF 136 may facilitate material reflow of the solder regions 128.

Referring to fig. 15A-15F, different amplification results of the joint between the package assembly 150 and the package assembly 200 after the TCB process and the bake process are shown, according to different embodiments. The embodiments shown in fig. 15A-15F may be produced by the package assembly 150 of fig. 12A or the package assembly 150 of fig. 12B. As shown in fig. 15A, during the TCB process and bake process, the NCF 136 may move into the opening 134o in the fill structure 134 and the reflowed solder region 128 may contact the upper surface of the metal post 215. In fig. 15B, the solder region 128 has moved into the NCF 136 and, in addition to contacting the upper surface of the metal post 215, also surrounds and contacts the sidewall of the metal post 215. In fig. 15C, the metal pillars 215 penetrate into the solder regions 128, as shown in fig. 14A and 14B, and the NCF 136 can move into the opening 134o in the fill structure 134, and the reflowed solder regions 128 can surround and contact the sidewalls of the metal pillars 215 in addition to contacting the upper surfaces of the metal pillars 215. In fig. 15D, the metal posts 215 penetrate into the solder regions 128, such as shown in fig. 14A and 14B, and the solder regions 128 can move into the NCF 136, and the reflowed solder regions 128 can surround and contact the sidewalls of the metal posts 215 in addition to contacting the upper surfaces of the metal posts 215.

In fig. 15E, the upper surface of the metal post 215 is curved, according to some embodiments. As the metal posts 215 bend, they may more easily penetrate into the solder regions 128 to form a better bond. Further, in addition to contacting the upper curved surface of the metal post 215, the solder region 128 can easily move into the NCF 136 to surround more sidewalls of the metal post 215 and contact more sidewalls of the metal post 215.

In fig. 15B, 15D, and 15E, the solder regions 128 moved into the NCF 136 may extend horizontally or laterally beyond the lateral extent of the opening 134o in the fill structure 134 by a distance between 0 μm and 2 μm. However, due to the fill structures 134 and NCF 136, the solder regions 128 cannot spread to adjacent joints, which may be between 5 μm and 15 μm apart, for example, when using narrower pitches.

In fig. 15F, the metal pillars 215 are wider than the openings 134o of the fill structures 134. In such an embodiment, the metal pillars 215 stop on the surface of the fill structure 134. After the TCB process and bake process, the solder region 128 is completely contained within the opening 134o and meets the upper surface of the metal post 215. Portions of the upper surface of the metal posts 215 remain free of the material of the solder regions 128. However, these portions have interfaces with the material of the fill structure 134.

It should be appreciated that each of the joints created by the TCB process and the bake process shown in fig. 15A-15F may be found in the attachment of one of the package assemblies 150 to any combination of package assemblies 200. For example, two or more joints shown in fig. 15A-15F may be between package assembly 150 and package assembly 250. Further, the features of the joint shown in fig. 15A to 15F may be appropriately combined to form a joint, which is a combination of two or more joints shown in fig. 15A to 15F.

After bonding, the NCF 136 can support the joint and no separate underfill is required.

Fig. 16 illustrates the attachment of a plurality of package assemblies 150 to a package assembly 200 using a TCB process and a bake process to attach the package assemblies 150 to the package assembly 200. It should be appreciated that in some embodiments, the plurality of package assemblies 150 may have different configurations and functions, i.e., may be of different package types, while in other embodiments, each of the plurality of package assemblies 150 may be of the same type.

After attaching the package assembly 150 to the package assembly 200, a sealant 230 may be deposited over the package assembly 150 and between the package assemblies 150. The encapsulant 230 may be a molding compound, dielectric material, polyimide, polymer, etc., or a combination thereof. The encapsulant 230 may be deposited by any suitable process, such as by spin coating, CVD, flowable CVD, lamination, compression, and the like.

In fig. 17, the encapsulant 230 may be planarized such that an upper surface of the package assembly 150 and an upper surface of the encapsulant 230 are flush with each other, such as by a Chemical Mechanical Planarization (CMP) process. In some embodiments, planarization may continue to thin the package assembly 150.

In fig. 17, the combination of the package assembly 150 and the package assembly 200 may be divided using a division process 205s such that the package regions 205 are separated from each other. The singulation process 205s may include a die sawing process, an etching process, a laser dicing process, and the like, or a combination thereof. The dicing process 205s is performed along scribe lines between the package regions 205. The package regions 205 are thus separated from each other to form discrete package assemblies 300 (see fig. 18).

Fig. 18 shows discrete package assembly 300 separated. After singulation, the discrete package assembly 300 may be used in another package or another device structure. In some embodiments, as shown in fig. 18, the conductive connection 310 may be formed on the opposite side of the substrate 210 from the package assembly 150 before or after singulation. Forming the conductive connection 310 may include forming a contact pad 305 at a surface of the substrate 210, the contact pad 305 being electrically coupled to the metal post 215, for example, through the interconnect 315 and the via 320 of the package assembly 200. Conductive connection 310 may be formed on contact pad 305. In some embodiments, conductive connection 310 may include an optional Under Bump Metal (UBM) that extends through a passivation layer disposed on substrate 210. UBM may be formed of the same material as contact pad 305. Conductive connector 310 may include a Ball Grid Array (BGA) connector, solder ball, metal post, controlled collapse chip connection (C4) bump, micro bump, bump formed by electroless nickel-electroless palladium-immersion gold technique (ENEPIG), etc. The conductive connector 310 may include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, or the like, or a combination thereof. The conductive connection 310 may be formed by sputtering, printing, electroplating, electroless plating, CVD, or the like. In some embodiments, the conductive connection 310 includes a metal post and a metal cap layer formed on top of the metal post. The metal cap layer may include nickel, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, or the like, or combinations thereof, and may be formed by a plating process.

FIG. 19 illustrates a TCB process and a bake process according to other embodiments. Like elements have like reference numerals. In fig. 19, instead of dividing the wafer 100 into package assemblies, package assemblies 450 with metal posts (similar to package assembly 200 with metal posts 215) are brought to the wafer 100, for example, by a pick and place process. The metal posts 415 of the package assembly 450 may then be pressed through the NCF 136 to contact the solder regions 128. Similar to that described above with reference to fig. 13A, 13B, 14A, and 14B, the metal posts 415 may or may not penetrate into the solder regions 128. Then, the TCB process and the baking process as described above may be performed, resulting in a joint similar to that described and illustrated with reference to fig. 15A to 15F, except that the joint image is flipped vertically.

In fig. 20, an encapsulant 430 may be deposited to surround the package assembly 450. Encapsulant 430 can be formed using processes and materials similar to encapsulant 230. The encapsulant 430 may then be planarized and, optionally, the package assembly 450 thinned. The structure may then be singulated between the package regions 405 using a singulation process similar to singulation process 205s (see fig. 19) resulting in a packaged discrete package assembly 400.

Conductive connections 410 may be formed on contact pads 405 before or after singulation to couple vias 420 to interconnects of package assembly 150. Conductive connection 410, contact pad 405, and via 420 are similar to conductive connection 310, contact pad 305, and via 320, and may be formed using similar processes and materials.

Embodiments advantageously provide a fill structure to capture solder material within an opening of the fill structure such that the solder material does not bridge from one connector to another. Embodiments advantageously provide fill structures in fine pitch bonded packages, for example, below 10 μm. Embodiments also provide an underfill-free design by utilizing a non-conductive film over the fill structure, through which the metal posts can penetrate such that each post is advantageously surrounded by the non-conductive film for further joint support. Because the metal posts may penetrate into the solder areas prior to reflow, the resulting joint may include solder areas that may surround and contact the sidewalls of the metal posts, thereby forming a connection with less resistance.

One embodiment is a method comprising forming an under bump structure on a workpiece, the under bump structure being electrically coupled to a metal component embedded in the workpiece. The method further includes forming solder bumps on the under bump structures to form solder structures. The method further includes depositing a first support layer over and laterally around the solder structure. The method further includes planarizing the first support layer such that an upper surface of the solder structure is level with an upper surface of the first support layer. The method further includes depositing a non-conductive film over the first support layer and over the solder structure. The method further includes singulating the workpiece to release the die.

In an embodiment, forming the solder bump on the under bump structure may include forming a plating mask around the under bump structure and plating the solder bump onto the under bump structure. In an embodiment, the method may include, after planarizing the first support layer, reflowing the solder bumps. In an embodiment, the method may include aligning a die with a second workpiece, which may include metal posts extending from a first surface thereof, pressing the die to the second workpiece to bring the metal posts into contact with the solder structure, and reflowing the solder bumps. In an embodiment, the metal posts penetrate into the solder structure prior to reflowing the solder bumps. In an embodiment, during reflow of the solder bumps, solder material of the solder bumps flows into the non-conductive film. In an embodiment, an outer surface of the metal post contacts the solder structure, wherein the outer surface is rounded.

Another embodiment is a method that includes providing a first workpiece including a metal post protruding from an upper surface of the first workpiece. The method also includes aligning a eutectic connection of a die with the metal pillar, the die including a eutectic connection electrically coupled to a metal feature of the die, a first film laterally surrounding the eutectic connection, and a second film disposed on the first film and on the eutectic connection. The method further includes pressing the die to the first workpiece, the metal posts penetrating the second film and contacting the eutectic connection. The method also includes reflowing the eutectic connection to electrically and physically couple the die to the first workpiece.

In an embodiment, the second film contacts the surface of the first workpiece after reflowing the eutectic connection. In an embodiment, pressing the die to the first workpiece causes the metal posts to penetrate to the eutectic connection. In an embodiment, reflowing the eutectic connection causes material of the eutectic connection to flow into the second film and laterally around the portion of the metal pillar. In an embodiment, the second film may include an epoxy resin with a filler and a flux. In an embodiment, the metal posts have rounded tips. In an embodiment, the thickness of the second film is less than the height of the metal posts. In an embodiment, the eutectic connection is disposed on a top metal feature of the die, wherein after reflowing the eutectic connection, the eutectic connection is confined within a lateral extent of the top metal feature of the die. In an embodiment, the eutectic connection has a flat outer surface prior to pressing the die to the first workpiece.

Another embodiment is a device that includes a first workpiece that may include a metal post extending perpendicularly from an upper surface of the first workpiece. The device also includes a second workpiece, which may include a metal pad along a lower surface of the second workpiece. The device also includes a eutectic connection extending between and coupling the metal post and the metal pad. The device also includes a first film abutting the lower surface of the second workpiece, the first film laterally sealing at least portions of the eutectic connection and the metal pad. The device also includes a second membrane adjacent the upper surface of the first workpiece and the lower surface of the first membrane, the second membrane laterally sealing the metal posts.

In an embodiment, the eutectic connection extends into the second film and surrounds the outer surface of the metal post. In an embodiment, the metal posts have rounded ends embedded in the eutectic connection. In an embodiment, the metal posts penetrate into the first film.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the embodiments of the present disclosure. Those skilled in the art will appreciate that they may readily use the presently disclosed embodiments as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments presented herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the embodiments of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the embodiments of the present disclosure.

Claims (10)

1. A method of forming a semiconductor device, comprising:

forming an under bump structure on a workpiece, the under bump structure being electrically coupled to a metal feature embedded in the workpiece;

forming a solder bump on the under bump structure to form a solder structure;

Depositing a first support layer over and laterally surrounding the solder structure;

planarizing the first support layer such that an upper surface of the solder structure is flush with an upper surface of the first support layer;

Depositing a non-conductive film over the first support layer and over the solder structure; and

The workpiece is singulated to release the die.

2. The method of claim 1, wherein forming the solder bump on the under bump structure comprises:

forming a plating mask around the under bump structure; and

Plating the solder bump onto the under bump structure.

3. The method of claim 1, further comprising:

after planarizing the first support layer, the solder bumps are reflowed.

4. The method of claim 1, further comprising:

aligning the die with a second workpiece, the second workpiece comprising a metal post extending from a first surface of the second workpiece;

Pressing the die to the second workpiece to bring the metal posts into contact with the solder structure; and

The solder bumps are reflowed.

5. The method of claim 4, wherein the metal posts penetrate into the solder structure prior to reflowing the solder bumps.

6. The method of claim 4, wherein during reflow of the solder bump, solder material of the solder bump flows into the non-conductive film.

7. The method of claim 4, wherein an outer surface of the metal post contacts the solder structure, wherein the outer surface is rounded.

8. A method of forming a semiconductor device, comprising:

providing a first workpiece comprising a metal post protruding from an upper surface of the first workpiece;

aligning a eutectic connection of the die with the metal pillar, the die including a eutectic connection electrically coupled to a metal part of the die, a first film laterally surrounding the eutectic connection, and a second film disposed on the first film and on the eutectic connection;

pressing the die to the first workpiece, the metal posts penetrating the second film and contacting the eutectic connection; and

The eutectic connection is reflowed to electrically and physically couple the die to the first workpiece.

9. The method of claim 8, wherein the second film contacts a surface of the first workpiece after reflowing the eutectic connection.

10. A semiconductor device, comprising:

A first workpiece comprising a metal post extending perpendicularly from an upper surface of the first workpiece;

A second workpiece, which may include a metal pad along a lower surface of the second workpiece;

A eutectic connection extending between and coupling the metal post and the metal pad;

A first film abutting the lower surface of the second workpiece, the first film laterally sealing at least portions of the eutectic connection and the metal pad; and

A second membrane abutting an upper surface of the first workpiece and a lower surface of the first membrane, the second membrane laterally sealing the metal posts.