CN118412273A - A method for preparing a gate of a GaN HEMT device, a gate and a GaN HEMT device - Google Patents

Abstract

The invention discloses a grid preparation method of a GaN HEMT device, the grid and the GaN HEMT device, wherein the method comprises the following steps: forming a GaN epitaxial layer on a substrate, and depositing a first dielectric layer on the GaN epitaxial layer; forming a first metal layer on the first dielectric layer; carrying out open pore etching on the first metal layer and the first dielectric layer at the position where the grid metal structure is to be formed, forming a large window structure, and exposing the GaN epitaxial layer at the position; depositing a second dielectric layer of a low dielectric constant material on the first metal layer and the exposed GaN epitaxial layer; manufacturing a protective layer above the second dielectric layer in the large window structure; removing the second dielectric layer outside the coverage of the protective layer, and then removing the protective layer; manufacturing a second metal layer above the second dielectric layer; removing the second dielectric layer except the lower part of the second metal layer; removing the first metal layer; and depositing SiN on the second metal layer and the first dielectric layer to form a third dielectric layer. The invention can improve the cut-off frequency of the device while inhibiting the current collapse.

Description

A method for preparing a gate of a GaN HEMT device, a gate and a GaN HEMT device

Technical Field

The present invention belongs to the technical field of integrated circuits, and in particular relates to a method for preparing a gate of a GaN HEMT device, a gate and a GaN HEMT device.

Background technique

In the manufacturing process of traditional GaN HEMT (high electron mobility transistor), SiN surface passivation technology is generally used to reduce the surface state density and suppress current collapse. Ft (cut-off frequency) is directly related to the gate-source capacitance and gate-drain capacitance. Under the condition of a certain gate length, if SiN is used under the gate cap, the gate-source or gate-drain capacitance will be large, resulting in a small Ft, which limits the application frequency scenario of the device.

Summary of the invention

The object of the present invention is to provide a method for preparing a gate of a GaN HEMT device, a gate and a GaN HEMT device, which can improve the Ft of the device while suppressing current collapse, thereby increasing the application frequency of the device.

In order to achieve the above object, one aspect of the present invention provides a method for preparing a gate of a GaN HEMT device, comprising:

Step S1, forming a GaN epitaxial layer on a substrate, and depositing a first dielectric layer on the GaN epitaxial layer;

Step S2, forming a first metal layer on the first dielectric layer by a sputtering process;

Step S3, performing hole etching on the first metal layer and the first dielectric layer at the position where the gate metal structure is to be formed, removing the first metal layer and the first dielectric layer at the position to form a large window structure, exposing the GaN epitaxial layer at the position;

Step S4, depositing a second dielectric layer on the first metal layer and the exposed GaN epitaxial layer, wherein the second dielectric layer is made of a low dielectric constant material;

Step S5, forming a protective layer on the second dielectric layer in the large window structure;

Step S6, removing the second dielectric layer other than the second dielectric layer covered by the protective layer to expose the first metal layer, and then removing the protective layer;

Step S7, forming a second metal layer on the second dielectric layer in the large window structure to form a gate metal structure;

Step S8, removing the second dielectric layer except the second dielectric layer below the second metal layer;

Step S9, removing the first metal layer above the first dielectric layer;

Step S10: depositing SiN on the second metal layer and the first dielectric layer to form a third dielectric layer.

Preferably, in step S1 , the first dielectric layer is formed by depositing SiN using LPCVD or PECVD.

Preferably, in step S2, the first metal layer is formed by sputtering Ti metal.

Preferably, in step S4, the low dielectric constant material used in the second dielectric layer is SiO ₂ , PI or PBO.

Preferably, in step S7, the second metal layer is made of Ni/Au.

Preferably, in step S7, a T-shaped gate metal structure having a gate cap and a gate foot is formed as the gate metal structure, and in step S8, the second dielectric layer except the second dielectric layer under the gate cap is removed.

Preferably, in step S8, grooves are formed on both sides of the second metal layer, and the GaN epitaxial layer is exposed in the grooves. In step S10, the grooves on both sides of the second metal layer are filled with SiN by depositing SiN.

Another aspect of the present invention provides a gate of a GaN HEMT device, which is prepared using the above method.

Another aspect of the present invention provides a GaN HEMT device having the above-mentioned gate.

According to the gate preparation method, gate and GaN HEMT device of the above aspects of the present invention, by introducing a second dielectric layer of low dielectric constant material under the gate cap, the Ft of the device can be improved while suppressing current collapse, thereby increasing the application frequency of the device.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the technical solution of the present invention, the following briefly introduces the drawings used in the description of the embodiments of the present invention. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work:

FIG1 is a flow chart of a method for preparing a gate of a GaN HEMT device according to an embodiment of the present invention;

FIG2 is a schematic diagram of step S1 in FIG1 ;

FIG3 is a schematic diagram of step S2 in FIG1 ;

FIG4 is a schematic diagram of step S3 in FIG1 ;

FIG5 is a schematic diagram of step S4 in FIG1 ;

FIG6 is a schematic diagram of step S5 in FIG1 ;

FIG7 is a schematic diagram of step S6 in FIG1 ;

FIG8 is a schematic diagram of step S7 in FIG1 ;

FIG9 is a schematic diagram of step S8 in FIG1 ;

FIG10 is a schematic diagram of step S9 in FIG1 ;

FIG11 is a schematic diagram of step S10 in FIG1 ;

Explanation of the reference numerals: 101, substrate, 102, GaN epitaxial layer, 103, first dielectric layer, 104, first metal layer, 105, second dielectric layer, 106, protective layer, 107, second metal layer, 108, third dielectric layer, 200, large window structure.

Detailed ways

In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

An embodiment of the present invention provides a method for preparing a gate of a GaN HEMT device. FIG. 1 is a flow chart of the method for preparing a gate of a GaN HEMT device according to an embodiment of the present invention. As shown in FIG. 1 , the method for preparing a gate of a GaN HEMT device according to an embodiment of the present invention includes steps S1 to S10.

In step S1, as shown in FIG2, a GaN epitaxial layer 102 is formed on a substrate 101, and a first dielectric layer 103 is deposited on the GaN epitaxial layer 102. In this step, the first dielectric layer 103 can be formed by depositing SiN using LPCVD (low pressure chemical vapor deposition) or PECVD (plasma enhanced chemical vapor deposition).

In step S2, as shown in Fig. 3, a first metal layer 104 is formed on the first dielectric layer 103 by a sputtering process. In this step, the first metal layer 104 may be formed by sputtering Ti metal.

In step S3, as shown in FIG4 , the first metal layer 104 and the first dielectric layer 103 are etched to form holes at the position where the gate metal structure is to be formed, and the first metal layer 104 and the first dielectric layer 103 at the position are removed to form a large window structure 200, exposing the GaN epitaxial layer 102 at the position. In this step, dry etching can be used, and the etching stops above the GaN epitaxial layer 102.

In step S4 , as shown in FIG5 , a second dielectric layer 105 is deposited on the first metal layer 104 and the GaN epitaxial layer 102 exposed in the large window structure 200 . The second dielectric layer 105 is made of a low dielectric constant material, generally SiO ₂ , PI (polyimide) or PBO (polybenzoxazole).

In step S5 , as shown in FIG. 6 , a protection layer 106 is formed on the second dielectric layer 105 in the large window structure 200 . The protection layer 106 can be formed by spin-coating a photoresist, then exposing and developing the photoresist and leaving the photoresist there.

In step S6, as shown in FIG7 , the second dielectric layer 105 other than the second dielectric layer 105 covered by the protective layer 106 is removed to expose the first metal layer 104, and then the protective layer 106 is removed. In this step, a dry etching process may be used, the etching stops above the first metal layer 104, and then the protective layer 106 is removed.

In step S7, as shown in FIG8, a second metal layer 107 is formed on the second dielectric layer 105 in the large window structure 200 to form a gate metal structure. In this step, the second metal layer can be made of Ni/Au, and the gate metal structure is finally formed through the existing exposure, development and stripping process, which will not be described in detail here.

In step S8, as shown in FIG. 9, the second dielectric layer 105 except the second dielectric layer 105 below the second metal layer 107 is removed, that is, except for the second dielectric layer 105 below the gate cap of the second metal layer 107, the second dielectric layer 105 at other positions can be removed by dry etching.

In step S9 , as shown in FIG. 10 , the first metal layer 104 above the first dielectric layer 103 is removed. A dry etching process may be used, and the etching stops above the first dielectric layer 103 .

In step S10 , as shown in FIG. 11 , a third dielectric layer 108 is deposited on the second metal layer 107 and the first dielectric layer 103 . The third dielectric layer 108 may be formed by depositing SiN using PECVD.

Through the above steps S1 to S10, the gate preparation of the GaN HEMT device is completed.

In one embodiment, when the second metal layer 107 does not completely cover the large window structure 200, after removing the second dielectric layer 105 except the second dielectric layer 105 below the second metal layer 107 in step S8, grooves are formed on both sides of the second metal layer 107, and the GaN epitaxial layer 102 is exposed in the grooves. In this step S10, SiN is filled in the grooves on both sides of the second metal layer 107 by SiN deposition.

In another embodiment, in step S7, a T-shaped gate metal structure having a gate cap and a gate foot is formed as a gate metal structure by manufacturing a second metal layer 107, and in step S8, the second dielectric layer 105 except the second dielectric layer 105 under the gate cap is removed, so that only the second dielectric layer 105 of low dielectric constant material is retained under the gate cap.

The embodiment of the present invention further provides a gate of a GaN HEMT device, which is prepared by the method of the embodiment of the present invention. In addition, the embodiment of the present invention further provides a GaN HEMT device, which has the gate of the embodiment of the present invention.

According to the gate preparation method of the GaN HEMT device of the above embodiment of the present invention, the gate-drain capacitance and gate-source capacitance of the device are reduced by introducing a low dielectric constant material (the second dielectric layer 105) under the gate cap of the gate metal structure, while other regions (gate-drain and gate-source) are passivated using SiN. This can suppress the current collapse effect, improve the efficiency of the GaN HEMT device, and improve the Ft of the device, thereby increasing the application frequency of the device, which is particularly suitable for millimeter wave application scenarios.

At the same time, by introducing the metal layer (first metal layer 104) between the first dielectric layer and the second dielectric layer, the advantages of simple and controllable process and high process stability can be achieved in the gate manufacturing process.

The above description is only by way of illustration of certain exemplary embodiments of the present invention. It is undoubted that, for those skilled in the art, the described embodiments can be modified in various ways without departing from the spirit and scope of the present invention. Therefore, the above drawings and descriptions are illustrative in nature and should not be construed as limiting the scope of protection of the claims of the present invention.

Claims (9)

1. A method for preparing a gate of a GaN HEMT device, comprising: Step S1, forming a GaN epitaxial layer on a substrate, and depositing a first dielectric layer on the GaN epitaxial layer; Step S2, forming a first metal layer on the first dielectric layer by a sputtering process; Step S3, performing hole etching on the first metal layer and the first dielectric layer at the position where the gate metal structure is to be formed, removing the first metal layer and the first dielectric layer at the position to form a large window structure, exposing the GaN epitaxial layer at the position; Step S4, depositing a second dielectric layer on the first metal layer and the exposed GaN epitaxial layer, wherein the second dielectric layer is made of a low dielectric constant material; Step S5, forming a protective layer on the second dielectric layer in the large window structure; Step S6, removing the second dielectric layer other than the second dielectric layer covered by the protective layer to expose the first metal layer, and then removing the protective layer; Step S7, forming a second metal layer on the second dielectric layer in the large window structure to form a gate metal structure; Step S8, removing the second dielectric layer except the second dielectric layer below the second metal layer; Step S9, removing the first metal layer above the first dielectric layer; Step S10: depositing SiN on the second metal layer and the first dielectric layer to form a third dielectric layer. 2 . The method according to claim 1 , wherein in step S1 , the first dielectric layer is formed by depositing SiN using LPCVD or PECVD. 3 . The method according to claim 1 , wherein in step S2 , the first metal layer is formed by sputtering Ti metal. 4 . The method according to claim 1 , wherein in step S4 , the low dielectric constant material used in the second dielectric layer is SiO ₂ , PI or PBO. 5 . 5 . The method according to claim 1 , wherein in step S7 , the second metal layer is made of Ni/Au. 6. The method according to claim 1 or 2, characterized in that in step S7, a T-shaped gate metal structure having a gate cap and a gate foot is formed as the gate metal structure, and in step S8, the second dielectric layer except the second dielectric layer under the gate cap is removed. 7. The method according to claim 1 or 2, characterized in that in step S8, grooves are formed on both sides of the second metal layer, and the GaN epitaxial layer is exposed in the grooves, and in step S10, the grooves on both sides of the second metal layer are filled with SiN by SiN deposition. 8. A gate of a GaN HEMT device, characterized in that it is prepared by the method according to any one of claims 1 to 7. 9. A GaN HEMT device, characterized by comprising the gate according to claim 8.