CN118398552A

CN118398552A - 3D vertical interconnection packaging structure and preparation method thereof

Info

Publication number: CN118398552A
Application number: CN202410658797.8A
Authority: CN
Inventors: 陈彦亨; 林正忠
Original assignee: Shenghejing Micro Semiconductor Jiangyin Co Ltd
Current assignee: SJ Semiconductor Jiangyin Corp
Priority date: 2024-05-24
Filing date: 2024-05-24
Publication date: 2024-07-26

Abstract

The invention provides a 3D vertical interconnection packaging structure and a preparation method thereof, wherein a 3D voltage stabilizing structure with rewiring layers on two sides is prepared, and the 3D voltage stabilizing structure is vertically arranged to form the 3D vertical voltage stabilizing structure during bonding, so that a power supply and a functional chip can form vertical butt joint through the 3D vertical voltage stabilizing structure, the transmission distance is shortened, the transmission interference is reduced, the IR voltage drop loss is reduced, and the power supply signal transmission is effectively carried out.

Description

3D vertical interconnection packaging structure and preparation method thereof

Technical Field

The invention belongs to the technical field of semiconductor manufacturing, and relates to a 3D vertical interconnection packaging structure and a preparation method thereof.

Background

Packaging technology is a key element in the semiconductor manufacturing process, and not only protects the chip from physical damage and environmental impact, but also provides the functions of electrical connection and thermal management. With the increasing demands of electronic products for miniaturization, light weight and high performance, packaging technology is also continuously developed and innovated.

In the packaging process, when a plurality of chiplets are integrated in a homogeneous or heterogeneous manner, the processing steps such as chip processing in the previous step, bump processing in the middle step (Bumping), interconnection between a rewiring layer (RDL) in the subsequent step and a through-silicon via (TSV) interposer, bonding between a chip and a passive element, plastic packaging, and interconnection between the chip and a substrate after plastic packaging are generally required. The power management chip and the passive element are horizontally bonded on the surface of the substrate, so that a transmission path needs to pass through the substrate, the power management chip, the passive element and the chip power supply area in the power transmission process, and the transmission distance is long, so that transmission interference is easy to cause IR voltage drop loss. Most existing solutions increase the platform voltage source (e.g. from 0.9V to 1.1V) to ensure electrical performance, but this approach causes an increase in the overall power of the chip.

Therefore, it is necessary to provide a 3D vertical interconnection package structure and a method for manufacturing the same.

Disclosure of Invention

In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a 3D vertical interconnection package structure and a method for manufacturing the same, which are used for solving the problem that it is difficult to effectively perform power signal transmission in the prior art.

To achieve the above and other related objects, the present invention provides a method for manufacturing a 3D vertical interconnect package structure, comprising the steps of:

providing a wafer level support substrate;

forming a first rewiring layer on the wafer-level support substrate;

Providing a power management chip unit, bonding the power management chip unit on the first rewiring layer, wherein the power management chip unit comprises a power management chip and a second rewiring layer positioned on the surface of the power management chip, the second rewiring layer is electrically connected with the power management chip, a metal connecting piece is formed on the first rewiring layer, and a first end of the metal connecting piece is electrically connected with the first rewiring layer;

Forming a packaging layer on the first rewiring layer, wherein the packaging layer coats the power management chip unit and the metal connecting piece, and the second rewiring layer and the second end of the metal connecting piece are exposed;

Forming a third rewiring layer on the packaging layer, wherein the third rewiring layer is electrically connected with the second rewiring layer and the second end of the metal connecting piece;

Providing a passive element, bonding the passive element on the third rewiring layer, and electrically connecting the passive element with the third rewiring layer;

removing the wafer-level support substrate to expose the first rewiring layer;

Cutting to form an independent 3D voltage stabilizing structure, wherein the first ends and the second ends of the metal wiring in the first rewiring layer and the third rewiring layer are exposed from opposite side surfaces of the 3D voltage stabilizing structure;

providing a substrate, wherein the substrate comprises a substrate first surface and an opposite substrate second surface;

Rotating the 3D voltage stabilizing structure, bonding the 3D voltage stabilizing structure on the first surface of the substrate to form a 3D vertical voltage stabilizing structure, electrically connecting the exposed first end of the metal wiring with the substrate, providing a TSV switching unit, and bonding the TSV switching unit on the first surface of the substrate, wherein the TSV switching unit comprises a TSV switching plate electrically connected with the substrate and a fourth re-wiring layer positioned on the surface of the TSV switching plate, and the fourth re-wiring layer is electrically connected with the TSV switching plate;

Forming a first filling layer, wherein the first filling layer fills gaps among the 3D vertical voltage stabilizing structure, the TSV switching unit and the substrate, and exposes the second end of the metal wiring and the fourth re-wiring layer;

Providing a chip unit, bonding the chip unit on the 3D vertical voltage stabilizing structure and the TSV switching unit, wherein the chip unit comprises a functional chip and a fifth rewiring layer, the functional chip comprises a chip power supply area and a chip signal area, the fifth rewiring layer comprises a wiring power supply area which is correspondingly and electrically connected with the chip power supply area and a wiring signal area which is correspondingly and electrically connected with the chip signal area, the wiring power supply area is electrically connected with the 3D vertical voltage stabilizing structure, and the wiring signal area is electrically connected with the fourth rewiring layer;

forming a second filling layer, wherein the second filling layer fills a gap between the chip unit and the first filling layer;

and forming a metal bump electrically connected with the substrate on the second surface of the substrate.

Optionally, the substrate has a substrate groove therein, and the 3D vertical voltage stabilizing structure is bonded in the substrate groove.

Optionally, the method further comprises the step of bonding a heat dissipation element on the chip unit.

Optionally, the heat dissipating element comprises a heat dissipating housing or a heat sink.

Optionally, the wiring power supply region and the 3D vertical voltage stabilizing structure are arranged vertically.

Optionally, the method of cutting to form the independent 3D voltage stabilizing structure includes one or a combination of mechanical cutting or laser cutting.

The present invention also provides a 3D vertical interconnection packaging structure, the 3D vertical interconnection packaging structure comprising:

the substrate comprises a substrate first surface and an opposite substrate second surface;

A 3D vertical voltage stabilizing structure bonded to the first side of the substrate, the 3D vertical voltage stabilizing structure comprising a power management chip unit, a first rewiring layer and a third rewiring layer on opposite sides of the power management chip unit, a packaging layer covering the power management chip unit, a metal connecting piece penetrating the packaging layer and having a first end electrically connected to the first rewiring layer and a second end electrically connected to the third rewiring layer, and a passive element bonded to the third rewiring layer and electrically connected to the third rewiring layer, wherein the power management chip unit comprises a power management chip and a second rewiring layer on the surface of the power management chip, the second rewiring layer is electrically connected to the power management chip, the third rewiring layer is electrically connected to the second rewiring layer, the 3D vertical voltage stabilizing structure exposes the first ends of metal wires in the first rewiring layer and the second ends of the second wires in the first rewiring layer and the second ends of the second wires are electrically connected to the substrate;

The TSV switching unit is bonded to the first surface of the substrate and comprises a TSV switching plate electrically connected with the substrate and a fourth rewiring layer positioned on the surface of the TSV switching plate, and the fourth rewiring layer is electrically connected with the TSV switching plate;

A first filling layer filling gaps among the 3D vertical voltage stabilizing structure, the TSV switching unit and the substrate, and exposing a second end of the metal wiring and the fourth re-wiring layer;

The chip unit is bonded on the 3D vertical voltage stabilizing structure and the TSV switching unit, the chip unit comprises a functional chip and a fifth re-wiring layer, the functional chip comprises a chip power supply area and a chip signal area, the fifth re-wiring layer comprises a wiring power supply area which is correspondingly and electrically connected with the chip power supply area and a wiring signal area which is correspondingly and electrically connected with the chip signal area, the wiring power supply area is electrically connected with the 3D vertical voltage stabilizing structure, and the wiring signal area is electrically connected with the fourth re-wiring layer;

a second filling layer filling a gap between the chip unit and the first filling layer;

And the metal lug is positioned on the second surface of the substrate and is electrically connected with the substrate.

Optionally, a heat dissipation element is further included on the chip unit, and the heat dissipation element includes a heat dissipation housing or a heat sink.

As described above, according to the 3D vertical interconnection packaging structure and the method for manufacturing the same, the 3D voltage stabilizing structure with the rewiring layer on both sides is manufactured, and the 3D voltage stabilizing structure is vertically arranged to form the 3D vertical voltage stabilizing structure during bonding, so that the power supply and the functional chip can form vertical butt joint through the 3D vertical voltage stabilizing structure, the transmission distance is shortened, the transmission interference is reduced, the IR voltage drop loss is reduced, and the power supply signal transmission is effectively performed.

Drawings

Fig. 1 is a schematic process flow diagram of preparing a 3D vertical interconnect package structure according to an embodiment of the present invention.

Fig. 2 to 15 are schematic structural views showing steps in preparing a 3D vertical interconnect package structure according to an embodiment of the present invention.

Description of the reference numerals

100. Wafer level support substrate

101. Separating layer

102. Metal seed layer

110 3D vertical voltage stabilizing structure

210. First rewiring layer

211. First metal wiring

212. A first dielectric layer

220. Second rewiring layer

221. Second metal wiring

222. Second dielectric layer

230. Third rewiring layer

231. Third metal wiring

232. Third dielectric layer

240. Fourth rewiring layer

241. Fourth metal wiring

242. Fourth dielectric layer

251. Wiring power supply region

252. Wiring signal region

300. Power management chip unit

301. Power management chip

400. Encapsulation layer

410. Passive element

500. Substrate board

501. Substrate groove

600 TSV switching unit

601 TSV adapter plate

710. First filling layer

720. Second filling layer

800. Chip unit

801. Chip power supply area

802. Chip signal region

900. Heat dissipation element

120. Metal bump

130. Metal connecting piece

Detailed Description

Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.

As described in detail in the embodiments of the present invention, the cross-sectional view of the device structure is not partially enlarged to a general scale for convenience of explanation, and the schematic drawings are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in actual fabrication.

For ease of description, spatially relative terms such as "under", "below", "beneath", "above", "upper" and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures, including embodiments in which the first and second features are formed in direct contact, as well as embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact, and further, when a layer is referred to as being "between" two layers, it may be the only layer between the two layers, or there may be one or more intervening layers.

It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of each component in actual implementation may be changed at will, and the layout of the components may be more complex.

As shown in fig. 1, the present embodiment provides a method for manufacturing a 3D vertical interconnection package structure, where fig. 2 to 15 illustrate schematic structural diagrams of each step in manufacturing the 3D vertical interconnection package structure. The preparation of the 3D vertical interconnect package structure is described below with reference to the accompanying drawings.

First, referring to fig. 2, step S1 is performed to provide a wafer level support substrate 100.

Specifically, the material of the wafer level support substrate 100 may include, but is not limited to, a material having insulation properties such as glass, silicon, epoxy, etc., and the dimensions of the wafer level support substrate 100 may include, but are not limited to, 4 feet, 6 inches, 8 inches, 12 inches, etc.

In this embodiment, the separation layer 101 is preferably formed on the surface of the wafer level support substrate 100, for example, a light-heat conversion layer formed by a light-heat conversion (LTHC) coating material may be selected as the separation layer 101, so that the LTHC coating material may be decomposed under heat, for example, by light/radiation (such as laser) to release the wafer level support substrate 100, thereby achieving convenience of separation operation.

Next, referring to fig. 3, step S2 is performed to form a first rewiring layer 210 on the wafer level support substrate 100.

Specifically, the first re-wiring layer 210 includes a first metal wiring 211 and a first dielectric layer 212, and the material of the first dielectric layer 212 may include a polymer such as polybenzoxazole, polyimide, or an inorganic dielectric material such as silicon nitride, silicon oxide, etc., which is not limited herein; the material of the first metal wiring 211 may include, for example, aluminum, copper, tungsten, or an alloy thereof, which is not limited herein. The specific structure, material and preparation method of the first re-wiring layer 210 are not limited herein, and the first re-wiring layer 210 may be formed by a process such as photolithography, etching, electroplating or deposition, etc. in combination, as known in the art.

In this embodiment, the first re-wiring layer 210 is formed by electroplating, so that a metal seed layer 102, such as a Ti/Cu stack, is disposed between the first re-wiring layer 210 and the separation layer 101, and the material of the metal seed layer 102 is not limited herein.

Next, referring to fig. 4 and 5, step S3 is performed, in which a power management chip unit 300 is provided, the power management chip unit 300 is bonded to the first rewiring layer 210, the power management chip unit 310 includes a power management chip 301 and a second rewiring layer 220 located on the surface of the power management chip 301, the second rewiring layer 220 is electrically connected to the power management chip 301, and a metal connection 130 is formed on the first rewiring layer 210, and a first end of the metal connection 130 is electrically connected to the first rewiring layer 210.

Specifically, fig. 5 is an enlarged view of the power management chip unit 300 shown in the dashed-line frame of fig. 4, and the preparation of the power management chip unit 300 is not limited herein, and the second re-wiring layer 220 includes the second metal wiring 221 and the second dielectric layer 222, and the specific structure, material and preparation method of the second re-wiring layer 220 are not limited herein, and may refer to the prior art. Wherein the second metal wiring 221 is electrically connected to a pad of the power management chip 301.

The order of forming the metal connection 130 and bonding the power management chip unit 300 is not limited herein, and may be selected according to the need. The metal connector 130 may be, for example, a copper metal pillar, but is not limited thereto, and a method for manufacturing the metal connector 130 is not limited thereto. Next, referring to fig. 4, step S4 is performed, and a package layer 400 is formed on the first rewiring layer 210, wherein the package layer 400 encapsulates the power management chip unit 300 and the metal connection 130, and exposes the second rewiring layer 220 and the second end of the metal connection 130.

Specifically, the method for forming the encapsulation layer 400 may include, but is not limited to, compression molding, transfer molding, and spin coating, and the material of the encapsulation layer 400 may include, but is not limited to, epoxy and polyamide, and the material and preparation method of the encapsulation layer 400 are not limited herein.

Wherein, a polishing process step, such as Chemical Mechanical Polishing (CMP), is preferably performed to expose the second metal wiring 221 and the second end of the metal connection member 130, and planarize the surface, so as to facilitate subsequent process operations.

Next, referring to fig. 6, step S5 is performed to form a third re-wiring layer 230 on the package layer 400, where the third re-wiring layer 230 is electrically connected to the second re-wiring layer 220 and the second end of the metal connection 130.

Specifically, the third re-wiring layer 230 includes a third metal wiring 231 and a third dielectric layer 232, and the specific structure, material and preparation method of the third re-wiring layer 230 are not limited herein, and may refer to the prior art.

In this embodiment, the metal connection member 130 may interconnect the first rewiring layer 210 and the third rewiring layer 230 located on opposite sides of the power management chip unit 300, so that electrical components can be conveniently connected in a limited space, the wiring density is improved, and the wiring mode is enabled to be more flexible.

Next, referring to fig. 7, step S6 is performed to provide a passive device 410, and the passive device 410 is bonded to the third re-wiring layer 230, and the passive device 410 is electrically connected to the third re-wiring layer 230.

Specifically, the passive element 410 may be selected from one or a combination of capacitance, resistance, and inductance, as desired, which is not limited herein.

Next, referring to fig. 8, step S7 is performed to remove the wafer level support substrate 100 and expose the first rewiring layer 210.

Specifically, based on the separation layer 101, the wafer level support substrate 100 may be released by, for example, light/radiation, and after the wafer level support substrate 100 is removed, the metal seed layer 102 may be removed by, for example, wet etching to expose the first rewiring layer 210, so as to facilitate subsequent electrical connection, but the method for removing the wafer level support substrate 100 and the metal seed layer 102 is not limited thereto.

Next, referring to fig. 8 and 9, step S8 is performed to cut to form an independent 3D voltage stabilizing structure, and the opposite sides of the 3D voltage stabilizing structure expose the first ends and the second ends of the first metal wires 211 and the third metal wires 231 in the first re-wiring layer 210 and the third re-wiring layer 230.

In the cutting process, one or a combination of mechanical cutting and laser cutting may be used, and the cutting process may be specifically selected according to needs, which is not limited herein. As shown in fig. 8, in the present embodiment, the dicing separation operation is performed by a mechanical dicing method based on a Wafer process (Wafer mount), but the dicing method is not limited thereto.

After dicing, the wafer level structure may be divided into a plurality of independently arranged 3D voltage stabilizing structures, and fig. 9 is a schematic structural diagram of a 3D vertical voltage stabilizing structure 110 formed by performing a rotation operation on the obtained 3D voltage stabilizing structure. After the dicing process, the first end and the second end of the first metal wiring 211, and the first end and the second end of the third metal wiring 231 may be exposed, so as to facilitate subsequent electrical connection.

Next, referring to fig. 10, step S9 is performed to provide a substrate 500, where the substrate 500 includes a substrate first surface and an opposite substrate second surface.

Specifically, in this embodiment, the substrate 500 is a PCB substrate having an electrical connection layer therein, and both opposite sides of the substrate 500 are provided with electrical terminals for electrical connection, such as metal pads, so that the substrate 500 can be electrically connected to other devices later.

Further, in this embodiment, the substrate 500 is preferably further provided with a substrate groove 501, so that a receiving space is provided for the 3D vertical voltage stabilizing structure 110 through the substrate groove 501, so as to further reduce the package size.

The width and depth of the substrate recess 501 may be set as desired, and are not excessively limited herein, and the specific type of the substrate 500 is not excessively limited herein.

Next, referring to fig. 10 and 11, step S10 is performed, in which the 3D voltage stabilizing structure is rotated, the 3D voltage stabilizing structure is bonded to the first surface of the substrate to form a 3D vertical voltage stabilizing structure 110, and the exposed first ends of the first metal wiring 211 and the third metal wiring 231 are electrically connected to the substrate 500, and a TSV switching unit 600 is provided, and the TSV switching unit 600 is bonded to the first surface of the substrate, wherein the TSV switching unit 600 includes a TSV switching board 601 electrically connected to the substrate 500, and a fourth re-wiring layer 240 located on the surface of the TSV switching board 601, and the fourth re-wiring layer 240 is electrically connected to the TSV switching board 601.

Specifically, fig. 11 is a partially enlarged view of the TSV switching unit 600 in the dashed-line box in fig. 10, wherein the fourth re-wiring layer 240 includes a fourth metal wiring 241 and a fourth dielectric layer 242, and the specific structure, material and preparation method of the fourth re-wiring layer 240 are not limited herein, and reference is made to the prior art.

The sequence of bonding the 3D voltage stabilizing structure and the TSV adapter unit 600 on the substrate 500 is not limited herein, and may be performed according to needs, for example, bonding the 3D voltage stabilizing structure first, then bonding the TSV adapter unit 600, or bonding the TSV adapter unit 600 first, then bonding the 3D voltage stabilizing structure, and the bonding manner of the 3D voltage stabilizing structure and the TSV adapter unit 600 may be performed by a reflow soldering process or a chip bonding (DA) process, which is not limited herein.

When the 3D voltage stabilizing structure is bonded, the 3D voltage stabilizing structure is required to be rotated, so that the 3D voltage stabilizing structure is converted into the 3D vertical voltage stabilizing structure 110, and the exposed first end of the first metal wiring 211 and the exposed first end of the second metal wiring 221 are electrically connected with the substrate 500. The rotation operation may be performed before bonding or may be performed during bonding, which is not limited herein.

The distribution and the number of the TSV switching units 600 and the 3D vertical voltage stabilizing structures 110 are not limited herein.

Next, referring to fig. 10, step S11 is performed, and a first filling layer 710 is formed, where the first filling layer 710 fills the gaps between the 3D vertical voltage stabilizing structure 110, the TSV switching unit 600 and the substrate 500, and exposes the second ends of the first metal wire 211 and the third metal wire 231 and the fourth metal wire 241 in the fourth re-wiring layer 240 for subsequent electrical connection.

Specifically, the first filling layer 710 may protect the electrical connection between the 3D vertical voltage stabilizing structure 110, the TSV adapter unit 600 and the substrate 500, and improve bonding stability. The material of the first filling layer 710 may be an insulating material, and the specific type is not limited herein.

Next, referring to fig. 12 and 13, step S12 is performed, in which a chip unit 800 is provided, the chip unit 800 is bonded to the 3D vertical voltage stabilizing structure 110 and the TSV switching unit 600, the chip unit 800 includes a functional chip and a fifth re-wiring layer, the functional chip includes a chip power supply region 801 and a chip signal region 802, the fifth re-wiring layer includes a wiring power supply region 251 correspondingly electrically connected to the chip power supply region 801 and a wiring signal region 252 correspondingly electrically connected to the chip signal region 802, and the wiring power supply region 251 is electrically connected to the 3D vertical voltage stabilizing structure 110, and the wiring signal region 252 is electrically connected to the fourth re-wiring layer 240.

Specifically, fig. 13 illustrates a partial enlarged view of the chip unit 800 shown in the dashed line box of fig. 12. The wiring density of the wiring signal region 252 is greater than that of the wiring power supply region 251, the number of wiring layers of the wiring signal region 252 is greater than that of the wiring power supply region 251, the wiring power supply region 251 is electrically connected to the second ends of the first metal wiring 211 and the third metal wiring 231 in the 3D vertical voltage stabilizing structure 110, and the wiring signal region 252 is electrically connected to the fourth metal wiring 241.

The chip signal area 802 has a dense line width and line distance compared with the chip power area 801, and has a large number of wiring layers, for example, the line width and line distance of the wiring signal area 252 is generally smaller than 10 μm, and the number of wiring layers is generally 3-4 layers, in order to avoid signal loss; for voltage and current transmission, the chip power region 801 needs a larger line width and line distance to avoid line burnout, for example, the line width and line distance of the wiring power region 251 need to be larger than 10 μm, and the number of wiring layers is generally 1-2.

As an example, the wiring power supply region 251 and the 3D vertical voltage stabilizing structure 110 are vertically disposed, so that the chip power supply region 251 directly performs power signal transmission vertically after passing through the 3D vertical voltage stabilizing structure 110 vertically disposed, so that vertical butt joint is formed between the power supply and the functional chip by the 3D vertical voltage stabilizing structure 110, so as to shorten the transmission distance, reduce the transmission interference, reduce the IR drop loss, and effectively perform power signal transmission.

Next, referring to fig. 14, step S13 is performed to form a second filling layer 720, where the second filling layer 720 fills the gap between the chip unit 800 and the first filling layer 710.

Specifically, the bonding stability and the electrical performance can be improved by the second filling layer 720, and the material of the second filling layer 720 may be an insulating material, and the specific type is not limited herein.

Next, referring to fig. 15, step S14 is performed to form a metal bump 120 electrically connected to the substrate 500 on the second surface of the substrate.

As an example, referring to fig. 15, the method may further include a step of bonding a heat dissipation element 900 to the chip unit 800, where the heat dissipation element 900 may include a heat dissipation housing or a heat sink.

Specifically, the heat dissipation element 900 may be in direct contact with the chip unit 800 or in indirect contact with the chip unit through a heat-conducting adhesive, so that the heat dissipation effect may be improved through the heat dissipation element 900. In this embodiment, the heat dissipating member 900 employs a heat dissipating housing bonded to the surface of the substrate 500 to provide a protection cavity through the heat dissipating housing, however, in another embodiment, the heat dissipating member 900 may also employ a heat dissipating fin located on the chip unit 800, which is not limited herein.

Referring to fig. 15, the present invention also provides a 3D vertical interconnection package structure, the 3D vertical interconnection package structure including:

A substrate 500, the substrate 500 comprising a substrate first face and an opposite substrate second face;

a 3D vertical voltage stabilizing structure 110, the 3D vertical voltage stabilizing structure 110 being bonded to the first side of the substrate, the 3D vertical voltage stabilizing structure 110 comprising a power management chip unit 300, a first rewiring layer 210 and a third rewiring layer 230 on opposite sides of the power management chip unit 300, a package layer 400 covering the power management chip unit 300, a metal connection member 130 penetrating the package layer 400 and having a first end electrically connected to the first rewiring layer 210 and a second end electrically connected to the third rewiring layer 230, and a passive element 410 bonded to the third rewiring layer 230 and electrically connected to the third rewiring layer 230, wherein the power management chip unit 300 comprises a power management chip 301 and a second rewiring layer 220 on a surface of the power management chip 301, the first rewiring layer 220 is electrically connected to the power management chip 301, the third rewiring layer 230 is electrically connected to the second rewiring layer 220, the 3D vertical structure 110 has a first end electrically connected to the first end of the first rewiring layer 230 and a second end electrically connected to the first rewiring layer 230, and the second end of the metal layer 230 is exposed from the substrate;

A TSV transfer unit 600, wherein the TSV transfer unit 600 is bonded to the first surface of the substrate, the TSV transfer unit 600 includes a TSV interposer 601 electrically connected to the substrate 500 and a fourth re-wiring layer 240 located on the surface of the TSV interposer 601, and the fourth re-wiring layer 240 is electrically connected to the TSV interposer 601;

A first filling layer 710, the first filling layer 710 filling gaps among the 3D vertical voltage stabilizing structure 110, the TSV switching unit 600 and the substrate 500 and exposing the second end of the metal wiring and the fourth re-wiring layer 240;

The chip unit 800 is bonded to the 3D vertical voltage stabilizing structure 110 and the TSV adapter unit 600, the chip unit 800 includes a functional chip and a fifth re-wiring layer, the functional chip includes a chip power supply region 801 and a chip signal region 802, the fifth re-wiring layer includes a wiring power supply region 251 correspondingly electrically connected to the chip power supply region 801 and a wiring signal region 252 correspondingly electrically connected to the chip signal region 802, the wiring power supply region 251 is electrically connected to the 3D vertical voltage stabilizing structure 110, and the wiring signal region 252 is electrically connected to the fourth re-wiring layer 240;

a second filling layer 720, the second filling layer 720 filling a gap between the chip unit 800 and the first filling layer 710;

and a metal bump 120, wherein the metal bump 120 is located on the second surface of the substrate and is electrically connected with the substrate 500.

As an example, the substrate 500 has a substrate groove 501 therein, and the 3D vertical voltage stabilizing structure 110 is bonded within the substrate groove 501.

As an example, a heat dissipating element 900 is further included on the chip unit 800, and the heat dissipating element 900 may include a heat dissipating housing or a heat dissipating fin.

As an example, the wiring power supply region 251 is disposed vertically with the 3D vertical voltage stabilizing structure 110.

Specifically, the method for preparing the 3D vertical interconnection packaging structure may be prepared by using the method for preparing the 3D vertical interconnection packaging structure described above, as shown in fig. 2 to 15, but is not limited thereto, and the embodiment directly prepares the 3D vertical interconnection packaging structure by using the preparation process described above, so that the method can be referred to as to the preparation, the material, the specific structure, etc. of the 3D vertical interconnection packaging structure.

In summary, according to the 3D vertical interconnection packaging structure and the method for manufacturing the same, the 3D voltage stabilizing structure with the rewiring layer on both sides is manufactured, and the 3D voltage stabilizing structure is vertically arranged to form the 3D vertical voltage stabilizing structure during bonding, so that the power supply and the functional chip can form vertical butt joint through the 3D vertical voltage stabilizing structure, the transmission distance is shortened, the transmission interference is reduced, the IR voltage drop loss is reduced, and the power supply signal transmission is effectively performed.

The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.

Claims

1. The preparation method of the 3D vertical interconnection packaging structure is characterized by comprising the following steps of:

providing a wafer level support substrate;

forming a first rewiring layer on the wafer-level support substrate;

removing the wafer-level support substrate to expose the first rewiring layer;

2. The method for manufacturing a 3D vertical interconnect package structure of claim 1, wherein: the substrate is provided with a substrate groove, and the 3D vertical voltage stabilizing structure is bonded in the substrate groove.

3. The method for manufacturing a 3D vertical interconnect package structure of claim 1, wherein: and the method also comprises the step of bonding a heat dissipation element on the chip unit.

4. The method for manufacturing a 3D vertical interconnect package structure of claim 3, wherein: the heat dissipation element comprises a heat dissipation shell or a heat dissipation fin.

5. The method for manufacturing a 3D vertical interconnect package structure of claim 1, wherein: the wiring power supply area and the 3D vertical voltage stabilizing structure are vertically arranged.

6. The method for manufacturing a 3D vertical interconnect package structure of claim 1, wherein: the method of cutting to form the independent 3D voltage stabilizing structure includes one or a combination of mechanical cutting and laser cutting.

7. A 3D vertical interconnect package structure, the 3D vertical interconnect package structure comprising:

8. The 3D vertical interconnect package structure of claim 7 wherein: the substrate is provided with a substrate groove, and the 3D vertical voltage stabilizing structure is bonded in the substrate groove.

9. The 3D vertical interconnect package structure of claim 7 wherein: the heat dissipation element comprises a heat dissipation shell or a heat dissipation sheet.

10. The 3D vertical interconnect package structure of claim 7 wherein: the wiring power supply area and the 3D vertical voltage stabilizing structure are vertically arranged.