CN118380482B - Back contact solar cell, battery module and photovoltaic system - Google Patents

Abstract

The present invention is applicable to the technical field of solar cells, and provides a back-contact solar cell, a battery assembly and a photovoltaic system. The back-contact solar cell comprises: a silicon substrate, the silicon substrate having a back side and a front side arranged oppositely; a P-type doped polysilicon layer, located in a first region on the back side of the silicon substrate; an N-type doped polysilicon layer, located in a second region on the back side of the silicon substrate; a first metal electrode arranged in the first region and in contact with the P-type doped polysilicon layer; a second metal electrode arranged in the second region and in contact with the N-type doped polysilicon layer; the depth of the metal crystals of the first metal electrode entering the P-type doped polysilicon layer is greater than the depth of the metal crystals of the second metal electrode entering the N-type doped polysilicon layer. The back-contact solar cell of the present invention can improve the contact effect between the metal electrode and the P-type doped polysilicon layer, thereby improving the conductivity of the metal electrode and the P-type doped polysilicon layer, and improving the battery conversion efficiency.

Description

Back contact solar cell, battery module and photovoltaic system

Technical Field

The present invention relates to the technical field of solar cells, and in particular to a back-contact solar cell, a cell assembly and a photovoltaic system.

Background Art

Solar cell power generation is a sustainable source of clean energy. It uses the photovoltaic effect of semiconductors to convert sunlight into electrical energy, and the conversion efficiency is an important indicator of solar cell performance. IBC (Interdigitated back contact) solar cells, also known as interdigitated back contact cells, have positive and negative electrodes designed on the back of the cell, so that the front surface is completely free from the shading of metal grid lines, eliminating the optical loss caused by the shading of metal grid lines. At the same time, the electrode width can be designed to be wider than the current one, reducing the series resistance loss, thereby greatly improving the cell conversion efficiency. In addition, due to the design of no electrode on the front, the product appearance is more beautiful and suitable for a variety of application scenarios.

In the prior art, the back side of a back-contact solar cell forms an alternating P-zone and N-zone. Usually, the depth of the metal electrode corresponding to the P-zone penetrating into the P-type doped polysilicon layer is equal to the depth of the metal electrode corresponding to the N-zone penetrating into the N-type doped polysilicon layer. Since the contact effect between the P-type doped polysilicon layer and the metal electrode is relatively poor, the conductivity of the P-type doped polysilicon layer and the metal electrode is poor, which affects the conversion efficiency of the battery.

Summary of the invention

The present invention provides a back-contact solar cell, aiming to solve the problem in the prior art that the back-contact solar cell has poor contact effect between a P-type doped polysilicon layer and a metal electrode, thereby affecting the cell conversion efficiency.

The present invention is implemented by providing a back contact solar cell, comprising:

A silicon substrate having a back surface and a front surface arranged opposite to each other;

A P-type doped polysilicon layer, located in a first region on the back side of the silicon substrate;

An N-type doped polysilicon layer is located in a second region on the back side of the silicon substrate, and the first region is different from the second region;

A first metal electrode disposed in the first region and in contact with the P-type doped polysilicon layer;

A second metal electrode disposed in the second region and in contact with the N-type doped polysilicon layer;

The depth of metal crystals of the first metal electrode penetrating into the P-type doped polysilicon layer is greater than the depth of metal crystals of the second metal electrode penetrating into the N-type doped polysilicon layer.

Preferably, the ratio of the depth of the metal crystals of the first metal electrode penetrating into the P-type doped polysilicon layer to the depth of the metal crystals of the second metal electrode penetrating into the N-type doped polysilicon layer is 1-4 and is not equal to 1.

Preferably, the ratio of the depth of the metal crystals of the first metal electrode penetrating into the P-type doped polysilicon layer to the depth of the metal crystals of the second metal electrode penetrating into the N-type doped polysilicon layer is 1-2 and is not equal to 1.

Preferably, the metal crystals of the first metal electrode penetrate into the P-type doped polysilicon layer to a depth of 2 to 300 nm; and the metal crystals of the second metal electrode penetrate into the N-type doped polysilicon layer to a depth of 1 to 200 nm.

Preferably, both the first metal electrode and the second metal electrode include silver, glass frit and organic material, and the content of glass frit in the first metal electrode is greater than that in the second metal electrode.

Preferably, the refractive index of the P-type doped polysilicon layer is smaller than the refractive index of the N-type doped polysilicon layer.

Preferably, it also includes a back passivation film layer located on the back side of the P-type doped polysilicon layer and the back side of the N-type doped polysilicon layer, and the metal crystals of the first metal electrode pass through the back passivation film layer to enter the P-type doped polysilicon layer, and the metal crystals of the second metal electrode pass through the back passivation film layer to enter the N-type doped polysilicon.

Preferably, an average grain size of the P-type doped polysilicon layer is greater than an average grain size of the N-type doped polysilicon layer.

Preferably, the ratio of the average grain size of the P-type doped polysilicon layer to the average grain size of the N-type doped polysilicon layer is 1-4 and is not equal to 1.

Preferably, the thickness of the N-type doped polysilicon layer is greater than the thickness of the P-type doped polysilicon layer.

Preferably, the ratio of the thickness of the N-type doped polysilicon layer to the thickness of the P-type doped polysilicon layer is 1-2, and is not equal to 1.

The present invention also provides a battery assembly, comprising the above-mentioned back-contact solar cell.

The present invention also provides a photovoltaic system, comprising the above-mentioned battery assembly.

A back-contact solar cell provided by the present invention increases the contact area between the metal crystals of the first metal electrode and the P-type doped polysilicon layer, thereby improving the contact effect between the first metal electrode and the P-type doped polysilicon layer, achieving good ohmic contact, and improving the conductivity of the first metal electrode and the P-type doped polysilicon layer, thereby improving the battery conversion efficiency.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a schematic diagram of a back-contact solar cell provided by an embodiment of the present invention;

FIG2 is a schematic diagram of a partial structure of a back contact solar cell provided by an embodiment of the present invention;

3 is a scanning electron microscope photograph of a metal crystal of a first metal electrode of a back contact solar cell provided by an embodiment of the present invention entering a P-type doped polysilicon layer;

4 is a scanning electron microscope photograph of a metal crystal of a second metal electrode of a back contact solar cell provided by an embodiment of the present invention entering an N-type doped polysilicon layer.

DETAILED DESCRIPTION

In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

A back-contact solar cell provided by an embodiment of the present invention increases the contact area between the metal crystals of the first metal electrode and the P-type doped polysilicon layer, improves the contact effect between the first metal electrode and the P-type doped polysilicon layer, achieves good ohmic contact, and improves the conductivity of the first metal electrode and the P-type doped polysilicon layer, thereby improving the battery conversion efficiency.

Referring to FIG. 1 , a back-contact solar cell provided by an embodiment of the present invention includes:

A silicon substrate 1, wherein the silicon substrate 1 has a back surface and a front surface that are oppositely arranged;

A P-type doped polysilicon layer 2, located in a first region on the back side of the silicon substrate 1;

The N-type doped polysilicon layer 3 is located in a second region on the back side of the silicon substrate 1, and the first region is different from the second region;

A first metal electrode 6 disposed in the first region and in contact with the P-type doped polysilicon layer 2;

A second metal electrode 7 disposed in the second region and in contact with the N-type doped polysilicon layer 3;

The depth d3 of the metal crystals of the first metal electrode 6 penetrating into the P-type doped polysilicon layer 2 is greater than the depth d4 of the metal crystals of the second metal electrode 7 penetrating into the N-type doped polysilicon layer 3 .

As shown in FIG1 , the back side of the silicon substrate 1 is the lower side, and the front side is the upper side. The dotted line L1 and the dotted line L2 are only used to distinguish the first area from the second area, and do not actually exist in the back contact solar cell. Referring to FIG1 , the area on the left side of the dotted line L1 is the first area, and the area on the right side of the dotted line L2 is the second area, and the first area and the second area are different areas. The P-type doped polysilicon layer 2 is located in the first area on the back side of the silicon substrate 1, and the N-type doped polysilicon layer 3 is located in the second area on the back side of the silicon substrate 1; the P-type doped polysilicon layer 2 is located in the area on the left side of the dotted line L1 on the back side of the silicon substrate 1; the N-type doped polysilicon layer 3 is located in the area on the right side of the dotted line L2 on the back side of the silicon substrate 1.

In an embodiment of the present invention, a back-contact solar cell is provided, in which the depth d3 of the metal crystals of the first metal electrode 6 entering the P-type doped polysilicon layer 2 is set to be greater than the depth d4 of the metal crystals of the second metal electrode 7 entering the N-type doped polysilicon layer 3. On the premise that the depth of the metal crystals of the second metal electrode 7 entering the N-type doped polysilicon layer 3 remains unchanged, the depth of the metal crystals of the first metal electrode 6 entering the P-type doped polysilicon layer 3 is increased, and the contact area between the metal crystals of the first metal electrode 6 and the P-type doped polysilicon layer 2 is increased, thereby improving the contact effect between the first metal electrode 6 and the P-type doped polysilicon layer 2, thereby improving the conductivity of the first metal electrode 6 and the P-type doped polysilicon layer 2, thereby improving the battery conversion efficiency.

In the embodiment of the present invention, the first metal electrode 6 and the second metal electrode 7 can be printed by using slurries with different burn-through capabilities, so as to control the depth of metal crystals of the metal electrodes entering the P-type doped polysilicon layer 2 and the N-type doped polysilicon layer 3. Specifically, the burn-through capability of the slurry of the first metal electrode 6 is greater than the burn-through capability of the slurry of the second metal electrode 7, so that the depth of metal crystals of the first metal electrode 6 entering the P-type doped polysilicon layer 2 is greater than the depth of metal crystals of the second metal electrode 7 entering the N-type doped polysilicon layer 3.

As an embodiment of the present invention, both the first metal electrode 6 and the second metal electrode 7 include silver, glass frit and organic material, and the content of the glass frit in the first metal electrode 6 is greater than that in the second metal electrode 7 .

In this embodiment, the first metal electrode 6 and the second metal electrode 7 both include silver, glass frit and organic material components; wherein the glass frit includes at least one of PbO, Bi ₂ O ₃ , ZnO, SiO ₂ , and MgO, and the glass frit content in the first metal electrode 6 is greater than the glass frit content in the second metal electrode 7, so that the slurry burn-through ability of the first metal electrode 6 is greater than the slurry burn-through ability of the second metal electrode 7, so that the depth of the metal crystals of the first metal electrode 6 entering the P-type doped polysilicon layer 2 is greater than the depth of the metal crystals of the second metal electrode 7 entering the N-type doped polysilicon layer 3.

As an embodiment of the present invention, the depth d3 of the metal crystals of the first metal electrode 6 entering the P-type doped polysilicon layer 2 is 2 to 300 nm; the depth d4 of the metal crystals of the second metal electrode 7 entering the N-type doped polysilicon layer 3 is 1 to 200 nm. The depth d3 of the metal crystals of the first metal electrode 6 entering the P-type doped polysilicon layer 2 and the depth d4 of the metal crystals of the second metal electrode 7 entering the N-type doped polysilicon layer 3 can be flexibly set according to actual needs. The depth d3 of the metal crystals of the first metal electrode 6 entering the P-type doped polysilicon layer 2 and the depth d4 of the metal crystals of the second metal electrode 7 entering the N-type doped polysilicon layer 3 can both be measured by a scanning electron microscope.

For example, the depth d3 of the metal crystals of the first metal electrode 6 entering the P-type doped polysilicon layer 2 can be 2nm, or 10nm, or 30nm, or 50nm, or 70nm, or 90nm, or 100nm, or 110nm, or 120nm, or 140nm, or 160nm, or 200nm, or 240nm, or 260nm, or 280nm, or 300nm. The depth d4 of the metal crystals of the second metal electrode 7 entering the N-type doped polysilicon layer 3 can be 1nm, or 5nm, or 20nm, or 30nm, or 50nm, or 80nm, or 90nm, or 100nm, or 120nm, or 130nm, or 150nm, or 160nm, or 180nm, or 190nm, or 200nm.

As an embodiment of the present invention, the ratio of the depth d3 of the metal crystals of the first metal electrode 6 penetrating into the P-type doped polysilicon layer 2 to the depth d4 of the metal crystals of the second metal electrode 7 penetrating into the N-type doped polysilicon layer 3 is 1-4 and is not equal to 1.

In this embodiment, the ratio of the depth d3 of the metal crystals of the first metal electrode 6 entering the P-type doped polysilicon layer 2 to the depth d4 of the metal crystals of the second metal electrode 7 entering the N-type doped polysilicon layer 3 is greater than 1 and less than or equal to 4. This can reduce the metallization damage of the P-type doped polysilicon layer 2, reduce the square resistance of the P region, and improve the battery efficiency, and can ensure good contact between the metal electrode and the P-type doped polysilicon layer 2, thereby improving the battery conversion efficiency.

For example, the ratio of the depth d3 of the metal crystals of the first metal electrode 6 penetrating into the P-type doped polysilicon layer 2 to the depth d4 of the metal crystals of the second metal electrode 7 penetrating into the N-type doped polysilicon layer 3 may be:

1.01, or 1.05, or 1.1, or 1.15, or 1.2, or 1.25, or 1.3, or 1.35, or 1.4, or 1.45, or 1.5, or 1.55, or 1.6, or 1.65, or 1.7, or 1.75, or 1.8, or 1.85, or 1.9, or 1.92, or 2, or 2.2, or 2.5, or 2.7, or 2.8, or 3.0, or 3.3, or 3.5, or 4.0.

As an embodiment of the present invention, the ratio of the depth d3 of the metal crystals of the first metal electrode 6 penetrating into the P-type doped polysilicon layer 2 to the depth d4 of the metal crystals of the second metal electrode 7 penetrating into the N-type doped polysilicon layer 3 is 1-2 and is not equal to 1.

In this embodiment, the ratio of the depth d3 of the metal crystals of the first metal electrode 6 entering the P-type doped polysilicon layer 2 to the depth d4 of the metal crystals of the second metal electrode 7 entering the N-type doped polysilicon layer 3 is greater than 1 and less than or equal to 2. This can not only ensure good contact between the metal electrodes and the P-type doped polysilicon layer 2, but also facilitate the process control of the depth d3 of the metal crystals of the first metal electrode 6 entering the P-type doped polysilicon layer 2 and the depth d4 of the metal crystals of the second metal electrode 7 entering the N-type doped polysilicon layer 3.

As an embodiment of the present invention, the depth of the metal crystals of the first metal electrode 6 entering the P-type doped polysilicon layer 2 is 2 to 300 nm; the depth of the metal crystals of the second metal electrode 7 entering the N-type doped polysilicon layer 3 is 1 to 200 nm, so as to prevent the metal crystals of the first metal electrode 6 from entering the P-type doped polysilicon layer 2 and the metal crystals of the second metal electrode 7 from entering the N-type doped polysilicon layer 3 from being too deep or too shallow. Among them, the depth d3 of the metal crystals of the first metal electrode 6 entering the P-type doped polysilicon layer 2 and the depth d4 of the metal crystals of the second metal electrode 7 entering the N-type doped polysilicon layer 3 can be flexibly set according to actual needs.

For example, the depth d3 of the metal crystals of the first metal electrode 6 entering the P-type doped polysilicon layer 2 can be 2nm, or 10nm, or 30nm, or 50nm, or 70nm, or 90nm, or 100nm, or 110nm, or 120nm, or 140nm, or 160nm, or 200nm, or 240nm, or 260nm, or 280nm, or 300nm. The depth d4 of the metal crystals of the second metal electrode 7 entering the N-type doped polysilicon layer 3 can be 1nm, or 5nm, or 20nm, or 30nm, or 50nm, or 80nm, or 90nm, or 100nm, or 120nm, or 130nm, or 150nm, or 160nm, or 180nm, or 190nm, or 200nm.

Exemplarily, as shown in FIG3 , the thickness d2 of the P-type doped polysilicon layer 2 is 105 nm, and the depth d3 of the metal crystals of the first metal electrode 6 entering the P-type doped polysilicon layer 2 is 55.6 nm; as shown in FIG4 , the thickness of the N-type doped polysilicon layer 2 is 107 nm, and the depth d4 of the metal crystals of the second metal electrode 7 entering the N-type doped polysilicon layer 3 is 45.6 nm.

As an embodiment of the present invention, the thickness d1 of the N-type doped polysilicon layer 3 is greater than the thickness d2 of the P-type doped polysilicon layer 2 .

In the present embodiment, by setting the thickness d1 of the N-type doped polysilicon layer 3 to be greater than the thickness d2 of the P-type doped polysilicon layer 2, the thickness d2 of the P-type doped polysilicon layer 2 is reduced compared with the thickness d1 of the N-type doped polysilicon layer 3, thereby reducing the etching difficulty of the P-type doped polysilicon layer 2 and the difficulty of the patterning process, thereby facilitating the patterning process of the P-type doped polysilicon layer; moreover, reducing the thickness d2 of the P-type doped polysilicon layer 2 can reduce the difficulty of boron diffusion, which is beneficial to the boron diffusion process and facilitates the preparation of a P-type doped polysilicon layer 2 with a higher concentration; moreover, the thickness d1 of the N-type doped polysilicon layer 3 is greater than the thickness d2 of the P-type doped polysilicon layer 2, and the N-type doped polysilicon is thicker than the P-type doped polysilicon layer 2, thereby enhancing the passivation effect and improving the battery efficiency.

As an embodiment of the present invention, the ratio of the thickness d1 of the N-type doped polysilicon layer 3 to the thickness d2 of the P-type doped polysilicon layer 2 is 1-2 and is not equal to 1.

In this embodiment, the ratio of the thickness d1 of the N-type doped polysilicon layer 3 to the thickness d2 of the P-type doped polysilicon layer 2 is greater than 1 and less than or equal to 2. This can reduce the etching difficulty of the P-type doped polysilicon layer 2 and facilitate the patterning process of the P-type doped polysilicon layer 2, and is beneficial to the boron diffusion process, reducing the difficulty of boron diffusion and facilitating the preparation of a P-type doped polysilicon layer 2 with a higher concentration.

For example, the ratio of the thickness d1 of the N-type doped polysilicon layer 3 to the thickness d2 of the P-type doped polysilicon layer 2 may be:

1.01, or 1.05, or 1.1, or 1.15, or 1.2, or 1.25, or 1.3, or 1.35, or 1.4, or 1.45, or 1.5, or 1.55, or 1.6, or 1.65, or 1.7, or 1.75, or 1.8, or 1.85, or 1.9, or 1.92, or 2.

Optionally, when the ratio of d1 to d2 is 1 to 2, the thickness d1 of the N-type doped polysilicon layer 3 is 100nm to 600nm, and the thickness d2 of the P-type doped polysilicon layer 2 can be 50nm to 300nm. When d1 and d2 are within the above range, both the P-type doped polysilicon layer 2 and the N-type doped polysilicon layer 3 are easy to achieve good doping effects, both have good passivation effects, and at the same time ensure that the metallization damage is small and the contact resistance is small, and the cost is relatively low; in addition, the etching difficulty of the P-type doped polysilicon can be reduced, which is convenient for the patterning process of the P-type doped polysilicon, which is beneficial to the preparation of the N-type doped polysilicon layer 3, and is beneficial to the boron diffusion process, reducing the difficulty of boron diffusion, and facilitating the preparation of a high-concentration P-type doped polysilicon layer 2.

As an embodiment of the present invention, the refractive index of the P-type doped polysilicon layer 2 is smaller than the refractive index of the N-type doped polysilicon layer 3 .

It can be understood that the refractive index of the N-type doped polysilicon layer 3 remains unchanged, and the refractive index of the P-type doped polysilicon layer 2 is reduced, so that the refractive index of the P-type doped polysilicon layer 2 is less than the refractive index of the N-type doped polysilicon layer 3, which can reduce the parasitic absorption effect of the P region, thereby further improving the battery efficiency. The refractive index of the P-type doped polysilicon layer 2 and the refractive index of the N-type doped polysilicon layer 3 are flexibly set according to actual needs, and it is only necessary to satisfy that the refractive index of the P-type doped polysilicon layer 2 is less than the refractive index of the N-type doped polysilicon layer 3.

As an embodiment of the present invention, the average grain size of the P-type doped polysilicon layer 2 is greater than the average grain size of the N-type doped polysilicon layer 3 .

In this embodiment, the average grain size of the P-type doped polysilicon layer 2 and the average grain size of the N-type doped polysilicon layer 3 can be measured by an X-ray diffraction (XRD), a scanning electron microscope (SEM) or a transmission electron microscope (TEM). Among them, the average grain size of the P-type doped polysilicon layer 2 is greater than the average grain size of the N-type doped polysilicon layer 3, which can be understood as the average value of all grain sizes of the P-type doped polysilicon layer 2 per unit area is greater than the average value of all grain sizes of the N-type doped polysilicon layer 3 per unit area; that is, within a unit area, the number of grains in the N-type doped polysilicon layer 3 is greater, and compared with the N-type doped polysilicon layer 3 per unit area, the P-type doped polysilicon layer 2 per unit area has fewer grain boundaries, thereby improving the compactness of the P-type doped polysilicon layer 2, reducing the square resistance of the P-type doped polysilicon layer 2, and reducing current loss, thereby further improving battery efficiency. Moreover, the P-type doped polysilicon layer 2 has fewer grain boundaries, which can reduce the metallization damage to the P-type doped polysilicon layer 2 during the battery metallization process, which is also conducive to improving battery efficiency.

In practical applications, during the preparation process of the P-type doped polysilicon layer 2 and the N-type doped polysilicon layer 3, intrinsic amorphous silicon can be first deposited, and then doping diffusion can be performed. During the doping diffusion process, high-temperature treatment can be performed. By controlling the diffusion temperature and diffusion time of the P-type doped polysilicon layer 2 and the N-type doped polysilicon layer 3, the average grain size of the P-type doped polysilicon layer 2 and the N-type doped polysilicon layer 3 can be controlled. For example, the doping diffusion temperature of the P-type doped polysilicon layer 2 can be set higher and the diffusion time can be set longer, so that the average grain size of the prepared P-type doped polysilicon layer 2 can be larger than the average grain size of the N-type doped polysilicon layer 3.

As an embodiment of the present invention, the ratio of the average grain size of the P-type doped polysilicon layer 2 to the average grain size of the N-type doped polysilicon layer 3 is 1-4 and is not equal to 1.

In this embodiment, the ratio of the grain size of the P-type doped polysilicon layer 2 to the grain size of the N-type doped polysilicon layer 3 is greater than 1 and less than or equal to 4. This can ensure that the average grain size of the P-type doped polysilicon layer 2 and the average grain size of the N-type doped polysilicon layer 3 are within a suitable range, which can reduce the square resistance of the P region and improve the battery efficiency, and facilitate the preparation of the P-type doped polysilicon layer 2 and the N-type doped polysilicon layer 3.

As an embodiment of the present invention, the average grain size of the P-type doped polysilicon layer 2 is 50-600 nm; the average grain size of the N-type doped polysilicon layer 3 is 10-400 nm, which facilitates the preparation of the P-type doped polysilicon layer 2 and the N-type doped polysilicon layer 3.

Please refer to Figure 2, as an embodiment of the present invention, there is a first height difference h1 between the surface of the P-type doped polysilicon layer 2 close to the silicon substrate 1 and the surface of the N-type doped polysilicon layer 3 close to the silicon substrate 1, and the surface of the P-type doped polysilicon layer 2 close to the silicon substrate 1 is farther away from the front side of the silicon substrate 1 than the surface of the N-type doped polysilicon layer 3 close to the silicon substrate 1.

In this embodiment, the surface of the silicon substrate 1 close to the P-type doped polysilicon layer 2 and the surface close to the N-type doped polysilicon layer 3 are not on the same plane; the surface of the P-type doped polysilicon layer 2 close to the silicon substrate 1 is farther away from the front of the silicon substrate 1 than the surface of the N-type doped polysilicon layer 3 close to the silicon substrate 1, and there is a first height difference h1 between the surface of the P-type doped polysilicon layer 2 close to the silicon substrate 1 and the surface of the N-type doped polysilicon layer 3 close to the silicon substrate 1. The relative position control of the P-type doped polysilicon layer 2 and the N-type doped polysilicon layer 3 is more accurate, and the position reference function is more accurate; and before the latter doped polysilicon layer is made, the part to be etched in the first doped polysilicon layer is etched more cleanly, and the P-type doped polysilicon layer 2 and the N-type doped polysilicon layer 3 in the gap between the first region and the second region are etched more cleanly, and the electrical performance is better. Among them, the first height difference h1 can be flexibly set according to actual needs and is not limited here.

As an embodiment of the present invention, there is a second height difference h2 between the surface of the P-type doped polysilicon layer 2 close to the silicon substrate 1 and the surface of the N-type doped polysilicon layer 3 away from the silicon substrate 1, and the surface of the P-type doped polysilicon layer 2 close to the silicon substrate 1 is farther away from the front side of the silicon substrate 1 than the surface of the N-type doped polysilicon layer 3 away from the silicon substrate 1.

In this embodiment, the surface of the P-type doped polysilicon layer 2 away from the silicon substrate 1 is farther away from the front of the silicon substrate 1 than the surface of the N-type doped polysilicon layer 3 away from the silicon substrate 1. There is a second height difference h2 between the surface of the P-type doped polysilicon layer 2 away from the silicon substrate 1 and the surface of the N-type doped polysilicon layer 3 away from the silicon substrate 1, so that the P-type doped polysilicon layer 2 and the N-type doped polysilicon layer 3 are well isolated, the electrical isolation effect is good, and the risk of short circuit or leakage is lower. The second height difference h2 can be flexibly set according to actual needs and is not limited here.

As an embodiment of the present invention, the front side of the silicon substrate 1 may also be provided with a velvet structure (not shown). The velvet structure can achieve a good light trapping effect and improve the conversion efficiency of the back contact solar cell.

As an embodiment of the present invention, a front passivation anti-reflection film layer 9 is further provided on the front side of the back-contact solar cell to further reduce light reflection, so as to further improve the conversion efficiency of the back-contact solar cell.

As an embodiment of the present invention, the back-contact solar cell further includes a back passivation film layer 5 located on the back of the P-type doped polysilicon layer 2 and the back of the N-type doped polysilicon layer 3. The metal crystals of the first metal electrode 6 pass through the back passivation film layer 5 to enter the P-type doped polysilicon layer 2, and the metal crystals of the second metal electrode 7 pass through the back passivation film layer 5 to enter the N-type doped polysilicon 3. By providing the back passivation film layer 5, the back passivation effect of the cell is further improved, so as to further improve the conversion efficiency of the back-contact solar cell.

As an embodiment of the present invention, the silicon substrate 1 is further provided with a groove 8 between the P-type doped polysilicon layer 2 and the N-type doped polysilicon layer 3. The P-type doped polysilicon layer 2 and the N-type doped polysilicon layer 3 are physically isolated by the groove 8, which can further enhance the isolation effect between the P-type doped polysilicon layer 2 and the N-type doped polysilicon layer 3, and further reduce the risk of short circuit or leakage. Among them, the width of the groove 8 can be flexibly set according to actual needs, and is not limited here.

An embodiment of the present invention further provides a battery assembly, which includes the back-contact solar cell of the above embodiment. It should be noted that the battery assembly and the back-contact solar cell have the same or similar beneficial effects, and the relevant parts between the two can be referenced to each other. In order to avoid repetition, they will not be repeated here. An embodiment of the present invention further provides a photovoltaic system, which includes the battery assembly of the above embodiment. It should be noted that the battery assembly and the back-contact solar cell have the same or similar beneficial effects, and the relevant parts between the two can be referenced to each other. In order to avoid repetition, they will not be repeated here.

A back-contact solar cell provided by an embodiment of the present invention increases the contact area between the metal crystals of the first metal electrode and the P-type doped polysilicon layer, thereby improving the contact effect between the first metal electrode and the P-type doped polysilicon layer, achieving good ohmic contact, and improving the conductivity of the first metal electrode and the P-type doped polysilicon layer, thereby improving the battery conversion efficiency.

The above are only preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims (12)

1. A back contact solar cell, comprising: A silicon substrate having a back surface and a front surface arranged opposite to each other; A P-type doped polysilicon layer, located in a first region on the back side of the silicon substrate; An N-type doped polysilicon layer is located in a second region on the back side of the silicon substrate, and the first region is different from the second region; A first metal electrode disposed in the first region and in contact with the P-type doped polysilicon layer; A second metal electrode disposed in the second region and in contact with the N-type doped polysilicon layer; Among them, the depth of metal crystals of the first metal electrode entering the P-type doped polysilicon layer is greater than the depth of metal crystals of the second metal electrode entering the N-type doped polysilicon layer; the average grain size of the P-type doped polysilicon layer is greater than the average grain size of the N-type doped polysilicon layer. 2. The back-contact solar cell according to claim 1 is characterized in that the ratio of the depth of the metal crystals of the first metal electrode penetrating into the P-type doped polysilicon layer to the depth of the metal crystals of the second metal electrode penetrating into the N-type doped polysilicon layer is 1~4 and is not equal to 1. 3. The back-contact solar cell according to claim 1 is characterized in that the ratio of the depth of the metal crystals of the first metal electrode penetrating into the P-type doped polysilicon layer to the depth of the metal crystals of the second metal electrode penetrating into the N-type doped polysilicon layer is 1~2 and is not equal to 1. 4. The back-contact solar cell according to claim 1 is characterized in that the depth of the metal crystals of the first metal electrode penetrating into the P-type doped polysilicon layer is 2~300nm; the depth of the metal crystals of the second metal electrode penetrating into the N-type doped polysilicon layer is 1~200nm. 5 . The back-contact solar cell according to claim 1 , wherein the first metal electrode and the second metal electrode both comprise silver, glass frit and organic material, and the glass frit content in the first metal electrode is greater than the glass frit content in the second metal electrode. 6 . The back-contact solar cell according to claim 1 , wherein a refractive index of the P-type doped polysilicon layer is smaller than a refractive index of the N-type doped polysilicon layer. 7. The back-contact solar cell according to claim 1 is characterized in that it also includes a back passivation film layer located on the back side of the P-type doped polysilicon layer and the back side of the N-type doped polysilicon layer, and the metal crystals of the first metal electrode pass through the back passivation film layer to enter the P-type doped polysilicon layer, and the metal crystals of the second metal electrode pass through the back passivation film layer to enter the N-type doped polysilicon. 8 . The back-contact solar cell according to claim 1 , wherein a ratio of an average grain size of the P-type doped polysilicon layer to an average grain size of the N-type doped polysilicon layer is 1 to 4 and is not equal to 1. 9 . The back-contact solar cell according to claim 1 , wherein a thickness of the N-type doped polysilicon layer is greater than a thickness of the P-type doped polysilicon layer. 10 . The back-contact solar cell according to claim 9 , wherein a ratio of a thickness of the N-type doped polysilicon layer to a thickness of the P-type doped polysilicon layer is 1-2 and is not equal to 1. 11. A battery assembly, characterized in that it comprises a back-contact solar cell as described in any one of claims 1 to 10. 12. A photovoltaic system, comprising the battery assembly according to claim 11.