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CN118380381A - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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Publication number
CN118380381A
CN118380381A CN202410377948.2A CN202410377948A CN118380381A CN 118380381 A CN118380381 A CN 118380381A CN 202410377948 A CN202410377948 A CN 202410377948A CN 118380381 A CN118380381 A CN 118380381A
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China
Prior art keywords
layer
etch stop
esl
stop layer
depositing
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Pending
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CN202410377948.2A
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Chinese (zh)
Inventor
吴彦儒
郑凯方
李承晋
张孝慷
黄心岩
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Publication date
Priority claimed from US18/349,672 external-priority patent/US20240332070A1/en
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN118380381A publication Critical patent/CN118380381A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76832—Multiple layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Layout of the interconnection structure
    • H01L23/5283—Cross-sectional geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H01L23/53295—Stacked insulating layers

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The method according to the present disclosure comprises: receiving a workpiece comprising a first conductive component embedded in a first dielectric layer; selectively depositing a capping layer over the first conductive feature; depositing a first Etch Stop Layer (ESL) over the capping layer; depositing an adhesive layer over the first ESL; depositing a second ESL over the adhesive layer; depositing a second dielectric layer over the second ESL; forming an opening through the second dielectric layer, the second ESL, the adhesive layer, and the first ESL to expose the capping layer; and forming a second conductive member in the opening. The density of the second ESL is greater than the density of the first ESL. According to other embodiments of the present application, semiconductor structures and methods of forming the same are also provided.

Description

Semiconductor structure and forming method thereof
Technical Field
Embodiments of the present application relate to semiconductor structures and methods of forming the same.
Background
The electronic industry is continually growing in demand for smaller and faster electronic devices capable of supporting more, more and more complex and advanced functions at the same time. Accordingly, in the semiconductor industry, there is a continuing trend to manufacture low cost, high performance, and low power Integrated Circuits (ICs). Up to now, these objectives have been largely achieved by scaling down the semiconductor IC size (e.g., minimum component size), thereby improving production efficiency and reducing associated costs. However, such scaling also increases the complexity of the semiconductor manufacturing process. Accordingly, similar advances in semiconductor manufacturing processes and techniques are needed to realize continued advances in semiconductor ICs and devices.
As device dimensions continue to shrink, the back-end-of-line interconnect structures may account for more than half of the parasitic capacitance of the IC chip, which may translate into dynamic power losses of more than 50%. For patterning purposes, the interconnect structure includes various dielectric layers of different properties. There is a need to reduce dynamic power loss due to the different dielectric layers in the interconnect structure.
Disclosure of Invention
According to one embodiment of the present application, there is provided a method of forming a semiconductor structure, comprising: receiving a workpiece comprising a first conductive component embedded in a first dielectric layer; selectively depositing a capping layer over the first conductive feature; depositing a first Etch Stop Layer (ESL) over the capping layer; depositing an adhesion layer over the first etch stop layer; depositing a second etch stop layer over the adhesion layer; depositing a second dielectric layer over the second etch stop layer; forming an opening through the second dielectric layer, the second etch stop layer, the adhesion layer and the first etch stop layer to expose the capping layer; and forming a second conductive feature in the opening, wherein a density of the second etch stop layer is greater than a density of the first etch stop layer.
According to another embodiment of the present application, there is provided a method of forming a semiconductor structure, including: receiving a workpiece comprising a first conductive component embedded in a first dielectric layer; selectively depositing a capping layer over the first conductive feature; depositing a first Etch Stop Layer (ESL) over the capping layer using a first Plasma Enhanced Chemical Vapor Deposition (PECVD) process; depositing an adhesion layer over the first etch stop layer; depositing a second etch stop layer over the adhesion layer using a second plasma enhanced chemical vapor deposition process; depositing a second dielectric layer over the second etch stop layer; forming an opening through the second dielectric layer, the second etch stop layer, the adhesion layer and the first etch stop layer to expose the capping layer; and forming a second conductive feature in the opening, wherein each of the first and second plasma enhanced chemical vapor deposition processes includes a high frequency pulse and a low frequency pulse, wherein in the first plasma enhanced chemical vapor deposition process, a plasma of a nitrogen-containing precursor is introduced during the high frequency pulse, wherein in the second plasma enhanced chemical vapor deposition process, a plasma of a nitrogen-containing precursor is introduced during the high frequency pulse and the low frequency pulse.
According to yet another embodiment of the present application, there is provided a semiconductor structure including: a first conductive member disposed in the first dielectric layer; a cover layer disposed on the first conductive member; a first Etch Stop Layer (ESL) disposed over and in contact with the top surfaces of the capping layer and the first dielectric layer; an adhesive layer disposed on the first etch stop layer; a second etch stop layer disposed on the adhesive layer; a second dielectric layer over the second etch stop layer; and a second conductive member extending through the second dielectric layer, the second etch stop layer, the adhesive layer, and the second etch stop layer to contact the capping layer, wherein a density of the second etch stop layer is greater than a density of the first etch stop layer.
Embodiments of the present application relate to an etch stop layer for an interconnect structure.
Drawings
Aspects of the disclosure may be best understood from the following detailed description when read in connection with the accompanying drawings. It should be noted that the various components are not drawn to scale according to standard practice in the industry. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
Fig. 1 is a flow chart of a method of forming a contact structure in accordance with one or more aspects of the present disclosure.
Fig. 2-14 are partial cross-sectional views of a workpiece at various stages of manufacture according to the method of fig. 1, in accordance with one or more aspects of the present disclosure.
Detailed Description
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component over or on a second component may include embodiments in which the first component and the second component are formed in direct contact, and may also include embodiments in which additional components may be formed between the first component and the second component, such that the first component and the second component may not be in direct contact. Further, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the embodiments and/or configurations discussed.
In addition, spatially relative terms such as "below …," "below …," "lower," "above …," "upper," and the like may be used herein for ease of description to describe one element or component's relationship to another element or component as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise positioned (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
In addition, when numerical values or numerical ranges are described by "about," "approximately," etc., the term is intended to cover numerical values within a reasonable range that takes into account variations inherently present during manufacture as understood by one of ordinary skill in the art. For example, a value or range of values encompasses a reasonable range including the recited value, such as within +/-10% of the recited value, based on known manufacturing tolerances associated with manufacturing components having characteristics associated with the value. For example, a material layer having a thickness of "about 5nm" may include a size range from 4.25nm to 5.75nm, wherein the manufacturing tolerances associated with depositing the material layer are +/-15% as known to one of ordinary skill in the art.
As device sizes continue to shrink, industry strives to keep pace with moore's law. As front-end-of-line (FEOL) devices become smaller, back-end-of-line (BEOL) interconnect structures play a greater role in maintaining switch speed rise and power consumption reduction. For example, BEOL interconnect structures may include low-k dielectric layers to keep parasitic capacitance reduced. To achieve etch endpoint detection, a more etch resistant Etch Stop Layer (ESL) may be employed to provide different etch rates. However, greater etch resistance is typically accompanied by a greater dielectric constant. As a result, the use of an etch stop layer may result in an increase in parasitic capacitance. This dilemma presents a challenge in lowering the dielectric constant of the ESL. Furthermore, it is desirable for the etch stop layer to have moisture barrier properties. An oxygen-containing etch stop layer formed using a carbon dioxide plasma may provide satisfactory moisture barrier capability. However, the use of carbon dioxide plasma may lead to oxidation problems.
The present disclosure provides methods of forming an Etch Stop Layer (ESL) structure comprising a low density, low dielectric constant dielectric layer bonded to a high density dielectric layer by an adhesive layer. The low density, low dielectric constant dielectric layer helps reduce parasitic capacitance. The high density dielectric layer acts as a hermetic moisture barrier. The adhesion layer improves the adhesion of the low density, low dielectric constant dielectric layer and the high density dielectric layer.
Various aspects of the disclosure will now be described in more detail with reference to the accompanying drawings. In this regard, fig. 1 is a flow chart illustrating a method 100 of forming a contact structure on a workpiece 200. The method 100 is merely an example and is not intended to limit the present disclosure to what is explicitly shown in the method 100. Additional steps may be provided before, during, and after the method 100, and some of the steps described may be replaced, eliminated, or rearranged for additional embodiments of the method. For simplicity, not all steps are described in detail herein. The method 100 is described below in connection with fig. 2-14, with fig. 2-14 being partial cross-sectional views of a workpiece 200 at different stages of manufacture according to an embodiment of the method 100. Since the workpiece 200 will be manufactured into the semiconductor structure 200 at the end of the manufacturing process, the workpiece 200 may be referred to as the semiconductor structure 200, depending on the context. Furthermore, throughout the present application and the various embodiments, the same reference numerals refer to the same parts having similar structures and compositions unless otherwise specified. Depending on the context, the source/drain regions may refer to either the source or the drain, either individually or collectively.
Referring to fig. 1 and 2, the method 100 includes a block 102 in which a workpiece 200 is received, the workpiece 200 including contacts 204 disposed in a first dielectric layer 202. The contacts 204 include copper (Cu), cobalt (Co), nickel (Ni), ruthenium (Ru), or tungsten (W), and may be metal lines, contact vias, or source/drain contacts. The first dielectric layer 202 may be an inter-layer dielectric (ILD) layer or an inter-metal dielectric (IMD) layer. In some embodiments, the first dielectric layer 202 may include silicon oxide or a low-k dielectric material having a k value (dielectric constant) less than the k value of silicon oxide (about 3.9). In some embodiments, the low-k dielectric material includes a porous organosilicate film (e.g., siOCH), tetraethylorthosilicate (TEOS) oxide, undoped silicate glass, borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), phosphosilicate glass (PSG), fluorine-doped silica, carbon-doped silica, porous carbon-doped silica, silicon oxynitride (SiOCN), spin-on silicon-based polymer dielectric, or a combination thereof. Although not explicitly shown in the figures, the contact 204 may be spaced apart from the first dielectric layer 202 by a barrier layer. The barrier layer may include titanium nitride, cobalt nitride, manganese nitride, nickel nitride, tungsten nitride, or tantalum nitride.
Referring to fig. 1 and 2, the method 100 includes a block 104 in which a second dielectric layer 206 is deposited over the workpiece 200. In some embodiments, the composition of the second dielectric layer 206 may be similar to the composition of the first dielectric layer 202. In some embodiments, the second dielectric layer 206 may be deposited over the contacts 204 and the first dielectric layer 202 using spin coating, chemical Vapor Deposition (CVD), or Flowable Chemical Vapor Deposition (FCVD). In some cases, an annealing process may be performed to improve the quality of the second dielectric layer 206 in order to improve the quality and density of the second dielectric layer 206 to withstand subsequent patterning operations. After depositing the second dielectric layer 206, a planarization process, such as a Chemical Mechanical Polishing (CMP) process, may be performed on the second dielectric layer 206 to provide a planar top surface.
Referring to fig. 1 and 2, the method 100 includes a block 106 in which the second dielectric layer 206 is patterned to form openings. Referring to fig. 2, the second dielectric layer 206 may be patterned using a combination of a photolithography process and an etching process. In an example process, a hard mask may be deposited over the second dielectric layer 206, and a photoresist layer may be deposited over the hard mask. The photoresist layer may be a single layer or multiple layers. To pattern the photoresist layer, the photoresist layer is exposed to radiation reflected or transmitted from the photomask, baked in a post-exposure bake process, developed in a development process, and rinsed. Thereby, the pattern of the photomask is transferred to the photoresist layer. The patterned photoresist layer is used as an etch mask to etch the hard mask, thereby forming a patterned hard mask. The patterned hard mask is then used as an etch mask to pattern the underlying second dielectric layer 206. In some embodiments, the etching at block 106 may be a dry etching process. For example, the dry etching process may employ oxygen-containing gases, hydrogen gases, fluorine-containing gases (e.g., ,CF4、SF6、CH2F2、CHF3、CH3F、C4H8、C4F6 and/or C 2F6), carbon-containing gases (e.g., CO, CH 4, and/or C 3H8), chlorine-containing gases (e.g., cl 2、CHCl3、CCl4 and/or BCl 3), bromine-containing gases (e.g., HBr and/or CHBR 3), iodine-containing gases, other suitable gases and/or plasmas, and/or combinations thereof. As shown in fig. 2, at least one opening reaches and exposes the top surface of the contact 204.
Referring to fig. 1 and 2, the method 100 includes a block 108 in which a first barrier layer 208 and a first metal fill layer 210 are deposited over the opening. In some embodiments, the first barrier layer 208 comprises a metal nitride, such as titanium nitride, cobalt nitride, manganese nitride, nickel nitride, tungsten nitride, or tantalum nitride. In one embodiment, the first barrier layer 208 comprises tantalum nitride. Although tantalum nitride is less conductive than some other metal nitrides, it has better barrier properties, which allows it to have a smaller thickness and still effectively act as a barrier. The first barrier layer 208 may be deposited using Chemical Vapor Deposition (CVD), plasma Enhanced CVD (PECVD), atomic Layer Deposition (ALD), or Plasma Enhanced ALD (PEALD). The precursors used to deposit the first barrier layer 208 may include metal-containing metal-organic precursors and nitrogen-containing precursors. For example, when the first barrier layer 208 comprises tantalum nitride, the precursors used may comprise pentakis (dimethylamino) tantalum (PDMAT) or t-butylimino-tris (dimethylamino) tantalum (TBDMT) as metal-containing metal-organic precursors and ammonia or monomethyl hydrazine (MMH) as nitrogen-containing precursors. The metal fill layer 210 may include copper (Cu), cobalt (Co), nickel (Ni), ruthenium (Ru), or tungsten (W). In one embodiment, the metal fill layer 210 includes copper (Cu). PVD, electroplating, or electroless plating may be used to deposit the metal fill layer 210. As an example, electroplating may be used to deposit the metal fill layer 210. In this example process, a seed layer may be deposited over the workpiece 200 using PVD or CVD. The seed layer may comprise titanium, copper, or both. Electroplating is then used to deposit copper over the seed layer.
Referring to fig. 1 and 3, the method 100 includes a block 110 in which the workpiece 200 is planarized to expose the second dielectric layer 206 to form lower conductive features 2102, 2104, and 2106. Planarization at block 110 may include Chemical Mechanical Polishing (CMP). As shown in fig. 3, the workpiece 200 is planarized until the planar top surface of the workpiece 200 includes the top surfaces of the second dielectric layer 206, the first barrier layer 208, and the metal fill layer 210. In the partial cross-sectional view shown in fig. 3, planarization forms a first lower conductive member 2102, a second lower conductive member 2104, and a third lower conductive member 2106. The first lower conductive member 2102, the second lower conductive member 2104, and the third lower conductive member 2106 may include metal lines, contact vias, or both. In the embodiment shown in fig. 3, second lower conductive element 2104 is physically and electrically coupled to contact 204.
Referring to fig. 1, 9, and 10, the method 100 may optionally include a block 112 in which the second dielectric layer 206 is replaced with a third dielectric layer 230. In some embodiments, the second dielectric layer 206 is removed and replaced with a dielectric structure having a lower dielectric constant. In the embodiment shown in fig. 9, the second dielectric layer 206 may be selectively removed using a selective wet etch process. For example, when the second dielectric layer 206 comprises silicon oxide, the selective wet etch process may include the use of ammonium fluoride (NH 4 F) and hydrofluoric acid (HF). After selective removal of the second dielectric layer 206, a third dielectric layer 230 may be deposited using CVD. Because the deposition of the third dielectric layer 230 may merge over the opening, leaving a void formed by the removal of the second dielectric layer 206, an air gap 232 (or void 232) may be formed in the third dielectric layer 230. The presence of the air gap 232 helps to reduce the overall dielectric constant of the third dielectric layer 230 even when the composition of the third dielectric layer 230 is the same as the composition of the second dielectric layer 206. In some embodiments, the third dielectric layer 230 may include silicon oxide or silicon oxynitride.
Referring to fig. 1 and 4, method 100 includes block 114 in which a capping layer 212 is selectively deposited over top surfaces of lower conductive features 2102, 2104, and 2106. Capping layer 212 may also be referred to as a metal cap 212 or conductive cap 212 and is formed of a metal that is different from the metal forming the conductive members (including first lower conductive member 2102, second lower conductive member 2104, and third lower conductive member 2106). In embodiments where lower conductive members 2102, 2104, and 2106 are formed of copper, capping layer 212 may include titanium (Ti), tantalum (Ta), molybdenum (Mo), nickel (Ni), cobalt (Co), ruthenium (Ru), or other refractory metals. In the depicted embodiment, the capping layer 212 includes cobalt (Co). In some embodiments, capping layer 212 is selectively deposited on top of first lower conductive feature 2102, second lower conductive feature 2104, and third lower conductive feature 2106 by CVD using metal organic precursors, each having metal ions and coordinating ligands. An example cobalt metal organic precursor may be cobalt cyclopentadienyl (C 5H5)Co(CO)2. As shown in FIG. 4, the capping layer 212 is deposited only on the lower conductive features 2102, 2104, and 2106 due to the selectivity of formation, and is not present on the surface of the second dielectric layer 206. When the operation at block 112 is performed, the second dielectric layer 206 is replaced with a third dielectric layer 230. In addition to functioning as a diffusion barrier, the capping layer 212 may also repair damage to the lower conductive features 2102, 2104, and 2106 during planarization. In some alternative embodiments, the capping layer 212 may comprise graphene.
Referring to fig. 1 and 5, the method 100 includes a block 116 in which a first Etch Stop Layer (ESL) 214 is deposited over the workpiece 200. The first ESL 214 comprises an oxygen free dielectric material. In some embodiments, the first ESL 214 comprises a low-k dielectric material such as silicon carbonitride (SiCN), and may be deposited using CVD, atomic Layer Deposition (ALD), plasma Enhanced CVD (PECVD), plasma Enhanced ALD (PEALD). The precursor used to deposit the first ESL 214 may include a first precursor comprising silicon and carbon and a second precursor comprising nitrogen. Examples of the first precursor include tetramethylsilane (Si (CH 3)4), and examples of the second precursor include ammonia (NH 3). Because the first ESL 214 does not contain oxygen atoms, its deposition process does not involve the use of a plasma of carbon dioxide (CO 2), thereby reducing oxidation problems. In some embodiments, the first ESL 214 includes about 30% to 60% silicon (Si), about 25% to 60% carbon (C), and about 10% to 20% nitrogen (N). In some embodiments, the dielectric constant of the first ESL 214 is between about 3.5 and about 4.5. When the dielectric constant of the first ESL 214 is less than 3.5, the first ESL 214 may not have the etch resistant properties required to act as an etch stop layer. When the dielectric constant of the first ESL 214 is greater than 4.5, its contribution to capacitance reduction may be negligibleAnd about (f)Between them. When the first ESL 214 ratio isWhen thick, the total thickness of the ESL may be too high to affect device size. When the first ESL 214 ratio isWhen thin, the contribution of the first ESL 214 to the capacitance reduction may not be sufficient to justify the added process steps. The fact that the first ESL 214 does not contain oxygen atoms may be contrary to some conventional wisdom. In some techniques, similarly positioned etch stop layers may include silicon oxycarbide or oxygen doped silicon carbide, as oxygen treatments (such as carbon dioxide plasma treatments) have been shown to increase the density and moisture barrier capability of the etch stop layer. Note that while the first ESL 214 is thinner than the second ESL 218 (as will be described below) when the former is used as a moisture barrier, the first ESL 214 is located on top of the metal lines and contributes more to the total capacitance. Simulation results and experiments show that by lowering the dielectric constant of the first ESL 214, the total capacitance can be effectively reduced.
Referring to fig. 1 and 6, the method 100 includes a block 118 in which an adhesive layer 216 is deposited over the first ESL 214. The adhesion layer 216 may be aluminum nitride (AlN) or a silicon-rich material. When the adhesive layer 216 comprises aluminum nitride (AlN), the adhesive layer 216 may be deposited using a plurality of thermal ALD cycles at a temperature between about 300c and about 400 c, and the deposition of the adhesive layer 216 may include the use of an aluminum-containing precursor, such as trimethylaluminum (Al (CH 3)3)), and a nitrogen-containing precursor, such as ammonia (NH 3), when the adhesive layer 216 comprises a silicon-rich material, the adhesive layer 216 may be deposited by CVD using a silicon-containing precursor, such as silane (SiH 4), and a nitrogen-containing precursor, such as ammonia (NH 3), when the adhesive layer 216 comprises a silicon-rich material, the adhesive layer 216 may be deposited in the same chamber as the first ESL 214 and the second ESL 218 (to be described below), when the adhesive layer 216 comprises AlN, the adhesive layer 216 may not be deposited in the same chamber as the first ESL 214 and the second ESL 218 (to be described below). When the adhesive layer 216 comprises a silicon-rich material, the adhesion between the two separate layers may be improved, such as to provide a low-adhesion, such as to a low-k adhesion, and a low-loss adhesion, such as may be achieved by a low-on-to-carbon adhesion, and a low-carbon-barrier layer, as a low-adhesion, and a low-adhesion, such as a low-moisture-loss test, when the adhesion, may be performed as a low-on the first ESL layer, and a low-adhesion, for example, as a low-adhesion-loss test, the thickness of the adhesive layer 216 may be aboutAnd about (f)Between them. When the adhesive layer 216 ratioWhen thin, such thickness is insufficient to improve adhesion. Since the dielectric constant of the adhesive layer 216 is greater than that of the first ESL 214 or the second ESL 218, when the adhesive layer 216 is thicker thanWhen thick, it may not achieve the goal of reducing capacitance. For example, when the adhesion layer 216 comprises aluminum nitride, its dielectric constant is about 8.9, which is much higher than the dielectric constant of the first ESL 214 or the second ESL 218.
Referring to fig. 1 and 7, the method 100 includes a block 120 in which a second ESL 218 is deposited over the adhesive layer 216. The second ESL 218 comprises an oxygen free dielectric material. In some embodiments, the second ESL 218 may also include silicon carbonitride (SiCN) and be deposited in such a way that it may act as an air barrier against moisture ingress. Although the second ESL 218 may be similar in composition to the first ESL 214, the second ESL 218 is deposited by means of a low frequency plasma at a frequency between about 200KHz and about 600 KHz. For comparison purposes, the high frequency plasma may have a frequency between about 10MHz and about 20 MHz. For example, the nitrogen-containing precursor may be supplied during the high frequency pulse and the low frequency pulse when the second ESL 218 is deposited, but may be supplied only during the high frequency pulse when the first ESL 214 is deposited. During deposition of the second ESL 218, the low frequency plasma enhances ion bombardment, thereby densifying the second ESL 118. For the avoidance of doubt, low frequency plasma is not used when depositing the first ESL 214. As a result, the density of the second ESL 218 is greater than the density of the first ESL 214. In some embodiments, the density of the first ESL 214 may be between about 1.5g/cm 3 and about 1.8g/cm 3, and the density of the second ESL 218 may be between about 1.8g/cm 3 and about 2.0g/cm 3. The dielectric constant of the denser second ESL 218 is greater than the dielectric constant of the first ESL 214. In some embodiments, the dielectric constant of the second ESL 218 may be between about 4.5 and about 5.5. To achieve a satisfactory moisture barrier effect, the second ESL 218 may be thicker than the first ESL 214. In some embodiments, the second ESL 218 has a value of aboutAnd about (f)And a thickness therebetween.
Referring to fig. 1 and 12, the method 100 may optionally include a block 122 in which a third ESL 220 is deposited over the second ESL 218. The third ESL 220 comprises a metal oxide. In some embodiments, the third ESL 220 may comprise aluminum oxide. At block 122, a third ESL 220 may be deposited using CVD, ALD, PECVD or PEALD. The third ESL 220 has a greater dielectric constant and a higher etch resistance than the first ESL 214 and the second ESL 218. For example, when the third ESL 220 comprises alumina, the dielectric constant of the third ESL 220 may be between about 9 and about 10, which is about or greater than twice the dielectric constant of the first ESL 214 or the second ESL 218. When the third ESL 220 is employed, the third ESL 220 provides better control of the Critical Dimension (CD). To reduce the dielectric constant effect of the third ESL 220, the thickness of the third ESL 220 may be less than the thickness of the first ESL 214 or the second ESL 218. In some embodiments, when a third ESL 220 is employed, the third ESL 220 may have aboutAnd about (f)And a thickness therebetween.
Referring to fig. 1, 8, 11, 13, and 14, the method 100 includes a block 124 in which a fourth dielectric layer 222 is deposited over the workpiece 200. After the second ESL 218 is deposited (or after the third ESL 220 is optionally deposited), a fourth dielectric layer 222 is deposited over the workpiece 200. In some embodiments, fourth dielectric layer 222 may include silicon oxide or a low-k dielectric material having a k value (dielectric constant) less than the k value of silicon oxide (about 3.9). In some embodiments, the low-k dielectric material includes a porous organosilicate film (e.g., siOCH), tetraethylorthosilicate (TEOS) oxide, undoped silicate glass, borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), phosphosilicate glass (PSG), fluorine-doped silica, carbon-doped silica, porous carbon-doped silica, silicon oxynitride (SiOCN), spin-on silicon-based polymer dielectric, or a combination thereof. In the embodiment shown in fig. 8, 11 and 13, a fourth dielectric layer 222 is deposited over the second ESL 218 and in contact with the second ESL 218. In other embodiments shown in fig. 14, when a third ESL 220 is employed, a fourth dielectric layer 222 is deposited over the third ESL 220 and in contact with the third ESL 220.
Referring to fig. 1, 8, 11, 13, and 14, the method 100 includes a block 126 in which upper metal lines 226 and metal contact vias 224 are formed. At block 126, at least one upper opening is formed through the fourth dielectric layer 222, the third ESL 220 (shown in fig. 13 when the third ESL 220 is employed), the second ESL 218, the adhesive layer 216, and the first ESL 214 to expose the cover layer 212 of the at least one lower conductive feature. In the embodiment shown in fig. 8, 11, 13 and 14, the opening exposes cover layer 212 on second lower conductive element 2104. The fourth dielectric layer 222 may be patterned using a combination of a photolithography process and an etching process. In an example process, a hard mask may be deposited over the fourth dielectric layer 222, and a photoresist layer may be deposited over the hard mask. The photoresist layer may be a single layer or multiple layers. To pattern the photoresist layer, the photoresist layer is exposed to radiation reflected or transmitted from the photomask, baked in a post-exposure bake process, developed in a development process, and rinsed. Thereby, the pattern of the photomask is transferred to the photoresist layer. The patterned photoresist layer is used as an etch mask to etch the hard mask, thereby forming a patterned hard mask. The patterned hard mask is then used as an etch mask to pattern the underlying fourth dielectric layer 222. In some embodiments, the etching at block 106 may be a dry etching process. For example, the dry etching process may employ oxygen-containing gases, hydrogen gases, fluorine-containing gases (e.g., ,CF4、SF6、CH2F2、CHF3、CH3F、C4H8、C4F6 and/or C 2F6), carbon-containing gases (e.g., CO, CH 4, and/or C 3H8), chlorine-containing gases (e.g., cl 2、CHCl3、CCl4 and/or BCl 3), bromine-containing gases (e.g., HBr and/or CHBR 3), iodine-containing gases, other suitable gases and/or plasmas, and/or combinations thereof. As shown in fig. 8, 11, 13 and 14, at least one upper opening reaches and exposes cover layer 212 over second lower conductive feature 2104.
After forming the opening in the fourth dielectric layer 222, a second barrier layer 225 may be deposited over the workpiece 200 (including over the sidewalls of the opening and over the top surface of the fourth dielectric layer 222). In some embodiments, the second barrier layer 225 comprises a metal nitride, such as titanium nitride, cobalt nitride, manganese nitride, nickel nitride, tungsten nitride, or tantalum nitride. In one embodiment, the second barrier layer 225 comprises tantalum nitride. Although tantalum nitride is less conductive than some other metal nitrides, it has better barrier properties, which allows it to have a smaller thickness and still effectively act as a barrier. The second barrier layer 225 may be deposited using Chemical Vapor Deposition (CVD), plasma Enhanced CVD (PECVD), atomic Layer Deposition (ALD), or Plasma Enhanced ALD (PEALD). The precursors for depositing the second barrier layer 225 may include metal-containing metal-organic precursors and nitrogen-containing precursors. For example, when the second barrier layer 225 comprises tantalum nitride, the precursors used may comprise pentakis (dimethylamino) tantalum (PDMAT) or t-butylimino-tris (dimethylamino) tantalum (TBDMT) as metal-containing metal-organic precursors and ammonia or monomethyl hydrazine (MMH) as nitrogen-containing precursors.
After depositing the second barrier layer 225, a metal fill layer is deposited over the second barrier layer 225 to form a metal contact via 224 disposed in the opening and an upper metal line 226 disposed over the metal contact via 224. The metal fill layer may include copper (Cu), cobalt (Co), nickel (Ni), ruthenium (Ru), or tungsten (W). In one embodiment, the metal fill layer comprises copper (Cu). PVD, electroplating, or electroless plating may be used to deposit the metal fill layer. As an example, at block 126, electroplating may be used to deposit a metal fill layer. In this example process, a seed layer may be deposited over the workpiece 200 using PVD or CVD. The seed layer may comprise titanium, copper, or both. Electroplating is then used to deposit copper over the seed layer.
Each of fig. 8, 11, 13, and 14 illustrates a final semiconductor structure 200 fabricated using the method 100 of fig. 1, depending on whether optional operations at blocks 112 and 122 are performed or not. Referring to fig. 8, each of first lower conductive member 2102, second lower conductive member 2104, and third lower conductive member 2106 is embedded in second dielectric layer 206 and surrounded by second dielectric layer 206. Each of the first lower conductive member 2102, the second lower conductive member 2104, and the third lower conductive member 2106 is covered by a cover layer 212, which cover layer 212 may include cobalt (Co). The first ESL 214 is deposited over the top surface of the second dielectric layer 206 and the top surface of the capping layer 212 on each of the first lower conductive feature 2102, the second lower conductive feature 2104, and the third lower conductive feature 2106, and in contact with the top surfaces of the second dielectric layer 206 and the capping layer 212. The second ESL 218 is disposed above the first ESL 214. The adhesive layer 216 is sandwiched directly between the first ESL 214 and the second ESL 218 along the Z-direction (i.e., the vertical direction) to improve adhesion therebetween. The improved adhesion is shown to increase the moisture barrier capability of the first and second ESLs 214 and 218. When the first ESL 214 and the second ESL 218 comprise silicon carbonitride, they may be collectively referred to as a silicon carbonitride bilayer. In both, the first ESL 214 may be deposited without ion bombardment from a low frequency ammonia plasma, while the second ESL 218 may be deposited with ion bombardment from a low frequency ammonia plasma. As a result, the second ESL 218 has a greater density and a greater dielectric constant than the first ESL 214. Simulation results indicate that the use of a silicon carbonitride bilayer (i.e., first ESL 214 and second ESL 218) may result in a capacitance reduction between 4.5% and about 5.5%.
In contrast to the semiconductor structure 200 in fig. 8, the second dielectric layer 206 in the counterpart in fig. 11 is replaced by a third dielectric layer 230. Because of the confined space between first lower conductive element 2102, second lower conductive element 2104, and third lower conductive element 2106, third dielectric layer 230 may prematurely merge over the opening, resulting in void 232. Because the gas species in the void 232 has a dielectric constant close to 1, the overall dielectric constant of the third dielectric layer 230 and the void 232 is less than the dielectric constant of the second dielectric layer 206. Replacing the second dielectric layer 206 with the third dielectric layer 230 may further reduce the parasitic capacitance of the semiconductor structure 200 in fig. 11.
In contrast to the semiconductor structure 200 in fig. 8, the counterpart in fig. 13 further includes a third ESL 220 disposed directly on top of the second ESL 218. The third ESL 220 comprises a metal oxide that is more etch resistant than the second ESL 218. The third ESL 220 helps control the critical dimension when patterning the upper opening through the ESL layer.
In contrast to the semiconductor structure 200 in fig. 11, the counterpart in fig. 14 further includes a third ESL 220 disposed directly on top of the second ESL 218. The third ESL 220 comprises a metal oxide that is more etch resistant than the second ESL 218. The third ESL 220 helps control the critical dimension when patterning the upper opening through the ESL layer.
Accordingly, one of the embodiments of the present disclosure provides a method. The method comprises the following steps: receiving a workpiece comprising a first conductive component embedded in a first dielectric layer; selectively depositing a capping layer over the first conductive feature; depositing a first Etch Stop Layer (ESL) over the capping layer; depositing an adhesive layer over the first ESL; depositing a second ESL over the adhesive layer; depositing a second dielectric layer over the second ESL; forming an opening through the second dielectric layer, the second ESL, the adhesive layer, and the first ESL to expose the capping layer; and forming a second conductive member in the opening. The density of the second ESL is greater than the density of the first ESL.
In some embodiments, the adhesion layer comprises aluminum nitride or silicon nitride. In some embodiments, the first ESL and the second ESL comprise silicon carbonitride. In some cases, the dielectric constant of the second ESL is greater than the dielectric constant of the first ESL. In some embodiments, the method further comprises: a third ESL is deposited over the second ESL prior to depositing the second dielectric layer. The third ESL comprises alumina. In some embodiments, the method further comprises replacing the first dielectric layer with a third dielectric layer after selectively depositing the capping layer. In some embodiments, the third dielectric layer includes an air gap.
In another embodiment, a method is provided. The method comprises the following steps: receiving a workpiece comprising a first conductive component embedded in a first dielectric layer; selectively depositing a capping layer over the first conductive feature; depositing a first Etch Stop Layer (ESL) over the capping layer using a first Plasma Enhanced Chemical Vapor Deposition (PECVD) process; depositing an adhesive layer over the first ESL; depositing a second ESL over the adhesion layer using a second PECVD process; depositing a second dielectric layer over the second ESL; forming an opening through the second dielectric layer, the second ESL, the adhesive layer, and the first ESL to expose the capping layer; and forming a second conductive member in the opening. Each of the first and second PECVD processes includes a high frequency pulse and a low frequency pulse. In a first PECVD process, a plasma of a nitrogen-containing precursor is introduced during the high frequency pulse. In a second PECVD process, a plasma of a nitrogen-containing precursor is introduced during the high frequency pulse and the low frequency pulse.
In some embodiments, the first ESL and the second ESL comprise silicon carbonitride. In some embodiments, the density of the second ESL is greater than the density of the first ESL. In some embodiments, the dielectric constant of the second ESL is greater than the dielectric constant of the first ESL. In some cases, the capping layer includes cobalt or graphene. In some embodiments, the method further comprises: a third ESL is deposited over the second ESL prior to depositing the second dielectric layer. In some embodiments, the third ESL comprises aluminum oxide. In some embodiments, the capping layer comprises aluminum nitride. In some cases, selectively depositing the capping layer includes an Atomic Layer Deposition (ALD) process that includes using trimethylaluminum (Al (CH 3)3) and ammonia (NH 3).
In yet another embodiment, a semiconductor structure is provided. The semiconductor structure includes: a first conductive member disposed in the first dielectric layer; a cover layer disposed on the first conductive member; a first Etch Stop Layer (ESL) disposed over and in contact with the top surfaces of the capping layer and the first dielectric layer; an adhesive layer disposed on the first ESL; a second ESL disposed on the adhesive layer; a second dielectric layer over the second ESL; and a second conductive member extending through the second dielectric layer, the second ESL, the adhesive layer, and the second ESL to contact the cover layer. The density of the second ESL is greater than the density of the first ESL.
In some embodiments, the adhesion layer comprises aluminum nitride or silicon nitride. In some embodiments, the dielectric constant of the second ESL is greater than the dielectric constant of the first ESL. In some cases, the first ESL and the second ESL comprise silicon carbonitride.
According to one embodiment of the present application, there is provided a method of forming a semiconductor structure, comprising: receiving a workpiece comprising a first conductive component embedded in a first dielectric layer; selectively depositing a capping layer over the first conductive feature; depositing a first Etch Stop Layer (ESL) over the capping layer; depositing an adhesion layer over the first etch stop layer; depositing a second etch stop layer over the adhesion layer; depositing a second dielectric layer over the second etch stop layer; forming an opening through the second dielectric layer, the second etch stop layer, the adhesion layer and the first etch stop layer to expose the capping layer; and forming a second conductive feature in the opening, wherein a density of the second etch stop layer is greater than a density of the first etch stop layer. In some embodiments, the adhesion layer comprises aluminum nitride or silicon nitride. In some embodiments, the first etch stop layer and the second etch stop layer comprise silicon carbonitride. In some embodiments, the dielectric constant of the second etch stop layer is greater than the dielectric constant of the first etch stop layer. In some embodiments, the method of forming a semiconductor structure further comprises: a third etch stop layer is deposited over the second etch stop layer prior to depositing the second dielectric layer, wherein the third etch stop layer comprises aluminum oxide. In some embodiments, the method of forming a semiconductor structure further comprises: after selectively depositing the cover layer, the first dielectric layer is replaced with a third dielectric layer. In some embodiments, the third dielectric layer includes an air gap.
According to another embodiment of the present application, there is provided a method of forming a semiconductor structure, including: receiving a workpiece comprising a first conductive component embedded in a first dielectric layer; selectively depositing a capping layer over the first conductive feature; depositing a first Etch Stop Layer (ESL) over the capping layer using a first Plasma Enhanced Chemical Vapor Deposition (PECVD) process; depositing an adhesion layer over the first etch stop layer; depositing a second etch stop layer over the adhesion layer using a second plasma enhanced chemical vapor deposition process; depositing a second dielectric layer over the second etch stop layer; forming an opening through the second dielectric layer, the second etch stop layer, the adhesion layer and the first etch stop layer to expose the capping layer; and forming a second conductive feature in the opening, wherein each of the first and second plasma enhanced chemical vapor deposition processes includes a high frequency pulse and a low frequency pulse, wherein in the first plasma enhanced chemical vapor deposition process, a plasma of a nitrogen-containing precursor is introduced during the high frequency pulse, wherein in the second plasma enhanced chemical vapor deposition process, a plasma of a nitrogen-containing precursor is introduced during the high frequency pulse and the low frequency pulse. In some embodiments, the first etch stop layer and the second etch stop layer comprise silicon carbonitride. In some embodiments, the density of the second etch stop layer is greater than the density of the first etch stop layer. In some embodiments, the dielectric constant of the second etch stop layer is greater than the dielectric constant of the first etch stop layer. In some embodiments, the capping layer comprises cobalt or graphene. In some embodiments, the method of forming a semiconductor structure further comprises: a third etch stop layer is deposited over the second etch stop layer prior to depositing the second dielectric layer. In some embodiments, the third etch stop layer comprises aluminum oxide. In some embodiments, the capping layer comprises aluminum nitride. In some embodiments, selectively depositing the capping layer includes an Atomic Layer Deposition (ALD) process including using trimethylaluminum (Al (CH 3)3) and ammonia (NH 3).
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art will appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims (10)

1.A method of forming a semiconductor structure, comprising:
Receiving a workpiece comprising a first conductive feature embedded in a first dielectric layer;
Selectively depositing a capping layer over the first conductive feature;
Depositing a first etch stop layer over the cap layer;
depositing an adhesion layer over the first etch stop layer;
depositing a second etch stop layer over the adhesion layer;
depositing a second dielectric layer over the second etch stop layer;
forming an opening through the second dielectric layer, the second etch stop layer, the adhesion layer, and the first etch stop layer to expose the capping layer; and
A second conductive member is formed in the opening,
Wherein the density of the second etch stop layer is greater than the density of the first etch stop layer.
2. The method of claim 1, wherein the adhesion layer comprises aluminum nitride or silicon nitride.
3. The method of claim 1, wherein the first and second etch stop layers comprise silicon carbonitride.
4. The method of claim 1, wherein a dielectric constant of the second etch stop layer is greater than a dielectric constant of the first etch stop layer.
5. The method of claim 1, further comprising:
depositing a third etch stop layer over the second etch stop layer prior to depositing the second dielectric layer,
Wherein the third etch stop layer comprises aluminum oxide.
6. The method of claim 1, further comprising:
after selectively depositing the capping layer, the first dielectric layer is replaced with a third dielectric layer.
7. The method of claim 6, wherein the third dielectric layer comprises an air gap.
8. A method of forming a semiconductor structure, comprising:
Receiving a workpiece comprising a first conductive feature embedded in a first dielectric layer;
Selectively depositing a capping layer over the first conductive feature;
depositing a first etch stop layer over the capping layer using a first plasma enhanced chemical vapor deposition process;
depositing an adhesion layer over the first etch stop layer;
Depositing a second etch stop layer over the adhesion layer using a second plasma enhanced chemical vapor deposition process;
depositing a second dielectric layer over the second etch stop layer;
forming an opening through the second dielectric layer, the second etch stop layer, the adhesion layer, and the first etch stop layer to expose the capping layer; and
A second conductive member is formed in the opening,
Wherein each of the first and second plasma enhanced chemical vapor deposition processes includes a high frequency pulse and a low frequency pulse,
Wherein, in the first plasma enhanced chemical vapor deposition process, a plasma of a nitrogen-containing precursor is introduced during the high frequency pulse,
Wherein, in the second plasma enhanced chemical vapor deposition process, a plasma of the nitrogen-containing precursor is introduced during the high frequency pulse and the low frequency pulse.
9. The method of claim 8, wherein the first and second etch stop layers comprise silicon carbonitride.
10. A semiconductor structure, comprising:
a first conductive member disposed in the first dielectric layer;
A cover layer disposed on the first conductive member;
a first etch stop layer disposed over and in contact with the capping layer and the top surface of the first dielectric layer;
an adhesive layer disposed on the first etch stop layer;
A second etch stop layer disposed on the adhesive layer;
a second dielectric layer over the second etch stop layer; and
A second conductive feature extending through the second dielectric layer, the second etch stop layer, the adhesion layer, and the second etch stop layer to contact the capping layer,
Wherein the density of the second etch stop layer is greater than the density of the first etch stop layer.
CN202410377948.2A 2023-03-29 2024-03-29 Semiconductor structure and forming method thereof Pending CN118380381A (en)

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