CN118379963B

CN118379963B - Gate driving circuit and display panel

Info

Publication number: CN118379963B
Application number: CN202410187050.9A
Authority: CN
Inventors: 肖丽娜; 曾迎祥
Original assignee: EverDisplay Optronics Shanghai Co Ltd
Current assignee: EverDisplay Optronics Shanghai Co Ltd
Priority date: 2024-02-20
Filing date: 2024-02-20
Publication date: 2024-10-18
Anticipated expiration: 2044-02-20
Also published as: CN118379963A

Abstract

The invention relates to the field of display panels, and provides a gate driving circuit and a display panel, wherein the gate driving circuit comprises a multi-stage shift register unit and a time sequence controller, each stage of shift register unit comprises 14 transistors and 3 capacitors, and the time sequence controller comprises two time sequence control signal lines. In addition, the grid driving circuit comprises at least one driving signal line controlled by the driving chip, and the shift register is controlled to output different electric signals in a low-frequency display area and a high-frequency display area, so that the display panel can update pictures in a partition mode, a high refresh rate is maintained in the high-frequency display area, the low refresh rate is adjusted in the low-frequency display area, the power consumption of the display panel is reduced, and the service life of the display panel is prolonged.

Description

Gate driving circuit and display panel

Technical Field

The present invention relates to the field of display panels, and in particular, to a gate driving circuit and a display panel.

Background

As a new generation of display technology, an OLED (Organic LIGHT EMITTING Diode) display has advantages of low power consumption, high color gamut, high brightness, high refresh rate, wide viewing angle, high response speed, and the like, and particularly, the advantage of the high refresh rate makes the OLED display more suitable for the display of a mobile device, so that the OLED display is increasingly widely used.

The refresh rate of the display means the number of times that the image on the screen is repeatedly scanned from top to bottom, and the higher the refresh rate is, the higher the stability of the displayed picture is, and the lower the degree of eye fatigue is. In recent years, as the usage time of mobile devices by people has gradually increased, the refresh rate of various mobile device displays has gradually increased for better use experience.

However, the mobile device has a high power consumption requirement, and the power consumption proportion of the display is particularly important, so that the refresh rate of the display directly affects the power consumption. Although low refresh rate has lower power consumption, the display quality is seriously affected by the dynamic picture display effect with low refresh rate.

At present, in the use process of the mobile device, not all the pictures in the display area change in real time, especially under the condition represented by short video application, a large number of static display areas with long-time pictures unchanged exist in the display area. However, all display areas of the display of the mobile device currently adopt the same refresh rate, i.e. adopt the high refresh rate of the dynamic display area, which causes waste of power consumption. At the same time, the display is always operating at the highest refresh rate, which accelerates its own aging.

It should be noted that the information disclosed in the above background section is only for enhancing understanding of the background of the invention and thus may include information that does not form the prior art that is already known to those of ordinary skill in the art.

Disclosure of Invention

In view of the above, the present invention provides a gate driving circuit and a display panel to solve at least the above-mentioned problems.

An aspect of the present invention provides a gate driving circuit applied to a display panel, including a multi-stage shift register unit including:

a first transistor, a first pole of which is connected to a first power supply, a second pole is connected to a first signal output terminal, and a gate is connected to a first node;

A second transistor, a first pole of which is connected to the first signal output terminal and a second pole of which is connected to a first timing control terminal;

A third transistor, a first electrode of which is connected to a second node, a second electrode of which is connected to a gate of the second transistor, and a gate of which is connected to a second power supply;

A fourth transistor, a first electrode of which is connected to a second timing control terminal, a second electrode of which is connected to the first node, and a gate of which is connected to the second node;

A fifth transistor, a first pole of which is connected to the first power supply, and a gate of which is connected to the first timing control terminal;

a sixth transistor having a first electrode connected to a second electrode of the fifth transistor, a second electrode connected to the second node, and a gate connected to the first node;

a seventh transistor, a first pole of which is connected to the first timing control terminal, and a gate of which is connected to the signal input terminal;

an eighth transistor, a first electrode of which is connected to the signal input terminal, and a gate electrode of which is connected to the second timing control terminal;

A ninth transistor, a first pole of which is connected to a second pole of the eighth transistor, a second pole of which is connected to the second node, and a gate of which is connected to the second timing control terminal;

a tenth transistor having a first electrode connected to the second power supply and a gate connected to the second timing control terminal;

An eleventh transistor having a first electrode connected to a second electrode of the tenth transistor, a second electrode connected to the first node, and a gate electrode connected to a second electrode of the seventh transistor;

a twelfth transistor, a first pole of which is connected to a second pole of the seventh transistor, a second pole of which is connected to the second power supply, and a gate of which is connected to the first timing control terminal;

a thirteenth transistor having a first electrode connected to the first power supply, a second electrode connected to the second signal output terminal, and a gate connected to the first driving signal line;

And a fourteenth transistor having a first electrode connected to the first signal output terminal, a second electrode connected to the second signal output terminal, and a gate connected to a second driving signal line.

In some embodiments of the present invention, in some embodiments,

The first transistor to the fourteenth transistor are P-type MOS transistors;

In a frame of picture time, inputting a low potential into the first driving signal line in a low-frequency display area of the display panel, wherein the potential of the second driving signal line is opposite to that of the first driving signal line at each moment;

In a high-frequency display region of the display panel, the first drive signal line inputs a high potential, and the second drive signal line has a potential opposite to that of the first drive signal line at each timing.

In some embodiments of the present invention, in some embodiments,

The first transistor to the thirteenth transistor are P-type MOS transistors, and the fourteenth transistor is an N-type MOS transistor;

the first driving signal line and the second driving signal line are the same driving signal line;

in a frame of picture time, inputting a low potential into the first driving signal line in a low-frequency display area of the display panel;

in a high-frequency display region of the display panel, the first driving signal line inputs a high potential.

In some embodiments, the shift register unit further includes:

A first capacitor, a first electrode of which is connected to the gate of the second transistor, and a second electrode of which is connected to the first electrode of the second transistor;

A second capacitor, a first pole of which is connected to the first power supply, and a second pole of which is connected to the first node;

And a third capacitor, wherein a first electrode of the third capacitor is connected to the first electrode of the eleventh transistor, and a second electrode of the third capacitor is connected to the gate of the eleventh transistor.

In some embodiments, the shift register unit further includes:

The timing controller comprises a first timing control signal line and a second timing control signal line;

the first timing control signal line is used for outputting a first timing control signal; the second timing control signal line is used for outputting a second timing control signal.

In some embodiments, the first timing control signal and the second timing control signal are square wave signals having the same output frequency and 180 ° phase difference.

In some embodiments, in a high-frequency display area of the display panel, the shift register unit is configured to delay a signal received from the signal input terminal under control of the first timing control signal line, the second timing control signal line, the first driving signal line, and the second driving signal line, and the processed signal is output from the second signal output terminal;

in the low-frequency display area of the display panel, the second signal output end continuously outputs high level.

In some embodiments, the first signal output terminal of the shift register unit at the previous stage outputs a first scan signal to the shift register unit at the next stage, and the second signal output terminal outputs a second scan signal to the corresponding pixel row;

and the second signal output end of the shift register unit at the last stage outputs a second scanning signal to the corresponding pixel row.

In some embodiments, in two adjacent stages of the shift register units, the first timing control terminal of one shift register unit is connected to the first timing control signal line, and the second timing control terminal is connected to the second timing control signal line; the first timing control end of the other shift register unit is connected to the second timing control signal line, and the second timing control end is connected to the first timing control signal line.

Another aspect of the present invention also provides a display panel, which includes the gate driving circuit described in any one of the above.

Compared with the prior art, the invention has the beneficial effects that at least:

According to the gate driving circuit and the display panel, the display panel is enabled to update pictures in a partition mode by providing the novel 14T3C shift register unit and at least one driving signal line controlled by the driving chip, a high refresh rate is maintained in a high-frequency display area, the low refresh rate is adjusted in a low-frequency display area, the power consumption of the display panel is reduced, and the service life of the display panel is prolonged.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention as claimed.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention. It is evident that the drawings in the following description are only some embodiments of the present invention and that other drawings may be obtained from these drawings without inventive effort for a person of ordinary skill in the art.

Fig. 1 shows a schematic structure of a display panel of the present invention;

fig. 2 shows a schematic cascade diagram of a gate driving circuit according to a first embodiment of the present invention;

Fig. 3 shows a circuit diagram of a shift register unit of a first embodiment of the present invention;

FIG. 4 shows waveforms of the shift register unit shown in FIG. 3 when operated;

FIG. 5 is a schematic diagram showing the on state of the shift register unit at stage t1 in FIG. 4;

FIG. 6 is a schematic diagram showing the on state of the shift register unit at stage t2 in FIG. 4;

FIG. 7 is a schematic diagram showing the on state of the shift register unit at stage t3 in FIG. 4;

Fig. 8 shows a circuit diagram of a shift register unit of a second embodiment of the present invention;

fig. 9 shows waveforms of the shift register unit shown in fig. 8 when operated.

Reference numerals:

10. Display panel

11. Low frequency display area

12. High frequency display area

13. Gate driving circuit

VDD first power supply

VEE second power supply

IN signal input terminal

CKV1 first timing control signal line

CKV2 second time sequence control signal line

TEN first driving signal line

TEP second drive signal line

Gout first signal output terminal

Gout' second signal output terminal

T1 first transistor

T2 second transistor

T3 third transistor

T4 fourth transistor

T5 fifth transistor

T6 sixth transistor

T7 seventh transistor

T8 eighth transistor

T9 ninth transistor

T10 tenth transistor

T11 eleventh transistor

T12 twelfth transistor

T13 thirteenth transistor

T14 fourteenth transistor

C1 First capacitor

C2 Second capacitor

C3 Third capacitor

N1 first node

N2 second node

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus a repetitive description thereof will be omitted.

The use of the terms "first," "second," and the like in the description herein do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. Furthermore, in the description of the present invention, the orientation or positional relationship indicated by the terms "upper", "lower", etc. are based on the orientation or positional relationship shown in the drawings, which are for convenience of description only, and are not indicative or implying that the apparatus or element in question must have a particular orientation, be constructed and operated in a particular orientation, and therefore should not be construed as limiting the present invention.

It should be noted that, without conflict, the embodiments of the present invention and features in different embodiments may be combined with each other.

The present inventors have made intensive studies to provide a solution to the problems existing in the prior art. The invention discloses a gate driving circuit and a display panel. The grid driving circuit comprises a plurality of stages of shift register units and a time sequence controller, wherein each stage of shift register unit comprises 14 transistors, 3 capacitors, a signal input end, two signal output ends and two time sequence control ends. The time schedule controller comprises two time schedule control signal lines. In addition, the grid driving circuit comprises at least one driving signal line controlled by the driving chip, and the shift register is controlled to output different electric signals in a low-frequency display area and a high-frequency display area, so that the display panel can update pictures in a partition mode, a high refresh rate is maintained in the high-frequency display area, the low refresh rate is adjusted in the low-frequency display area, the power consumption of the display panel is reduced, and the service life of the display panel is prolonged.

The following describes the embodiments of the present invention in further detail with reference to the drawings.

Fig. 1 shows a schematic structure of a display panel of the present invention.

As shown in fig. 1 to 2, one aspect of the present invention provides a display panel 10, the display panel 10 including a display region and a non-display region. Wherein the timing controller, the gate driving circuit 13, the data driver and the light emitting driving circuit are located in the non-display area of the display panel 10. The display area includes light emitting pixels and pixel circuits arranged in an array, and is divided into a low-frequency display area 11 and a high-frequency display area 12. The light emitting pixels emit light under the combined action of the timing controller, the gate driving circuit 13, the data driver, and the light emitting driving circuit.

Fig. 2 shows a cascade schematic diagram of a gate driving circuit according to a first embodiment of the present invention.

As shown in fig. 1 to 2, a first embodiment of the present invention provides a gate driving circuit 13, which includes a multi-stage shift register unit, a timing controller, and two first driving signal lines TEN and second driving signal lines TEP controlled by a driving chip.

IN the present embodiment, the shift register unit includes 14 transistors, 3 capacitors, a signal input terminal IN, a first signal output terminal Gout, and a second signal output terminal Gout'. The first signal output terminal Gout of the upper stage shift register unit outputs a first scanning signal to the signal input terminal IN of the lower stage shift register unit as a start signal, and the second signal output terminal Gout' outputs a second scanning signal to the corresponding pixel row to drive the pixels of the row to emit light. The second signal output terminal Gout' of the last stage shift register unit outputs a second scanning signal to the corresponding pixel row, and drives the pixels of the row to emit light. The last shift register unit does not output the first scan signal because there is no next stage. In addition, a stage of shift register units (dummy GOAs) is added to the gate driving circuit 13, and the stage does not enter the display area, so as to ensure that all the shift register units output normally and are not affected by the variation of the first driving signal line TEN and the second driving signal line TEP.

Specifically, in fig. 2, taking 4 cascaded shift register units as an example, the signal input terminal of the zeroth shift register unit (dummy GOA) inputs the start pulse signal STV as an input signal. The signal output end of the zeroth-stage shift register unit is connected with the signal input end IN1 of the first-stage shift register unit. The signal output end of the zeroth-stage shift register unit outputs a scanning signal as an input signal of the first-stage shift register unit. The first signal output terminal Gout1 of the first stage shift register unit is connected to the signal input terminal IN2 of the second stage shift register unit. The first signal output terminal Gout1 of the first stage shift register unit outputs the first scan signal as an input signal of the second stage shift register unit. The first signal output terminal Gout2 of the second stage shift register unit is connected to the signal input terminal IN3 of the third stage shift register unit. The first signal output terminal Gout2 of the second stage shift register unit outputs the first scan signal as the input signal … … of the third stage shift register unit, and the subsequent stage shift register units are repeated in this way, forming the gate driving circuit 13.

Fig. 3 shows a circuit diagram of a shift register unit of a first embodiment of the present invention; fig. 4 shows waveforms of the shift register unit shown in fig. 3 when operated.

In this embodiment, as shown in fig. 4, the timing controller includes a first timing control signal line CKV1 and a second timing control signal line CKV2. The first timing control signal line CKV1 is configured to output a first timing control signal; the second timing control signal line CKV2 is for outputting a second timing control signal. The first time sequence control signal and the second time sequence control signal are square wave signals with the same output frequency and 180 degrees phase difference.

In this embodiment, as shown in fig. 2, in two adjacent stages of the shift register units, the first timing control terminal of one shift register unit is connected to the first timing control signal line CKV1, and the second timing control terminal is connected to the second timing control signal line CKV2; the first timing control end of the other shift register unit is connected to the second timing control signal line CKV2, and the second timing control end is connected to the first timing control signal line CKV1.

IN the present embodiment, as shown IN fig. 1 and 4, IN the high frequency display region 12 of the display panel 10, the shift register unit is configured to delay the signal received from the signal input terminal IN under the control of the first timing control signal line CKV1, the second timing control signal line CKV2, the first driving signal line TEN, and the second driving signal line TEP, and the processed signal is output from the second signal output terminal Gout'. In the low frequency display region 11 of the display panel 10, the second signal output terminal Gout' continuously outputs a high level.

IN this embodiment, as shown IN fig. 3, the shift register unit includes 14 transistors, 3 capacitors, a signal input terminal IN, a first signal output terminal Gout, and a second signal output terminal Gout'. The first transistor T1 has a first pole connected to the first power supply VDD, a second pole connected to the first signal output terminal Gout, and a gate connected to the first node N1. The first pole of the second transistor T2 is connected to the first signal output terminal Gout, and the second pole is connected to the first timing control terminal. The third transistor T3 has a first electrode connected to the second node N2, a second electrode connected to the gate of the second transistor T2, and a gate connected to the second power source VEE. The fourth transistor T4 has a first pole connected to the second timing control terminal, a second pole connected to the first node N1, and a gate connected to the second node N2. The first pole of the fifth transistor T5 is connected to the first power supply VDD, and the gate is connected to the first timing control terminal. The first pole of the sixth transistor T6 is connected to the second pole of the fifth transistor T5, the second pole is connected to the second node N2, and the gate is connected to the first node N1. The first pole of the seventh transistor T7 is connected to the first timing control terminal, and the gate is connected to the signal input terminal IN. The eighth transistor T8 has a first electrode connected to the signal input terminal IN and a gate connected to the second timing control terminal. The first pole of the ninth transistor T9 is connected to the second pole of the eighth transistor T8, the second pole is connected to the second node N2, and the gate is connected to the second timing control terminal. The tenth transistor T10 has a first electrode connected to the second power VEE and a gate connected to the second timing control terminal. The eleventh transistor T11 has a first pole connected to the second pole of the tenth transistor T10, a second pole connected to the first node N1, and a gate connected to the second pole of the seventh transistor T7. The twelfth transistor T12 has a first pole connected to the second pole of the seventh transistor T7, a second pole connected to the second power VEE, and a gate connected to the first timing control terminal. The thirteenth transistor T13 has a first pole connected to the first power supply VDD, a second pole connected to the second signal output terminal Gout', and a gate connected to the first driving signal line TEN. The fourteenth transistor T14 has a first pole connected to the first signal output terminal Gout, a second pole connected to the second signal output terminal Gout', and a gate connected to the second driving signal line TEP. The first transistor T1 to the fourteenth transistor T14 are P-type MOS transistors. The first pole of the first capacitor C1 is connected to the gate of the second transistor T2, and the second pole is connected to the first pole of the second transistor T2. The first pole of the second capacitor C2 is connected to the first power supply VDD, and the second pole is connected to the first node N1. The first pole of the third capacitor C3 is connected to the first pole of the eleventh transistor T11, and the second pole is connected to the gate of the eleventh transistor T11. The first power supply VDD provides a positive voltage signal and the second power supply VEE provides a negative voltage signal.

In the present embodiment, as shown in fig. 4, in the low frequency display region 11 of the display panel 10, the first driving signal line TEN inputs a low potential, and the potential of the second driving signal line TEP is opposite to the first driving signal line TEN at each time; in the high-frequency display region 12 of the display panel 10, the first drive signal line TEN inputs a high potential, and the potential of the second drive signal line TEP is opposite to the first drive signal line TEN at every timing.

FIG. 5 is a schematic diagram showing the on state of the shift register unit at stage t1 in FIG. 4; FIG. 6 is a schematic diagram showing the on state of the shift register unit at stage t2 in FIG. 4; fig. 7 shows a schematic diagram of the on state of the shift register unit at stage t3 in fig. 4.

In the present embodiment, the waveform diagram shown in fig. 4 includes 3 processes: t1, t2 and t3. In these 3 processes, the display panel 10 completes one full-screen pixel line scanning process from top to bottom, that is, the time of one frame of picture. In the following, fig. 4 is taken as an example, wherein the low frequency display area 11 is represented by a first stage shift register unit, a second stage shift register unit, a sixth stage shift register unit and a seventh stage shift register unit, and the high frequency display area 12 is represented by a third stage shift register unit, a fourth stage shift register unit and a fifth stage shift register unit. For convenience of understanding, the high level signal "H" is shown in the drawing, and the low level signal is shown as "L". The relationship between the inputs and outputs of the shift register units in the above 3 processes is analyzed as follows in conjunction with fig. 6 to 5:

In the process t1, referring to fig. 4 and 5, the process corresponds to the first stage shift register unit and the second stage shift register unit, that is, refers to the low frequency display region 11 of the display panel 10. In this process, i.e., in the low frequency display region 11, the first driving signal line TEN inputs a low potential, the second driving signal line TEP inputs a high potential, and then the thirteenth transistor T13 is turned on, and the fourteenth transistor T14 is turned off, resulting in the second signal output terminal Gout1 'of the first stage shift register unit and the second signal output terminal Gout2' of the second stage shift register unit outputting a high potential. At this time, the screen of the low-frequency display area 11 of the display panel is not updated, and the previous frame of screen is maintained.

In the process t2, referring to fig. 4 and 6, the process corresponds to the third stage shift register unit, the fourth stage shift register unit, and the fifth stage shift register unit, that is, refers to the high frequency display area 12 of the display panel 10. In this process, i.e., in the high frequency display region 12, the first driving signal line TEN inputs a high potential, the second driving signal line TEP inputs a low potential, and then the thirteenth transistor T13 is turned off, and the fourteenth transistor T14 is turned on, resulting in the second signal output terminal Gout3' of the third stage shift register unit, the second signal output terminal Gout4' of the fourth stage shift register unit, and the second signal output terminal Gout5' of the fifth stage shift register unit sequentially outputting a low potential during T2. At this time, the screen of the high-frequency display area 12 of the display panel is updated.

In the process t3, referring to fig. 4 and 7, the process corresponds to the sixth stage shift register unit and the seventh stage shift register unit, that is, refers to the low frequency display region 11 of the display panel 10. In this process, i.e., in the low frequency display region 11, the first driving signal line TEN inputs a low potential, the second driving signal line TEP inputs a high potential, and then the thirteenth transistor T13 is turned on, and the fourteenth transistor T14 is turned off, resulting in the second signal output terminal Gout1 'of the first stage shift register unit and the second signal output terminal Gout2' of the second stage shift register unit outputting a high potential. At this time, the screen of the low-frequency display area 11 of the display panel is not updated, and the previous frame of screen is maintained.

When the gate driving circuit 13 starts displaying the next frame after t3, the start pulse signal STV or the signal input terminal IN inputs a low voltage to enter the next round of t1 again.

It is to be noted that the above correspondence relationship of the shift register unit and the low-frequency display area 11 and the high-frequency display area 12 is merely exemplary, and the reality may be different therefrom. The display area may have a plurality of low frequency display areas 11 and high frequency display areas 12 at the same time, and the positions of the two display areas may be adjusted as required, and only the input waveforms of the first driving signal line TEN and the second driving signal line TEP in the shift register unit corresponding to the pixel row need to be adjusted.

Fig. 8 shows a circuit diagram of a shift register unit of a second embodiment of the present invention; fig. 9 shows waveforms of the shift register unit shown in fig. 8 when operated.

In the present embodiment, the difference from the first embodiment is that the first transistor T1 to the thirteenth transistor T13 are P-type MOS transistors, and the fourteenth transistor T14 is an N-type MOS transistor. The first driving signal line TEN and the second driving signal line TEP are the same driving signal line. In the low frequency display region 11 of the display panel 10, the first driving signal line TEN inputs a low potential during one frame of picture time; in the high-frequency display region 12 of the display panel 10, a high potential is input to the first driving signal line TEN.

In this embodiment, referring to fig. 8 and 9, the working process of the circuit of this embodiment may also be divided into a portion corresponding to the low frequency display area 11 and a portion corresponding to the high frequency display area 12, and the same technical effects are achieved, and the specific working process of the circuit may refer to the first embodiment, which is not repeated here. In addition, compared with the first embodiment, the present embodiment can accomplish the same function by only one first driving signal line TEN, thereby simplifying the complexity of the gate driving circuit 13.

According to the grid driving circuit, the novel 14T3C shift register unit and at least one driving signal line controlled by the driving chip are provided, so that the display panel is enabled to update pictures in a partitioned mode, a high refresh rate is maintained in a high-frequency display area, the low refresh rate is adjusted in a low-frequency display area, the power consumption of the display panel is reduced, and the service life of the display panel is prolonged.

Based on the same inventive concept, the embodiment of the present invention also provides a display device, including the display panel 10 provided by the embodiment of the present invention. The display device may be: any product or component with display function such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like. The implementation of the display device can be referred to the embodiment of the display panel 10, and the repetition is not repeated.

The foregoing is a further detailed description of the invention in connection with the preferred embodiments, and it is not intended that the invention be limited to the specific embodiments described. It will be apparent to those skilled in the art that several simple deductions or substitutions may be made without departing from the spirit of the invention, and these should be considered to be within the scope of the invention.

Claims

1. A gate driving circuit for a display panel, comprising a plurality of stages of shift register units, the shift register units comprising:

A fourteenth transistor having a first electrode connected to the first signal output terminal, a second electrode connected to the second signal output terminal, and a gate connected to a second driving signal line;

The shift register unit outputs different electric signals in a low-frequency display area and a high-frequency display area of the display panel, so that the display panel maintains a low refresh rate in the low-frequency display area and maintains a high refresh rate in the high-frequency display area.

2. The gate driving circuit according to claim 1, wherein,

The first transistor to the fourteenth transistor are P-type MOS transistors;

3. The gate driving circuit according to claim 1, wherein,

4. The gate drive circuit according to claim 1, wherein the shift register unit further comprises:

5. The gate drive circuit of claim 1, further comprising:

6. The gate driving circuit of claim 5, wherein the gate driving circuit comprises a gate driver circuit,

The first time sequence control signal and the second time sequence control signal are square wave signals with the same output frequency and 180 degrees phase difference.

7. The gate driving circuit according to claim 6, wherein,

In the high-frequency display area of the display panel, the shift register unit is used for carrying out time delay processing on signals received from the signal input end under the control of the first time sequence control signal line, the second time sequence control signal line, the first driving signal line and the second driving signal line, and the processed signals are output by the second signal output end;

8. The gate driving circuit of claim 5, wherein the gate driving circuit comprises a gate driver circuit,

The first signal output end of the shift register unit at the previous stage outputs a first scanning signal to the shift register unit at the next stage, and the second signal output end outputs a second scanning signal to the corresponding pixel row;

9. The gate driving circuit according to claim 8, wherein,

In two adjacent stages of shift register units, the first timing control end of one shift register unit is connected to the first timing control signal line, and the second timing control end is connected to the second timing control signal line; the first timing control end of the other shift register unit is connected to the second timing control signal line, and the second timing control end is connected to the first timing control signal line.

10. A display panel comprising the gate driving circuit according to any one of claims 1 to 9.