CN118368881A - Semiconductor structure, manufacturing method thereof and memory - Google Patents
Semiconductor structure, manufacturing method thereof and memory Download PDFInfo
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- CN118368881A CN118368881A CN202310041910.3A CN202310041910A CN118368881A CN 118368881 A CN118368881 A CN 118368881A CN 202310041910 A CN202310041910 A CN 202310041910A CN 118368881 A CN118368881 A CN 118368881A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 50
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 21
- 239000010410 layer Substances 0.000 claims abstract description 406
- 239000011241 protective layer Substances 0.000 claims abstract description 35
- 230000000149 penetrating effect Effects 0.000 claims abstract description 21
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- 238000000034 method Methods 0.000 claims description 62
- 239000000463 material Substances 0.000 claims description 51
- 238000005530 etching Methods 0.000 claims description 29
- 239000000758 substrate Substances 0.000 claims description 13
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- 239000003990 capacitor Substances 0.000 description 24
- 238000003860 storage Methods 0.000 description 23
- 238000005240 physical vapour deposition Methods 0.000 description 7
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 4
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- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 229910001925 ruthenium oxide Inorganic materials 0.000 description 3
- WOCIAKWEIIZHES-UHFFFAOYSA-N ruthenium(iv) oxide Chemical compound O=[Ru]=O WOCIAKWEIIZHES-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
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- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
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- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
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Abstract
The embodiment of the disclosure provides a semiconductor structure, a manufacturing method thereof and a memory, wherein the manufacturing method of the semiconductor structure comprises the following steps: providing a stacked structure; the stacking structure comprises a first supporting layer, a first medium layer, a second supporting layer, a second medium layer and a third supporting layer which are sequentially stacked from bottom to top; forming a plurality of first holes penetrating through the stacked structure, and forming a first conductive layer in the first holes; forming a second hole penetrating the third support layer at a preset position offset from the first conductive layer in a direction perpendicular to the lamination; removing the second dielectric layer through the second hole to form a gap; forming a protective layer at least on the side wall of the second hole and the side wall of the gap; forming a third hole penetrating the second support layer at the preset position; and removing at least the first dielectric layer through the third hole.
Description
Technical Field
The present disclosure relates to the field of semiconductor technology, and relates to, but is not limited to, a semiconductor structure, a method of manufacturing the same, and a memory.
Background
One common memory array architecture for dynamic random access memory (DRAM, dynamic Random Access Memory) is an array comprising a transistor and a capacitor as a memory cell (i.e., a 1T1C memory cell). The gate of the transistor is connected with the word line, one end of the source/drain is connected with the bit line, and the other end is connected with the capacitor.
As the size of the dynamic random access memory is reduced, the size of the capacitor is also reduced. On the premise of ensuring that the performances of the capacitor are not affected, higher requirements are put on the preparation process and the like.
Disclosure of Invention
In view of this, in order to solve the related technical problems, embodiments of the present disclosure provide a semiconductor structure, a manufacturing method thereof, and a memory.
In one aspect, an embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, the method including:
providing a stacked structure; the stacking structure comprises a first supporting layer, a first medium layer, a second supporting layer, a second medium layer and a third supporting layer which are sequentially stacked from bottom to top;
forming a plurality of first holes penetrating through the stacked structure, and forming a first conductive layer in the first holes;
Forming a second hole penetrating the third support layer at a preset position offset from the first conductive layer in a direction perpendicular to the lamination;
removing the second dielectric layer through the second hole to form a gap;
forming a protective layer at least on the side wall of the second hole and the side wall of the gap;
Forming a third hole penetrating the second support layer at the preset position;
and removing at least the first dielectric layer through the third hole.
In the above scheme, the material of the protective layer is the same as the material of the first dielectric layer;
the removing at least the first dielectric layer through the third hole includes:
And removing the first dielectric layer and the protective layer through the third hole.
In the above scheme, the materials of the first dielectric layer and the protective layer both comprise oxides of semiconductor materials.
In the above aspect, the forming a protective layer includes:
and forming the protective layer through an atomic layer deposition process.
In the above aspect, the stacked structure further includes: a sacrificial layer on the third support layer;
The forming a first hole through the stacked structure includes:
forming a first mask layer on the sacrificial layer;
performing first etching on the stacked structure by using the first mask layer to form the first hole; in the process of carrying out the first etching, the first mask layer and part of the sacrificial layer are removed at the same time;
the method further comprises the steps of:
And removing the remaining sacrificial layer.
In the above scheme, the etching selection ratio of each dielectric layer in the stacked structure and the sacrificial layer is different; the etching selection ratio of each supporting layer and the sacrificial layer in the stacked structure is different.
In the above scheme, the material of each dielectric layer in the stacked structure includes an oxide of a semiconductor material, the material of each supporting layer in the stacked structure includes a nitride of the semiconductor material, and the sacrificial layer includes the semiconductor material.
In the above aspect, the forming a first conductive layer in the first hole includes:
forming a first initial conductive layer in the first hole on the top surface of the third support layer;
the method further comprises the steps of:
and removing the first initial conductive layer positioned on the top surface of the third supporting layer before forming the second hole, and taking the rest of the first initial conductive layer as the first conductive layer.
In the above scheme, the plurality of first conductive layers form a plurality of rows, and three adjacent first conductive layers in two adjacent rows of first conductive layers are arranged in a triangle;
The forming a second hole through the third support layer, comprising:
forming a second mask layer on the third support layer; the pattern corresponding to the second mask layer is positioned in the middle of the triangle and is contacted with all the three first conductive layers adjacent to each other;
And performing second etching on the third supporting layer by using the second mask layer to form the second hole.
In the above aspect, the forming a protective layer at least on the side wall of the second hole and the side wall of the gap includes:
Forming the protective layer on the side wall of the second hole, the side wall of the gap, the top of the third supporting layer and the bottom of the gap;
forming a third hole through the second support layer at the preset position, including:
and performing third etching on the protective layer at the bottom of the gap and the second support layer by using the protective layer at the top of the third support layer as a mask layer to form the third hole.
In the above scheme, the method further comprises:
Forming a dielectric layer covering the first conductive layer after removing the first dielectric layer;
a second conductive layer is formed overlying the dielectric layer.
In another aspect, an embodiment of the present disclosure further provides a semiconductor structure, where the semiconductor structure is prepared by the method described in the foregoing embodiment of the present disclosure, and the semiconductor structure includes:
A substrate;
a plurality of support layers positioned on the substrate and stacked along a first direction;
The first conductive layers are arranged in an array along the second direction and the third direction; the first conductive layer extends along the first direction and penetrates through a plurality of the supporting layers; the first direction is perpendicular to the second direction and the third direction, and the second direction intersects the third direction;
a plurality of dielectric layers; the dielectric layer covers the surface of the first conductive layer;
and a second conductive layer covering surfaces of the dielectric layers.
In the above scheme, the plurality of first conductive layers form a plurality of rows, and three first conductive layers adjacent to each other in two adjacent rows of first conductive layers are arranged in a triangle.
In yet another aspect, an embodiment of the present disclosure provides a memory, including: the semiconductor structure as in the above embodiments of the present disclosure, and a transistor array within the substrate, the first conductive layer being electrically connected to the transistor array.
In various embodiments of the present disclosure, a first supporting layer, a first dielectric layer, a second supporting layer, a second dielectric layer, and a third supporting layer that are stacked and disposed are sequentially formed from bottom to top, then a first hole penetrating the first supporting layer, the first dielectric layer, the second supporting layer, the second dielectric layer, and the third supporting layer is formed, a first conductive layer is formed in the first hole, then a second hole penetrating the third supporting layer is formed at a preset position that is offset from the first conductive layer, and the second dielectric layer is removed through the second hole, a gap is formed, then a protective layer is formed at both side walls of the second hole and the gap, then a third hole penetrating the second supporting layer is formed at the preset position, and the first dielectric layer is removed through the third hole, so that the second hole, the gap, the third hole, and a gap left after the first dielectric layer is removed form a storage structure hole together; the memory structure holes are used to form complete memory cells. In the process of forming the storage structure hole, a protective layer is formed on the side wall of the second hole and the side wall of the gap, so that the top structure of the third support layer is not damaged in the operations of forming the third hole, removing the second medium layer, removing the first medium layer and the like, and the shape-preserving capability of the third support layer is further improved; meanwhile, the exposed side wall of the first conductive layer is not damaged, so that the quality of the first conductive layer is improved, uniformity of the storage structure holes can be improved, and thus, the shape-preserving capability of forming a complete storage unit in the storage structure holes is also improved, and further, the electrical performance of the storage unit and the reliability of a memory are improved.
Drawings
FIG. 1 is a schematic diagram of a control circuit of a 1T1C architecture provided in an embodiment of the disclosure;
FIG. 2 is a schematic diagram of a cross-sectional structure of a hole of a memory structure with different widths of upper and lower diameters according to an embodiment of the present disclosure;
fig. 3 is a schematic flow chart of a method for manufacturing a semiconductor structure according to an embodiment of the disclosure;
fig. 4 a-4 r are schematic cross-sectional views illustrating a process for fabricating a semiconductor structure according to an embodiment of the present disclosure.
In the drawings (which are not necessarily drawn to scale), like numerals may describe similar components in different views. Like reference numerals having different letter suffixes may represent different instances of similar components. The drawings illustrate generally, by way of example and not by way of limitation, various embodiments discussed herein.
Detailed Description
In order to make the technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the present disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
In the presently disclosed embodiments, the term "layer" refers to a portion of material that includes a region having a thickness. The layer may extend over the entirety of the underlying or overlying structure, or may have a range that is less than the range of the underlying or overlying structure. Further, the layer may be a region of homogeneous or heterogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, the layer may be located between the top and bottom surfaces of the continuous structure, or the layer may be between any horizontal facing at the top and bottom surfaces of the continuous structure. The layers may extend horizontally, vertically and/or along an inclined surface. The layer may comprise a plurality of sub-layers. For example, the interconnect layer may include one or more conductors and contact sublayers (in which interconnect lines and/or via contacts are formed), and one or more dielectric sublayers.
In the presently disclosed embodiments, the terms "first," "second," and the like are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order.
It should be noted that, for clarity of description of the present disclosure, in the following embodiments, the first direction is perpendicular to the second direction and the third direction, and the second direction intersects with the third direction, that is, an included angle between the second direction and the third direction is any angle between 0-90 degrees, and for convenience of understanding, the second direction is illustrated as being perpendicular to the third direction. It can be understood that the included angle between the second direction and the third direction constructs the positional relationship of the plurality of storage structure holes in array arrangement along the second direction and the third direction. Illustratively, the first direction is the Z-axis direction shown in the drawings; the second direction is the X-axis direction shown in the drawing; the third direction is the Y-axis direction shown in the drawings. It should be noted, however, that the description of the directions in the following examples is only for illustrating the present disclosure and is not intended to limit the scope of the present disclosure.
Embodiments of the present disclosure relate to semiconductor structures that will be used in subsequent processes to form at least a portion of a final device structure. Here, the final device may include a memory including, but not limited to, a dynamic random access memory, which is described below as an example only, and is not intended to limit the scope of the present disclosure.
With the development of dynamic random access memory technology, the size of the memory cells is smaller and smaller, and the array architecture is from 8F 2 to 6F 2 to 4F 2; in addition, based on the ion and leakage current requirements in DRAM, the memory architecture is from planar array transistors (PLANAR ARRAY Transport) to recessed gate array transistors (RECESS GATE ARRAY Transport), from recessed gate array transistors to buried channel array transistors (Buried CHANNEL ARRAY Transport), and from buried channel array transistors to vertical channel array transistors (VERTICAL CHANNEL ARRAY Transport).
In some embodiments of the present disclosure, a dynamic random access memory is composed of a plurality of memory structures, each memory structure is mainly composed of one Transistor and one memory cell (e.g., capacitor) operated by the Transistor, i.e., the dynamic random access memory includes an architecture of 1 Transistor (T) and 1 capacitor (C, capacitor) (1T 1C).
Fig. 1 is a schematic diagram of a control circuit employing a 1T1C architecture according to an embodiment of the present disclosure, where, as shown in fig. 1, a drain electrode of a transistor T is electrically connected to a bit Line (BL, bit Line), a source electrode of the transistor T is electrically connected to one of electrode plates of a capacitor C, and another electrode plate of the capacitor C may be connected to a reference voltage, where the reference voltage may be a ground voltage or another voltage, and a gate electrode of the transistor T is connected to a Word Line (WL, word Line); the transistor T is controlled to be turned on or off by the application of a voltage to the word line WL, and the bit line BL is used to perform a read or write operation on the capacitor C when the transistor T is turned on.
However, with the development of high integration of devices, the following problems may exist in the existing capacitor manufacturing method: as shown in fig. 2, the storage structure hole for forming the capacitor has the problems of top damage 201, bending 202, sidewall inclination 203, top supporting layer loss 204, and the like, wherein the bending 202 and the sidewall inclination 203 enable the upper and lower diameter widths of the storage structure hole to be different or the critical dimensions (CD, critical Dimension) of the storage structure hole to be changed, and the morphology of the capacitor formed in the storage structure hole is greatly different, so that the performance of the capacitor is affected, and the reliability of the memory is reduced; the top damage 201 and the top supporting layer loss 204 easily cause the reduction of the effective area of the top supporting layer, the supporting force is reduced, and the storage structure hole is bent or collapsed, so that the capacitor is short-circuited, and the storage performance and the structural stability of the capacitor are affected; in addition, the top support layer loss 204 results in a reduced capacitance height, which is also reduced; further, the electrode layer of the capacitor may be consumed, which may also affect the structural stability of the capacitor.
In view of this, in order to solve one or more of the above problems, embodiments of the present disclosure provide a method for manufacturing a semiconductor structure, which can improve the conformal capability of a memory cell (such as a capacitor), and further improve the electrical performance of the memory cell (such as a capacitor) and the reliability of the memory. Fig. 3 is a flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of the disclosure. As shown in fig. 3, a method for manufacturing a semiconductor structure according to an embodiment of the disclosure includes the following steps:
Step S301: providing a stacked structure; the stacking structure comprises a first supporting layer, a first medium layer, a second supporting layer, a second medium layer and a third supporting layer which are sequentially stacked from bottom to top;
Step S302: forming a plurality of first holes penetrating through the stacked structure, and forming a first conductive layer in the first holes;
Step S303: forming a second hole penetrating the third support layer at a preset position offset from the first conductive layer in a direction perpendicular to the lamination;
Step S304: removing the second dielectric layer through the second hole to form a gap;
step S305: forming a protective layer at least on the side wall of the second hole and the side wall of the gap;
step S306: forming a third hole penetrating the second support layer at the preset position;
step S307: and removing at least the first dielectric layer through the third hole.
It should be understood that the steps shown in fig. 3 are not exclusive and that other steps may be performed before, after, or between any of the steps in the illustrated operations. The steps shown in fig. 3 can be sequentially adjusted according to actual requirements. Fig. 4a to 4r are schematic cross-sectional views illustrating a manufacturing process of a semiconductor structure according to an embodiment of the disclosure. The following describes in detail the method for manufacturing the semiconductor structure according to the embodiment of the present disclosure with reference to fig. 3 and fig. 4a to 4 r.
In step S301, referring to fig. 4a, a stacked structure 40 is provided.
The providing of the stacked structure 40 includes: a substrate 400 is provided, a first support layer 401 is formed on the substrate 400, a first dielectric layer 402 is formed on the first support layer 401, a second support layer 403 is formed on the first dielectric layer 402, a second dielectric layer 404 is formed on the second support layer 403, and a third support layer 405 is formed on the second dielectric layer 404. In some embodiments, the stacked structure 40 further comprises a sacrificial layer 406 on the third support layer 405, based on which the method further comprises: a sacrificial layer 406 is formed on the third support layer 405.
Here, the constituent material of the substrate 400 may include silicon (Si), germanium (Ge), silicon germanium (SiGe), and the like. In other embodiments, the constituent materials of the substrate 400 may also include silicon-on-insulator (Silicon on Insulator, SOI) or germanium-on-insulator (Germanium on Insulator, GOI). In the embodiment of the disclosure, when materials are selected for each dielectric layer, each supporting layer and the sacrificial layer in the stacked structure 40, the etching selection ratio of each dielectric layer to the sacrificial layer is different; the etching selectivity ratio of each supporting layer to the sacrificial layer is different.
Illustratively, the etching selectivity of the first support layer 401, the second support layer 403, and the third support layer 405 are the same, the etching selectivity of the first dielectric layer 402 and the etching selectivity of the second dielectric layer 404 are the same, and the etching selectivity of the first support layer 401, the second support layer 403, and the etching selectivity of the third support layer 405 are different from the etching selectivity of the sacrificial layer 406; the etch selectivity of the first dielectric layer 402 and the second dielectric layer 404 is different from the etch selectivity of the sacrificial layer 406.
In some embodiments, the etch selectivity of the first support layer 401, the second support layer 403, and the third support layer 405 is less than the etch selectivity of the sacrificial layer 406, and the etch selectivity of the first dielectric layer 402 and the second dielectric layer 404 is less than the etch selectivity of the sacrificial layer 406; in other words, under the same etching conditions, the etching rate of the sacrificial layer is slower and less prone to be etched than that of each of the support layers and each of the dielectric layers, so that the third support layer 405 can be protected from being etched or excessively consumed when the first hole is formed, so as to facilitate the shape retention of the third support layer 405.
In some embodiments, the material of each dielectric layer in the stack structure comprises an oxide of a semiconductor material, the material of each support layer in the stack structure comprises a nitride of a semiconductor material, and the sacrificial layer comprises a semiconductor material.
In other words, the first support layer 401, the second support layer 403, and the third support layer 405 have the same composition, and each include, but are not limited to, nitrides of semiconductor materials, such as silicon nitride (SiN); the first dielectric layer 402 and the second dielectric layer 404 have the same composition, and each include, but are not limited to, oxides of semiconductor materials, such as silicon oxide (SiO), etc.; the constituent materials of the sacrificial layer 406 include, but are not limited to, semiconductor materials such as polysilicon (Poly).
In the embodiment of the disclosure, the first support layer 401, the first dielectric layer 402, the second support layer 403, the second dielectric layer 404, the third support layer 405, and the sacrificial layer 406 may be formed by physical vapor deposition (PVD, physical Vapor Deposition), chemical vapor deposition (CVD, chemical Vapor Deposition), atomic layer deposition (ALD, atomic Layer Deposition), and the like.
In step S302, referring to fig. 4a, 4b, a first hole and a first conductive layer are formed.
Before forming the first hole, the method further comprises forming a first mask layer on the sacrificial layer.
Specifically, referring to fig. 4a, before forming the first hole, a first mask material layer 407a and a second mask material layer 407b, which are stacked, and a photoresist layer (not shown in fig. 4 a) disposed over the second mask material layer 407b are sequentially formed on the sacrificial layer 406; wherein the first mask material layer 407a includes: an Oxide layer, an anti-reflection layer (e.g., an amorphous carbon layer (ACL, amorphous Carbon Layer)), the second mask material layer 407b includes: a hard mask spin-on layer (SOH, spin On Hardmasks), a silicon oxynitride layer (SiON); methods of forming the first mask material layer 407a and the second mask material layer 407b include, but are not limited to, PVD, CVD, and the like processes. Then, the first mask material layer 407 having the first hole preset pattern is finally formed by exposing, developing, and pattern transferring the first mask material layer 407a and the second mask material layer 407b, referring to fig. 4b.
It should be noted that, referring to fig. 4b, the stacked structure 40 may include a first sub-stacked structure 40a and a second sub-stacked structure 40b, and in some embodiments, the first sub-stacked structure 40a may be used to form a memory cell array, and the second sub-stacked structure 40b may be used to form a peripheral circuit, where the memory cell array includes a plurality of memory cells, that is, the memory cells in the embodiments of the present disclosure are all disposed in the first sub-stacked structure 40 a.
Next, referring to fig. 4b and fig. 4c, the first mask layer 407 is used to perform a first etching on the stacked structure 40 to form a plurality of first holes 408, where each first hole 408 penetrates through the stacked structure 40 and extends along a first direction, and it should be noted that the plurality of first holes 408 are arranged in an array along a second direction and a third direction. The first etch includes, but is not limited to, a dry etch process. It should be noted that, referring to fig. 4c, during the first etching process, the first mask layer 407 and a portion of the sacrificial layer 406 are removed at the same time. It should be noted that, in the embodiments of the present disclosure, the first direction is the Z-axis direction in the drawing, the second direction is the X-axis direction in the drawing, and the third direction is the Y-axis direction in the drawing.
It should be appreciated that since the etch selectivity of the sacrificial layer 406 is smaller than the etch selectivity of the dielectric layers and the support layers, the etch rate of the sacrificial layer 406 is relatively slow during the performance of the first etch, wherein only a portion of the sacrificial layer is consumed, in other words, the sacrificial layer 406 may also serve to protect the top of the third support layer 405 from being etched during the performance of the first etch.
Next, referring to fig. 4d, the method further comprises: the remaining sacrificial layer 406 is removed. The removal process includes, but is not limited to, a dry etching process.
Next, referring to fig. 4e, 4f, and 4g, fig. 4g is a top view corresponding to fig. 4f, and a first initial conductive layer 409a is formed in the first hole 408, and in some embodiments, the first initial conductive layer 409a is further formed on a top surface of the third support layer 405, referring to fig. 4e, based on which the method further includes: the first initial conductive layer 409a on the top surface of the third support layer 405 is removed by a dry etching process, and the remaining first initial conductive layer serves as the first conductive layer 409b, referring to fig. 4f. Materials of the first conductive layer include, but are not limited to, ruthenium (Ru), ruthenium oxide (RuO), titanium nitride (TiN), titanium (Ti), tungsten (W); methods of forming the first conductive layer include, but are not limited to, PVD, CVD, ALD processes. It should be noted that, referring to fig. 4g, the plurality of first conductive layers 409b form a plurality of rows, and three first conductive layers 409b adjacent to each other in two adjacent rows of first conductive layers are arranged in a triangle; or the first conductive layers 409b may be arranged in a hexagonal density.
In step S303, a second hole is formed through the third support layer.
In some embodiments, the forming a second hole through the third support layer includes:
Referring to fig. 4h, a second mask layer 410 is formed on the third support layer 405; the material of the second mask layer 410 includes, but is not limited to, photoresist, such as photoresist, or a hard mask material patterned based on a photolithographic mask, and the method of forming the second mask layer 410 includes, but is not limited to, a coating process. In actual operation, the method further comprises: a preset pattern of second holes is formed on the second mask layer 410 by performing operations such as exposing, developing, pattern transferring, etc. on the second mask layer 410, wherein a position of each corresponding second hole on the second mask layer 410 is located in the middle of three first conductive layers 409b adjacent to each other.
Referring next to fig. 4i and 4j, fig. 4j is a top view corresponding to fig. 4i, and the method further includes: the second etching is performed on the third supporting layer 405 by using the second mask layer 410 to form a plurality of second holes 411 penetrating through the third supporting layer 405, where the plurality of second holes 411 are arranged in an array along the X-axis direction and the Y-axis direction, and each second hole 411 extends along the Z-axis direction, and it should be noted that, in the embodiment of the present disclosure, each second hole 411 is located at a preset position offset from the first conductive layer 409b, where the preset position may be understood as that each second hole 411 is offset from the first conductive layer 409b in both the X-axis direction and the Y-axis direction, and in particular, reference may be made to fig. 4j, where each second hole 411 is located in the middle of three first conductive layers 409b adjacent to each other and is in contact with three first conductive layers 409b adjacent to each other. It should be noted that the second etching includes, but is not limited to, dry etching and other processes; in some embodiments, after forming the second hole 411, the method further comprises: the second mask layer 410 is removed by dissolution or ashing.
In step S304, referring to fig. 4k, the second dielectric layer 404 is removed through the second hole 411 to form a gap 412, where the removal process includes, but is not limited to, wet etching, and the etchant includes, but is not limited to, phosphoric acid (H 3PO4).
In step S305, a protective layer is formed at least on the side walls of the second hole and the side walls of the gap.
Referring to fig. 4l and 4m, fig. 4m is a top view corresponding to fig. 4l, and the protective layer 413 is formed on the sidewall of the second hole 411, the sidewall of the gap 412, the top of the third supporting layer 405, and the bottom of the gap 412; here, the material of the protective layer 413 is the same as that of the first dielectric layer 402, and illustratively, the material of the protective layer 413 includes an oxide of a semiconductor material, for example, silicon oxide; methods of forming the protective layer 413 include, but are not limited to, PVD, CVD, ALD processes.
In step S306, a third hole penetrating the second support layer is formed at the preset position.
Referring to fig. 4n and 4o, fig. 4o is a plan view corresponding to fig. 4n, and a third hole 411 is formed by performing a third etching on a portion of the protective layer at the bottom of the gap 412 and a portion of the second support layer 403 by using the protective layer 413 at the top of the third support layer 405 as a mask layer, so as to form a third hole 414 penetrating the second support layer; the third etch includes, but is not limited to, a dry etch process. In the process of executing the third etching, the protection layer 413 located at the top of the third supporting layer 405 is consumed, so that the top of the third supporting layer 405 can be prevented from being consumed or etched in the etching process by arranging the protection layer 413 at the top of the third supporting layer 405, which is favorable for the shape retention of the third supporting layer 405, so that the third supporting layer 405 plays a supporting role, structural collapse is prevented, structural stability is improved, and further, the risk of capacitive short circuit is reduced.
In step S307, referring to fig. 4p and fig. 4q, fig. 4q is a top view corresponding to fig. 4p, and the first dielectric layer 402 and the remaining protective layer 413 are removed through the third hole to form a fourth hole 415, and in other embodiments, the method further includes: after removing the first dielectric layer, a portion of the second support layer 403 located between adjacent two first conductive layers is removed using the first holes, forming enlarged third holes 414 (refer to fig. 4 p). Here, the orthographic projections of the corresponding holes or gaps in each supporting layer along the Z-axis direction overlap, in other words, the fourth holes 415, the third holes 414, the gaps 412 and the second holes 411 are communicated along the Z-axis direction and form storage structure holes, and in the subsequent process, a part of the dielectric layer and a part of the second conductive layer may be formed in the storage structure holes. The process of removing the first dielectric layer 402 and the protective layer 413 includes, but is not limited to, wet etching, the etchant includes, but is not limited to, phosphoric acid, and the method of removing the portion of the second support layer 403 includes, but is not limited to, dry etching.
Specifically, referring to fig. 4r, the method further comprises: after removing the first dielectric layer, a dielectric layer 416 is formed overlying the first conductive layer, and a second conductive layer 417 is formed overlying the dielectric layer. Here, the dielectric layer 416 covers not only the surface of the first conductive layer on the side of the storage structure hole but also the bottom surface of the third support layer and the top and bottom surfaces of the second support layer; also, the second conductive layer 417 is located not only in the storage structure hole but also in the dielectric layer between the bottom surface of the third support layer and the top surface of the second support layer. In practice, the first conductive layer 409b, the dielectric layer 416 and the second conductive layer 417 together form a complete memory cell (such as a capacitor), where the first conductive layer 409b is used as a lower electrode of the capacitor; dielectric layer 416 is used as the dielectric of the capacitor; the second conductive layer 417 is used as an upper electrode of the capacitor.
In some embodiments, the constituent materials of the dielectric layer include High dielectric constant (High-K) materials, which generally refer to materials having a dielectric constant above 3.9, and typically significantly above that value. In some specific examples, the material of the dielectric layer may include, but is not limited to, aluminum oxide (Al 2O3), zirconium oxide (ZrO), hafnium oxide (HfO 2), strontium titanate (SrTiO 3), and the like. The composition material of the second conductive layer is the same as that of the first conductive layer, and may include, but is not limited to, ruthenium oxide, titanium nitride, titanium, and tungsten. Methods of forming the dielectric layer and the second conductive layer include, but are not limited to, PVD, CVD, ALD and the like.
Based on this, in each embodiment of the disclosure, a first supporting layer, a first dielectric layer, a second supporting layer, a second dielectric layer and a third supporting layer are sequentially formed from bottom to top, then a first hole penetrating through the first supporting layer, the first dielectric layer, the second supporting layer, the second dielectric layer and the third supporting layer is formed, a first conductive layer is formed in the first hole, then a second hole penetrating through the third supporting layer is formed at a preset position offset from the first conductive layer, the second dielectric layer is removed through the second hole to form a gap, next, a protective layer is formed on the side walls of the second hole and the gap, then a third hole penetrating through the second supporting layer is formed at the preset position, and the first dielectric layer is removed through the third hole, so that the second hole, the gap, the third hole and the gap left after the first dielectric layer is removed jointly form a storage structure hole; the memory structure holes are used to form complete memory cells. In the process of forming the storage structure hole, a protective layer is formed on the side wall of the second hole and the side wall of the gap, so that the top structure of the third support layer is not damaged in the operations of forming the third hole, removing the second medium layer, removing the first medium layer and the like, and the shape-preserving capability of the third support layer is further improved; meanwhile, the exposed side wall of the first conductive layer is not damaged, so that the quality of the first conductive layer is improved, uniformity of the storage structure holes can be improved, and thus, the shape-preserving capability of forming a complete storage unit in the storage structure holes is also improved, and further, the electrical performance of the storage unit and the reliability of a memory are improved.
According to another aspect of the present disclosure, an embodiment of the present disclosure further provides a semiconductor structure, where the semiconductor structure is prepared by a method for manufacturing the semiconductor structure described in the foregoing embodiments of the present disclosure, and the semiconductor structure includes:
A substrate;
a plurality of support layers positioned on the substrate and stacked along a first direction;
The first conductive layers are arranged in an array along the second direction and the third direction; the first conductive layer extends along the first direction and penetrates through a plurality of the supporting layers; the first direction is perpendicular to the second direction and the third direction, and the second direction intersects the third direction;
a plurality of dielectric layers; the dielectric layer covers the surface of the first conductive layer;
A second conductive layer; covering the surfaces of the plurality of dielectric layers.
In some embodiments, the plurality of first conductive layers form a plurality of rows, and three first conductive layers adjacent to each other in two adjacent rows of first conductive layers are arranged in a triangle.
According to yet another aspect of the present disclosure, an embodiment of the present disclosure further provides a memory including: the semiconductor structure of the above embodiments of the present disclosure, and a transistor array within the substrate, the first conductive layer being electrically connected to the transistor array.
Note that, in different types of transistors, the shapes of the gates are different; in the pillar type gate transistor, the gate is formed in a pillar form at one side of the channel region; in a half-wrapped around gate transistor, the gate half surrounds the channel region; in a Gate All Around (GAA) Gate transistor, the Gate entirely surrounds the channel region. The transistor types in the embodiments of the present disclosure may include the above-described various types, but are not limited thereto.
In several embodiments provided by the present disclosure, it should be understood that the disclosed apparatus and methods may be implemented in a non-targeted manner. The above described device embodiments are only illustrative, e.g. the division of the units is only one logical function division, and there may be other divisions in practice, such as: multiple units or components may be combined or may be integrated into another system, or some features may be omitted, or not performed. In addition, the components shown or discussed are coupled to each other or directly.
The units described as separate units may or may not be physically separate, and units displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units; some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
The features disclosed in the several method or apparatus embodiments provided in the present disclosure may be arbitrarily combined without any conflict to obtain new method embodiments or apparatus embodiments.
The foregoing is merely specific embodiments of the disclosure, but the protection scope of the disclosure is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the disclosure, and it is intended to cover the scope of the disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.
Claims (14)
1.A method of fabricating a semiconductor structure, the method comprising:
providing a stacked structure; the stacking structure comprises a first supporting layer, a first medium layer, a second supporting layer, a second medium layer and a third supporting layer which are sequentially stacked from bottom to top;
forming a plurality of first holes penetrating through the stacked structure, and forming a first conductive layer in the first holes;
Forming a second hole penetrating the third support layer at a preset position offset from the first conductive layer in a direction perpendicular to the lamination;
removing the second dielectric layer through the second hole to form a gap;
forming a protective layer at least on the side wall of the second hole and the side wall of the gap;
Forming a third hole penetrating the second support layer at the preset position;
and removing at least the first dielectric layer through the third hole.
2. The method of claim 1, wherein the material of the protective layer is the same as the material of the first dielectric layer;
the removing at least the first dielectric layer through the third hole includes:
And removing the first dielectric layer and the protective layer through the third hole.
3. The method of claim 2, wherein the materials of the first dielectric layer and the protective layer each comprise an oxide of a semiconductor material.
4. The method of fabricating a semiconductor structure of claim 1, wherein forming a protective layer comprises:
and forming the protective layer through an atomic layer deposition process.
5. The method of fabricating a semiconductor structure of claim 1, wherein the stacked structure further comprises: a sacrificial layer on the third support layer;
The forming a first hole through the stacked structure includes:
forming a first mask layer on the sacrificial layer;
performing first etching on the stacked structure by using the first mask layer to form the first hole; in the process of carrying out the first etching, the first mask layer and part of the sacrificial layer are removed at the same time;
the method further comprises the steps of:
And removing the remaining sacrificial layer.
6. The method of claim 5, wherein the etching selectivity of each dielectric layer to the sacrificial layer in the stacked structure is different; the etching selection ratio of each supporting layer and the sacrificial layer in the stacked structure is different.
7. The method of claim 6, wherein the material of each dielectric layer in the stack comprises an oxide of a semiconductor material, the material of each support layer in the stack comprises a nitride of a semiconductor material, and the sacrificial layer comprises a semiconductor material.
8. The method of fabricating a semiconductor structure of claim 1, wherein forming a first conductive layer in the first hole comprises:
forming a first initial conductive layer in the first hole on the top surface of the third support layer;
the method further comprises the steps of:
and removing the first initial conductive layer positioned on the top surface of the third supporting layer before forming the second hole, and taking the rest of the first initial conductive layer as the first conductive layer.
9. The method for manufacturing a semiconductor structure according to claim 1, wherein the plurality of first conductive layers form a plurality of rows, and three first conductive layers adjacent to each other in two adjacent rows of the first conductive layers are arranged in a triangle;
The forming a second hole through the third support layer, comprising:
forming a second mask layer on the third support layer; the pattern corresponding to the second mask layer is positioned in the middle of the triangle and is contacted with all the three first conductive layers adjacent to each other;
And performing second etching on the third supporting layer by using the second mask layer to form the second hole.
10. The method of fabricating a semiconductor structure according to claim 1, wherein forming a protective layer at least on sidewalls of the second hole and sidewalls of the gap comprises:
Forming the protective layer on the side wall of the second hole, the side wall of the gap, the top of the third supporting layer and the bottom of the gap;
forming a third hole through the second support layer at the preset position, including:
and performing third etching on the protective layer at the bottom of the gap and the second support layer by using the protective layer at the top of the third support layer as a mask layer to form the third hole.
11. The method of fabricating a semiconductor structure of claim 1, further comprising:
Forming a dielectric layer covering the first conductive layer after removing the first dielectric layer;
a second conductive layer is formed overlying the dielectric layer.
12. A semiconductor structure prepared by the method of any one of claims 1 to 11, comprising:
A substrate;
a plurality of support layers positioned on the substrate and stacked along a first direction;
The first conductive layers are arranged in an array along the second direction and the third direction; the first conductive layer extends along the first direction and penetrates through a plurality of the supporting layers; the first direction is perpendicular to the second direction and the third direction, and the second direction intersects the third direction;
a plurality of dielectric layers; the dielectric layer covers the surface of the first conductive layer;
A second conductive layer; covering the surfaces of the plurality of dielectric layers.
13. The semiconductor structure of claim 12, wherein the plurality of first conductive layers form a plurality of rows, and three first conductive layers adjacent to each other in two adjacent rows of first conductive layers are arranged in a triangle.
14. A memory, comprising: a semiconductor structure as claimed in any one of claims 12 to 13, and an array of transistors within the substrate, the first conductive layer being electrically connected to the array of transistors.
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