CN118367922A

CN118367922A - Delay phase-locked loop circuit and delay phase-locking method

Info

Publication number: CN118367922A
Application number: CN202410467556.5A
Authority: CN
Inventors: 殷宁淳
Original assignee: Yellow River Electronic Technology Co ltd; Institute Of Integrated Circuits Henan Academy Of Sciences
Current assignee: Yellow River Electronic Technology Co ltd; Institute Of Integrated Circuits Henan Academy Of Sciences
Priority date: 2024-04-18
Filing date: 2024-04-18
Publication date: 2024-07-19
Also published as: CN118367925A

Abstract

The invention provides a delay phase-locked loop circuit, comprising: the delay distribution circuit delays the zero delay signal by m times of preset time length according to the total delay time length and generates a delay signal, delays the reference time length and the analog delay time length for the delay signal to correspondingly generate a first clock signal and a second clock signal, and adjusts the digital delay time length and the analog delay time length according to the phase relation between the first clock signal and the second clock signal and the phase relation between the third clock signal, so that the adjusted second clock signal is output when the adjusted analog delay time length is within the preset time length range; a second phase comparator for phase comparing the adjusted second clock signal with the reference clock signal and generating a first signal and a second signal; and the voltage generating circuit generates a regulating voltage according to the first signal and the second signal to readjust the adjusted analog delay time length until the readjusted second clock signal output by the delay distributing circuit is synchronous with the reference clock signal.

Description

Delay phase-locked loop circuit and delay phase-locking method

Technical Field

The present invention relates to the field of integrated circuits, and in particular, to a delay locked loop circuit and a delay locked method.

Background

The clock signal is widely used as a signal for synchronizing operation timings of the semiconductor device. When a clock signal generated from an external device is used for an internal circuit of a semiconductor device, the internal circuit may cause a time delay problem. Accordingly, a delay locked loop circuit is generally integrated in a semiconductor device to compensate for a time delay so as to synchronize a clock signal inside the semiconductor device with an externally input clock signal.

However, current delay locked loop circuits generally employ all-digital circuits to adjust the time delay. However, the delay time of each delay unit in the all-digital circuit is a fixed value, so that the problems of poor delay precision and the like are caused.

Disclosure of Invention

The application provides a delay phase-locked loop circuit, which at least comprises: the delay distribution circuit is configured to receive the zeroth delay signal, delay the zeroth delay signal by m times of preset time length according to the total delay time length and generate an mth delay signal, delay the reference time length and the analog delay time length for the mth delay signal respectively to correspondingly generate a first clock signal and a second clock signal, determine whether to change the analog delay time length into the adjusted analog delay time length and change the m times of preset time length into the preset time length (m+1) according to the phase relation between the first clock signal and the second clock signal, and output the adjusted second clock signal when the adjusted analog delay time length is in the preset time length range; wherein the sum of the m times of preset time length and the analog time delay time length is not more than the total time delay time length, the reference time length is more than the preset time length, and the adjusted analog time delay time length is the difference of the analog time delay time length minus the preset time length; a second phase comparator coupled to the delay distribution circuit and configured to receive the adjusted second clock signal and the reference clock signal, to phase compare the adjusted second clock signal and the reference clock signal and to generate a first signal and a second signal; and the voltage generating circuit is coupled with the second phase comparator and is configured to generate a regulating voltage according to the first signal and the second signal so as to readjust the adjusted analog delay time length until the readjusted second clock signal output by the delay distributing circuit is synchronous with the reference clock signal.

In one embodiment, when the first clock signal is advanced or synchronized with the second clock signal, the preset time length is increased by m times, so that the analog delay time length is reduced; when the first clock signal lags behind the second clock signal, the m times of preset time length is kept unchanged, so that the analog delay time length is also kept unchanged.

In one embodiment, the delay distribution circuit includes: the series adjustable digital delay circuit is configured to receive the zeroth delay signal, delay the zeroth delay signal by m times of preset time length and generate a delay signal, wherein the preset time length is the delay time of each digital delay unit in the series adjustable digital delay circuit to the received signal; a delay reference circuit coupled to the series adjustable digital delay circuit configured to delay the delay signal by a reference time length and generate a first clock signal; and the analog delay circuit is coupled with the series adjustable digital delay circuit and is configured to receive the mth delay signal, delay the analog delay time length for the mth delay signal to generate a second clock signal, and readjust the adjusted analog delay time length according to the regulation voltage.

In one embodiment, the delay distribution circuit further comprises: a phase comparison circuit coupled to the delay reference circuit and the analog delay circuit, respectively, and configured to phase compare the first clock signal and the second clock signal to generate a first phase signal; and a control circuit coupled between the phase comparison circuit and the series adjustable digital delay circuit and configured to generate a plurality of control signals according to the first phase signal, wherein the plurality of control signals control whether the number of digital delay units connected in the series adjustable digital delay circuit is changed from m to (m+1) so as to change the analog delay time length to the adjusted analog delay time length and change the m times of the preset time length to the preset time length (m+1), and further enable the analog delay circuit to output the adjusted second clock signal.

In an embodiment, when the first phase signal indicates that the first clock signal is advanced or synchronous with the second clock signal, an mth control signal in the plurality of control signals jumps from the second level to the first level, an (m+1) th control signal in the plurality of control signals jumps from the first level to the second level, and other control signals keep maintaining the first level, so that the number of digital delay units connected in the series adjustable digital delay circuit is changed from m to (m+1); when the first phase signal indicates that the first clock signal lags behind the second clock signal, the mth control signal in the plurality of control signals keeps keeping the second level, and other control signals keep keeping the first level, so that the number of the digital delay units connected in the series adjustable digital delay circuit is still m.

In an embodiment, when the number of digital delay units connected in the series adjustable digital delay circuit is changed from m to (m+1), the series adjustable digital delay circuit delays the zeroth delay signal by a preset time length (m+1) times and generates the (m+1) th delay signal, the analog delay circuit delays the (m+1) th delay signal by an adjusted analog delay time length and generates an adjusted second clock signal, the delay reference circuit delays the (m+1) th delay signal by a reference time length and generates an adjusted first clock signal, and the phase comparison circuit compares the adjusted first clock signal with the adjusted second clock signal in phase and generates an adjusted first phase signal, wherein when the adjusted first phase signal indicates that the adjusted first clock signal lags the adjusted second clock signal, the analog delay circuit outputs the adjusted second clock signal.

In an embodiment, the series adjustable digital delay circuit includes a plurality of digital delay units and a plurality of switch circuits correspondingly arranged, wherein each digital delay unit is correspondingly connected with one switch circuit, an mth switch circuit in the switch circuits is controlled to be conducted by an mth control signal in the control signals, and other switch circuits except the mth switch circuit are controlled to be disconnected by other control signals except the mth control signal, so that the mth digital delay unit delays the zeroth delay signal to generate the mth delay signal, and the mth delay signal is further output to the analog delay circuit and the delay reference circuit respectively.

In one embodiment, the phase comparison circuit includes a first phase comparator and a reset circuit; the first phase comparator is respectively coupled with the delay reference circuit and the analog delay circuit, and the reset circuit is coupled with the first phase comparator; the first phase comparator is configured to control the first phase signal to perform a first level shift according to a phase relationship between the first clock signal and the second clock signal, and the reset circuit is configured to generate a reset signal according to the first phase signal and the second clock signal to control the first phase signal to perform a second level shift.

In one embodiment, under the condition that the first clock signal is ahead of or synchronous with the second clock signal, when the first rising edge of the first clock signal arrives, the first phase signal jumps from the first level to the second level, and when the first rising edge of the second clock signal arrives, the reset signal jumps from the first level to the second level, so as to control the first phase signal to jump from the second level to the first level; the first phase signal and the reset signal are both always at the first level under the condition that the first clock signal lags behind the second clock signal.

In an embodiment, the first phase comparator includes a first trigger, a first not gate, a second not gate, a first nor gate, a second trigger, a third not gate, a fourth not gate and a second nor gate, where an input end of the first not gate receives the second clock signal, an output end of the first not gate is connected to an input end of the first trigger, a clock end of the first trigger receives the first clock signal, an output end of the first trigger is connected to the reset circuit to output the first phase signal to the reset circuit, a first input end of the second nor gate is connected to an output end of the first trigger, a second input end of the second nor gate is connected to the reset circuit to receive the reset signal generated by the reset circuit, an output end of the second nor gate is connected to an input end of the fourth not gate, an output end of the fourth not gate is connected to a reset end of the second trigger, an input end of the third not gate receives the first clock signal, an output end of the third not gate is connected to an input end of the second trigger, a first input end of the second trigger is connected to the first output end of the second trigger.

In an embodiment, the reset circuit includes a plurality of flip-flops, a third nor gate and a fifth nor gate connected in sequence, where an input terminal of a first flip-flop receives the first phase signal, a clock terminal of each flip-flop receives the second clock signal, an output terminal of a last flip-flop is connected to a reset terminal of each flip-flop, an output terminal of each flip-flop is connected to an input terminal of the third nor gate, an output terminal of the third nor gate is connected to the fifth nor gate, the fifth nor gate outputs the reset signal, and the plurality of flip-flops are triggered in sequence according to a plurality of edges of the second clock signal.

In an embodiment, the control circuit includes a plurality of control units, each control unit has the same configuration, an mth control unit in the plurality of control units includes a nand gate, a not gate and a trigger, wherein the nand gate receives the first phase signal and the (m-1) th control signal, an output end of the nand gate is connected to an input end of the not gate, an output end of the not gate is connected to a clock end of the trigger, a power supply voltage is connected to an input end of the trigger, an output end of the trigger is connected to the mth switching circuit to output the mth control signal to the mth switching circuit, and a reset end of the trigger is connected to an output end of the (m+1) th control unit to receive the (m+1) th control signal.

In an embodiment, when the adjusted second clock signal leads the reference clock signal, the voltage value of the regulated voltage is increased to increase the adjusted analog delay time; when the adjusted second clock signal lags behind the reference clock signal, the voltage value of the regulating voltage is reduced so as to reduce the adjusted analog delay time; when the adjusted second clock signal is synchronous with the reference clock signal, the voltage value of the regulating voltage is kept unchanged, so that the adjusted analog delay time length is kept unchanged.

The application also provides a delay phase locking method which is applied to the delay phase locking loop circuit in any embodiment, and the delay phase locking method comprises the following steps:

The delay distribution circuit receives a zeroth delay signal, delays the zeroth delay signal by m times of preset time length according to the total delay time length and generates an mth delay signal, delays the mth delay signal by a reference time length and an analog delay time length respectively to correspondingly generate a first clock signal and a second clock signal, and determines whether to change the analog delay time length into the adjusted analog delay time length and change the m times of preset time length into (m+1) times of preset time length according to the phase relation between the first clock signal and the second clock signal; wherein the sum of the m times of preset time length and the analog time delay time length is not more than the total time delay time length, the reference time length is more than the preset time length, and the adjusted analog time delay time length is the difference of the analog time delay time length minus the preset time length; when the adjusted analog delay time length is within a preset time length range, the delay distributing circuit outputs an adjusted second clock signal; the second phase comparator receives the adjusted second clock signal and the reference clock signal, performs phase comparison on the reference clock signal and the adjusted second clock signal and generates a first signal and a second signal; the voltage generating circuit generates a regulating voltage according to the first signal and the second signal to readjust the adjusted analog delay time length until the readjusted second clock signal output by the delay distributing circuit is synchronous with the reference clock signal.

The delay phase-locked loop circuit of the application initially adjusts the analog delay time length and m times of preset time length so that the adjusted analog delay time length is as small as possible within the range of the preset time length, and then further finely adjusts the adjusted analog delay time length by utilizing the regulating voltage. The method can reduce the frequency of phase comparison of the adjusted second clock signal and the reference clock signal, thereby realizing quick locking of the delay phase-locked loop circuit. In addition, the series adjustable digital delay circuit and the analog delay circuit are used for jointly delaying the signals, on one hand, because the delay time of the analog delay circuit to the signals is continuously adjustable, the delay time of the delay phase-locked loop circuit to the signals is also continuously adjustable, and meanwhile, the time jumping caused by the single use of the digital delay circuit to delay the signals is avoided, and the delay precision is further improved; on the other hand, the number of the digital delay units connected in the series adjustable digital delay circuit can be reduced, so that the power consumption is reduced, and the performance of the chip is improved.

Drawings

The objects, specific structural features and advantages of the present invention will be further understood from the following description in conjunction with some embodiments of the present invention and the accompanying drawings.

FIG. 1 is a block diagram of a delay distribution circuit according to one embodiment of the present invention;

FIG. 2 is a circuit diagram of a series adjustable digital delay circuit according to one embodiment of the invention;

fig. 3 is a circuit diagram of a digital delay unit according to one embodiment of the invention;

FIG. 4 is a circuit diagram of a delay reference circuit according to one embodiment of the invention;

FIG. 5 is a circuit diagram of an analog delay circuit according to one embodiment of the invention;

FIG. 6 is a circuit diagram of a first phase comparator according to one embodiment of the present invention;

FIG. 7 is a circuit diagram of a reset circuit according to one embodiment of the invention;

FIG. 8 is a circuit diagram of a control circuit according to one embodiment of the invention;

Fig. 9 is a timing diagram of the first clock signal CLKA ', the second clock signal CLKA, the first phase signal PH ' and the RESET signal RESET when the first clock signal CLKA ' leads the second clock signal CLKA according to an embodiment of the invention;

Fig. 10 is a timing diagram of the first clock signal CLKA ', the second clock signal CLKA, the first phase signal PH ' and the RESET signal RESET when the first clock signal CLKA ' lags behind the second clock signal CLKA according to an embodiment of the invention;

FIG. 11 is a method flow diagram illustrating a delay allocation method according to one embodiment of the invention;

Fig. 12 is a block diagram of a delay locked loop circuit according to one embodiment of the invention;

FIG. 13 is a circuit diagram of a second phase comparator and voltage generation circuit according to one embodiment of the invention;

FIG. 14 is a timing diagram of the reference clock signal CLK_REF, the adjusted second clock signal CLKB, the first signal PH _H1, the second signal PH _H2 and the RESET signal RESET3 when the adjusted second clock signal CLKB leads the reference clock signal CLK_REF according to one embodiment of the invention;

FIG. 15 is a timing diagram of the reference clock signal CLK_REF, the adjusted second clock signal CLKB, the first signal PH _H1, the second signal PH _H2 and the RESET signal RESET3 when the adjusted second clock signal CLKB lags behind the reference clock signal CLK_REF according to one embodiment of the invention;

FIG. 16 is a timing diagram of the reference clock signal CLK_REF, the adjusted second clock signal CLKB, the first signal PH _H1, the second signal PH _H2 and the RESET signal RESET3 when the adjusted second clock signal CLKB is synchronized with the reference clock signal CLK_REF according to one embodiment of the invention;

Fig. 17 is a method flow diagram of a delay locked loop method according to an embodiment of the invention.

Detailed Description

The objects, specific structural features and advantages of the present application will be further understood from the following description in conjunction with some embodiments of the present application and the accompanying drawings. In addition, numerous specific details are set forth in the following description in order to provide a better illustration of the application. It will be understood by those skilled in the art that the present application may be practiced without these specific details. In other instances, well-known methods, procedures, components, and circuits have not been described in detail. The description is made in order to highlight the gist of the present application. The terms "connected," "coupled," and the like in connection with the present application are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

In the present application, the reference clock signal clk_ref is a square wave having a fixed clock period within a certain error range.

In an embodiment of the present application, the first level may be a low level and the second level may be a high level. It will be appreciated that a simple replacement of the circuit of the present application by a person skilled in the art may also implement a high level for the first level and a low level for the second level.

As shown in fig. 1, the delay distributing circuit 100 includes a stage-adjustable digital delay circuit 10, a delay reference circuit 11, an analog delay circuit 12, a phase comparing circuit 13, and a control circuit 14.

The series adjustable digital delay circuit 10 is configured to delay the zeroth delay signal CLK0 by m times a preset time length to generate the mth delay signal, where the preset time length is a time delayed by each digital delay unit in the series adjustable digital delay circuit 10 to the received signal.

In an embodiment, as shown in fig. 2, the stage-number-adjustable digital delay circuit 10 includes n digital delay units 10_1, 10_2, 10_n and n switch circuits 101_1, 101_2, 101_n, where n is equal to or greater than 2 and n is an integer. The n digital delay units are sequentially connected, and the output end of the mth digital delay unit 10_m is connected with an mth switching circuit, wherein m is more than or equal to 1 and less than or equal to n, and m is an integer. For example, the stage-number adjustable digital delay circuit 10 includes a first digital delay unit 10_1, a second digital delay unit 10_2, a first switch circuit 101_1, and a second switch circuit 101_2. The first digital delay unit 10_1 is connected with the second digital delay unit 10_2, the first digital delay unit 10_1 receives the zeroth delay signal CLK0, the output end of the first digital delay unit 10_1 is connected with the first switch circuit 101_1, and the output end of the second digital delay unit 10_2 is connected with the second switch circuit 101_2.

Each digital delay unit may delay the received signal with equal delay times. The application takes the delay time of each digital delay unit as a preset duration as an example. For example, when the first switch circuit 101_1 is turned on and the other switch circuits are turned off, the first digital delay unit 10_1 delays the zeroth delay signal CLK0 by a preset period and generates the first delay signal CLK1 (reference numerals 1,2, and the number of digital delay units, n are merely for distinguishing from which delay signal is output, and do not indicate that a plurality of delay signals are generated at the same time). The first delay signal CLK1 is transmitted to the delay reference circuit 11 and the analog delay circuit 12 through the first switch circuit 101_1, respectively. It can be seen that the first delay signal CLK1 lags the zero delay signal CLK0 and the lag time is a predetermined duration. For another example, when the second switch circuit 101_2 is turned on and the other switch circuits are turned off, the zero-th delay signal CLK0 becomes the second delay signal CLK2 after being delayed by the first digital delay unit 10_1 and the second digital delay unit 10_2, and the second delay signal CLK2 is transmitted to the delay reference circuit 11 and the analog delay circuit 12 through the second switch circuit 101_2, respectively. It can be seen that the second delay signal CLK2 lags the zero delay signal CLK0 by a predetermined amount of time twice.

In some embodiments, as shown in fig. 3, each digital delay unit includes an AND gate AND1, an AND gate AND2, an AND gate AND3, AND an AND gate AND4 connected in sequence. For example, for the first digital delay unit 10_1, the zeroth delay signal CLK0 becomes the first delay signal CLK1 through AND gates AND1, AND2, AND3, AND4 in order. Since each and gate can delay the received signal by a fixed time, the first delay signal CLK1 lags the zeroth delay signal CLK0 by a fixed time of 4 times. The fixed time of 4 times is the preset time length. Of course, the four logic gates in each digital delay cell may be other types of logic gates (e.g., OR gates, NOT gates, etc.), as not limiting herein. Different preset time periods can be determined according to the types and the number of the logic gates.

In one embodiment, as shown in fig. 2, each switching circuit includes a first branch and a second branch. The first branch of the mth switching circuit 101_m is coupled between the mth digital delay unit 10_m and the delay reference circuit 11, and the second branch of the mth switching circuit 101_m is coupled between the mth digital delay unit 10_m and the analog delay circuit 12, wherein m is greater than or equal to 1 and less than or equal to n, and m is an integer. Only one of the n switching circuits is turned on under the control of the corresponding control signal S ₁、S₂、......、S_n. For example, if the control signal S ₁ controls the first switch circuit 101_1 to be turned on, the control signal S ₂、S₃、......、S_n other than the control signal S ₁ controls the other switch circuits other than the first switch circuit 101_1 to be turned off.

The first branch 1011 and the second branch 1012 of the first switch circuit 101_1 are described below as an example, and the first branch and the second branch of other switch circuits are similar to each other, which is not described herein again. The first branch 1011 includes a PMOS transistor P11 and an NMOS transistor N11. The drain of the PMOS transistor P11 is connected with the source of the NMOS transistor N11 to form an input end of the first branch 1011 (the input end can receive the first delay signal CLK 1), the source of the PMOS transistor P11 is connected with the drain of the NMOS transistor N11 to form an output end of the first branch 1011 (the output end can output the first delay signal CLK 1), and the gate of the PMOS transistor P11 receives the inverted control signalThe gate of NMOS transistor N11 receives control signal S ₁ (control signals will be described in detail below, and S ₁ andActs on the first switch circuits 101_1, S ₂, andActs on the second switching circuit 101_2, & gt, S _n, andActing on the n-th switching circuit 101—n). The second branch 1012 includes a PMOS tube P '11 and an NMOS tube N '11, the source of the PMOS tube P '11 is connected with the drain of the NMOS tube N '11 to form an input end of the second branch 1012 (the input end can receive the first delay signal CLK 1), the drain of the PMOS tube P '11 is connected with the source of the NMOS tube N '11 to form an output end of the second branch 1012 (the output end can output the first delay signal CLK 1), and the gate of the PMOS tube P '11 receives the inverted control signalThe gate of NMOS transistor N'11 receives control signal S ₁. When the control signal S ₁ is at the second level (e.g., high level), the PMOS transistor P11 and the NMOS transistor N11 are turned on so that the first delay signal CLK1 is transmitted to the delay reference circuit 11, and the PMOS transistor P '11 and the NMOS transistor N'11 are turned on so that the first delay signal CLK1 is transmitted to the analog delay circuit 12. When the control signal S ₁ is at the first level (e.g., low level), the PMOS transistor P11 and the NMOS transistor N11, and the PMOS transistor P '11 and the NMOS transistor N'11 are all turned off, so that the first delay signal CLK1 cannot be transmitted to the delay reference circuit 11 and the analog delay circuit 12. Of course, in other embodiments, the first and second branches may also be formed of transistors, junction field effect transistors, and the like.

The delay reference circuit 11, coupled to the stage-number-adjustable digital delay circuit 10, is configured to delay the mth delay signal CLKm by a reference time period T _REF to generate the first clock signal CLKA', wherein the reference time period T _REF is slightly greater than the preset time period. For example, when the preset time period is 100ps, the reference time period T _REF is 101ps.

In some embodiments, as shown in fig. 4, the delay reference circuit 11 includes at least AND gates AND5, AND6, AND7, AND8, AND load capacitances C3, C4, C5, AND C6, which are connected in sequence. The connection is shown in fig. 4. Since each and gate may delay the received signal by a first fixed time period and each load capacitor may also delay the transmitted signal by a second fixed time period, the first clock signal CLKA' lags the mth delay signal CLKm by a sum of the first fixed time period and the second fixed time period of 4 times. The sum of the first fixed duration of 4 times and the second fixed duration of 4 times is the reference duration T _REF, and the reference duration T _REF is a fixed value. Compared with the preset time length of a single digital delay unit, since each AND gate is coupled with a load capacitor, the reference time length T _REF is slightly longer than the preset time length. In other embodiments, on the premise of ensuring that the reference time period T _REF is slightly longer than the preset time period, the number of logic gates may be arbitrarily set, for example, 3,5, 6, etc., and the types of logic gates may be not gates, or gates, nand gates, etc., which are not limited herein.

The analog delay circuit 12 is coupled to the stage-number-adjustable digital delay circuit 10 and is configured to delay the mth delay signal CLKm by an analog delay time period T _ANA to generate the second clock signal CLKA, and to readjust the adjusted analog delay time period according to the regulated voltage Vc (Vc will be described later). The sum of the digital delay time length (m times of the preset time length) and the analog delay time length T _ANA is not greater than the total delay time length T _TOTAL. If the second clock signal CLKA lags behind the first clock signal CLKA', the analog delay time period T _ANA is longer than the reference time period T _REF, which indicates that the analog delay time period T _ANA is longer than the preset time period, and the number of digital delay units connected in the series adjustable digital delay circuit 10 can be adjusted to increase the digital delay time period, so as to reduce the analog delay time period T _ANA.

In some embodiments, as shown in fig. 5, the analog delay circuit 12 may include a first not gate 121, a second not gate 122, a first MOS capacitor C1, and a second MOS capacitor C2. The input end of the first not gate 121 receives the mth delay signal CLKm, the output end of the first not gate 121 is connected to the input end of the second not gate 122 and the first end of the first MOS capacitor C1, the output end of the second not gate 122 is connected to the first end of the second MOS capacitor C2 to output the second clock signal CLKA, and the second end of the first MOS capacitor C1 and the second end of the second MOS capacitor C2 are both connected to the regulated voltage Vc (Vc will be described in detail below). The first MOS capacitor C1 and the second MOS capacitor C2 may be formed by PMOS transistors or NMOS transistors, for example, the source, the substrate, and the drain of the PMOS transistors or NMOS transistors are shorted together to form a first end, and the gate of the PMOS transistors or NMOS transistors forms a second end.

The mth delay signal CLKm is changed into a second clock signal CLKA after passing through the first not gate 121, the first MOS capacitor C1, the second not gate 122 and the second MOS capacitor C2, wherein the first MOS capacitor C1 and the second MOS capacitor C2 can both charge and discharge according to the received signal to delay the signal, so that the second clock signal CLKA lags behind the mth delay signal CLKm, the lag time is an analog delay time period T _ANA, and the sum of the analog delay time period T _ANA and the digital delay time period is not greater than the total delay time period T _TOTAL. Meanwhile, the regulation voltage Vc can change the capacitance values of the first MOS capacitor C1 and the second MOS capacitor C2, so that the delay time of the first MOS capacitor C1 and the second MOS capacitor C2 to signals is changed, and the purpose of fine-tuning the adjusted analog delay time is achieved.

A phase comparison circuit 13, coupled to the delay reference circuit 11 and the analog delay circuit 12, respectively, is configured to phase compare the first clock signal CLKA 'and the second clock signal CLKA and generate a first phase signal PH'. Wherein the first phase signal PH 'indicates the magnitude relationship of the reference time period T _REF and the analog delay time period T _ANA, i.e., the phase relationship of the first clock signal CLKA' and the second clock signal CLKA.

When the first phase signal PH 'indicates that the first clock signal CLKA' is advanced or synchronized with the second clock signal CLKA, the mth control signal S _m in the plurality of control signals S ₁、S₂、......、S_n transitions from the second level to the first level, the (m+1) th control signal S _(m+1) in the plurality of control signals S ₁、S₂、......、S_n transitions from the first level to the second level, and the other control signals continue to keep the first level, so that the number of digital delay units accessed in the series adjustable digital delay circuit 10 is changed from m to (m+1); when the first phase signal PH 'indicates that the first clock signal CLKA' lags behind the second clock signal CLKA, the mth control signal S _m of the plurality of control signals S ₁、S₂、......、S_n keeps on the second level, and the other control signals keep on the first level, so that the number of digital delay units connected in the series adjustable digital delay circuit 10 is still m.

In some embodiments, as shown in fig. 1, the phase comparison circuit 13 includes a first phase comparator 131 and a reset circuit 132. The first phase comparator 131 is coupled to the delay reference circuit 11 and the analog delay circuit 12, respectively, and the reset circuit 132 is coupled to the first phase comparator 131. The first phase comparator 131 is configured to control the first phase signal PH 'to perform a first level shift according to a phase relationship between the first clock signal CLKA' and the second clock signal CLKA, and the RESET circuit 132 is configured to generate a RESET signal RESET according to the first phase signal PH 'and the second clock signal CLKA to control the first phase signal PH' to perform a second level shift. Under the condition that the first clock signal CLKA ' is ahead of or synchronous with the second clock signal CLKA ', when the first rising edge of the first clock signal CLKA ' arrives, the first phase signal PH ' jumps from the first level to the second level, and when the first rising edge of the second clock signal CLKA arrives, the RESET signal RESET jumps from the first level to the second level, thereby controlling the first phase signal PH ' to jump from the second level to the first level; the first phase signal PH 'and the RESET signal RESET are uniformly at the first level under the condition that the first clock signal CLKA' lags behind the second clock signal CLKA.

In some embodiments, as shown in fig. 6, the first phase comparator 131 includes a first flip-flop 1312, a third nor gate 1311, a fourth nor gate 1313, a first nor gate 1314, a second flip-flop 1316, a fifth nor gate 1315, a sixth nor gate 1317, and a second nor gate 1318. The input terminal of the third nor gate 1311 receives the second clock signal CLKA, the output terminal of the third nor gate 1311 is connected to the input terminal D of the first flip-flop 1312, the clock terminal Ck of the first flip-flop 1312 receives the first clock signal CLKA ', the output terminal Q of the first flip-flop 1312 is connected to the RESET circuit 132 to output the first phase signal PH ', the first input terminal Q of the second nor gate 1318 is connected to the output terminal Q of the first flip-flop 1312, the second input terminal of the second nor gate 1318 is connected to the RESET circuit 132 to receive the RESET signal RESET generated by the RESET circuit 132, the output terminal of the second nor gate 1318 is connected to the input terminal R of the sixth nor gate 1317, the input terminal of the fifth nor gate 1315 receives the first clock signal CLKA ', the output terminal of the fifth nor gate 1315 is connected to the input terminal D of the second flip-flop 1316, the clock terminal Ck of the second flip-flop 1316 receives the second clock signal RESET generated by the RESET circuit 132, the output terminal of the second nor gate 1318 is connected to the RESET terminal R of the first flip-flop 1316, and the output terminal 1314 is connected to the output terminal of the fourth nor gate 1313 is connected to the RESET terminal of the first flip-flop 1316. The operation principle of the first phase comparator 131 will be described below.

In some embodiments, as shown in fig. 7, the reset circuit 132 includes n flip-flops 132_1, 132_2, a third nor gate 1321, and a seventh nor gate 1322 connected in sequence, where n is an integer greater than or equal to 2. The input terminal D of the first flip-flop 132_1 receives the first phase signal PH', the clock terminal Ck of the first flip-flop 132_1 receives the second clock signal CLKA, the output terminal Q of the first flip-flop 132_1 is connected to the input terminal D of the second flip-flop 132_2 to output the signal PH ₁, the clock terminal Ck of the second flip-flop 132_2 receives the second clock signal CLKA, and so on, the output terminal Q of the (n-1) -th flip-flop 132_1 is connected to the input terminal D of the n-th flip-flop 132_n to output the signal PH _(n-1), the clock terminal Ck of the n-th flip-flop 132_n receives the second clock signal CLKA, and the output terminals Q of the n-th flip-flop 132_n are respectively connected to the RESET terminals R of the n flip-flops to output the signals _n, the n flip-flops 132_1, 132_2, the output terminals Q of the n flip-flops 132_132_n are all connected to the input terminal of the third nor gate 1321, and the output terminal 1322 of the seventh nor gate 1322. n flip-flops 132_1, 132_2, &.&..the n flip-flops 132_1 are sequentially triggered on multiple rising edges of the second clock signal CLKA, e.g., flip-flop 132_1 is triggered on the first rising edge of the second clock signal CLKA, the flip-flop 132_2 is triggered on the second rising edge of the second clock signal CLKA. In an actual circuit design, the number of flip-flops in the reset circuit 132 may be set according to actual requirements, for example, 3,6, etc., which is not limited herein.

Under the condition that the total delay time period T _TOTAL is not less than the sum of the digital delay time period (preset time period of m times) and the analog delay time period T _ANA, there may be the following two cases: first case: the analog delay time period T _ANA is not less than the reference time period T _REF (as represented by the first clock signal CLKA' leading or being synchronized to the second clock signal CLKA); second case: the analog delay time period T _ANA is less than the reference time period T _REF (which is manifested as the first clock signal CLKA' lagging the second clock signal CLKA).

The operation principle of the phase comparison circuit 13 will be described with reference to fig. 5, 6, and 8 to 10, based on the two cases described above:

for the first case: the timing diagram of the signals is shown in fig. 9.

Before time t1, the first phase signal PH', the signal PH ₁、PH₂、......、PH_n, and the RESET signal RESET are all at low level.

At time t1, the rising edge of the first clock signal CLKA' arrives and the first flip-flop 1312 is triggered. At this time, the second clock signal CLKA at the low level becomes a signal at the high level after passing through the third nor gate 1311, and the signal at the high level is input to the input terminal D of the first flip-flop 1312, so that the first phase signal PH' transitions from the low level to the high level.

At time t2, the first rising edge of the second clock signal CLKA comes, and the flip-flop 132_1 in the reset circuit 132 is triggered. At this time, the first phase signal PH' at the high level is input to the flip-flop 132_1, thereby causing the signal PH ₁ to transition from the low level to the high level. Since neither the second nor the n-th rising edge of the second clock signal CLKA has arrived, neither the flip-flop 132_2 nor the n-th rising edge is triggered, the signal PH ₂、......、PH_n is at a low level. The signal PH ₁ at the high level and the signal PH ₂、......、PH_n at the low level change to the RESET signal RESET at the high level (i.e., the RESET signal RESET transitions from the low level to the high level) after passing through the third nor gate 1321 and the seventh nor gate 1322. When the RESET signal RESET transitions to a high level, the RESET signal RESETA in fig. 7 also transitions from a low level to a high level, and the first phase signal PH' then transitions from a high level to a low level.

At times t2, t3, t4, and/or at times t5, flip-flop 132_1, flip-flop 132_2, and/or 132—n are sequentially triggered, signal PH ₁ is at a high level at times t 1-t 3, signal PH ₂ is at a high level at times t 3-t 4, and so on, signal PH _n is at a high level at times t 5-t 6.

At time t5, when the signal PH _n transitions to a high level, the flip-flops 132_1, 132_2, and 132—n are all RESET, so that the signal PH _n transitions from a high level to a low level at time t6, and the RESET signal RESET also transitions from a high level to a low level. Subsequently, upon the arrival of the next rising edge of the first clock signal CLKA', the phase comparison circuit 13 starts the next phase comparison.

For the second case: the timing diagram of the signals is shown in fig. 10.

Before time t7, the first phase signal PH', the signal PH ₁、PH₂、......、PH_n, and the RESET signal RESET are all at low level.

At time t7, the rising edge of the second clock signal CLKA comes, and the second flip-flop 1316 is triggered. At this time, the first clock signal CLKA' at the low level is changed to a signal at the high level through the fifth nor gate 1315, and the signal at the high level is input to the input terminal D of the second flip-flop 1316, and the signal output from the output terminal Q of the second flip-flop 1316 transitions from the low level to the high level. At this time, the RESET signal RESETA transitions to a high level no matter what level state the RESET signal RESET is in, so that the first phase signal PH' is continuously at a low level. Although the flip-flop 132_1 is triggered at time t7, the first phase signal PH' is at a low level, and the signals PH ₁、PH₂、......、PH_n are all kept at a low level. The signal PH ₁、PH₂、......、PH_n at the low level becomes the RESET signal RESET continuing to be at the low level after passing through the third nor gate 1321 and the seventh nor gate 1322.

At time t8, the first rising edge of the first clock signal CLKA' arrives and the flip-flop 1312 is triggered. At this time, the second clock signal CLKA at the high level becomes a signal at the low level after passing through the third nor gate 1311, and the signal at the low level is input to the input terminal D of the first flip-flop 1312, so that the first phase signal PH' continues to be at the low level. Since the first phase signal PH' is always at a low level, the signal PH ₁、PH₂、......、PH_n is always at a low level regardless of whether the flip-flops 132_1, 132_2, 132—n are triggered.

In summary, in the first case, the first phase signal PH 'will be level shifted, while in the second case the first phase signal PH' is always at the same level.

The control circuit 14, coupled between the first phase comparator 131 and the stage-number adjustable digital delay circuit 10, is configured to generate a plurality of control signals S ₁、S₂、......、S_n according to the first phase signal PH', where the plurality of control signals S ₁、S₂、......、S_n control whether the number of digital delay units connected in the stage-number adjustable digital delay circuit 10 is changed from m to (m+1), so as to change the analog delay time period T _ANA to an adjusted analog delay time period and change a preset time period m to a preset time period m+1, and further make the analog delay circuit 12 output the adjusted second clock signal CLKB.

In an embodiment, the control circuit 14 includes n control units 14_1, 14_2. Each control unit has the same configuration. Taking the mth control unit 14_m as an example, the mth control unit 14_m includes a nand gate 144, a not gate 145, and a flip-flop 146. The first input terminal of the NAND gate 144 receives the first phase signal PH', the second input terminal of the NAND gate 144 is connected to the output terminal of the (m-1) -th control unit 14_ (m-1) to receive the control signal S _(m-1), the output terminal of the NAND gate 144 is connected to the input terminal of the NAND gate 145, the output terminal of the NAND gate 145 is connected to the clock terminal Ck of the flip-flop 146, the input terminal D of the flip-flop 146 receives the power supply voltage VH (high level), the output terminal Q of the flip-flop 146 is connected to the second input terminal of the NAND gate 147 and the reset terminal of the (m-1) -th control unit 14_1 in the (m+1) -th switching circuit 101_m, the (m+1) -th control unit 14_1 to output the (m-1) -th control signal S _m thereto, and the reset terminal R of the flip-flop 146 is connected to the output terminal of the (m+1) -th control unit 14_m+1. Since the control signal S _m is again used as the reset signal of the flip-flop 143, the control signal S _(m-1) is reset to the first level when the control signal S _m is at the second level.

The present application is exemplified by any adjacent three control units to describe how the level state of the control signal is changed, wherein the specific connection relationship of the (m-1) th control unit 14_ (m-1), the (m+1) th control unit 14_m, and the (m+1) th control unit 14_ (m+1) is shown in fig. 8.

In the initial state, the control signal S _m is at a high level, and the control signal S _(m-1) and the control signal S _(m+1) are both at a low level.

For the first case: as shown in fig. 9, at time t1, when the first phase signal PH' transitions from low to high, the signal output from the nand gate 147 transitions from high to low, and the trigger signal output from the not gate 148 transitions from low to high. When the trigger signal output from the not gate 148 transitions from low to high, the trigger 149 is triggered such that the control signal S _(m+1) also transitions from low to high. When the control signal S _(m+1) transitions from low to high, the flip-flop 146 is reset so that the control signal S _m transitions from high to low. While control signal S _(m-1) continues to remain low. The number of the digital delay units accessed so far is changed from m to (m+1).

For the second case: as shown in fig. 10, since the first phase signal PH' is not level-shifted, the control signal S _m is continuously at a high level, and the control signal S _(m-1) and the control signal S _(m+1) are continuously at a low level, i.e. the number of the accessed digital delay units is continuously m.

In summary, the working principle of the delay distribution circuit is as follows:

In the initial state, the control signal S _m is at a high level, and the other control signals are all at a low level, so that the mth switch circuit 101—m is turned on and the other switch circuits are turned off, and the mth delay signal CLK0 is delayed by the m digital delay Shi Shanyuan and becomes the mth delay signal CLKm, wherein the delay time of the m digital delay unit to the mth delay signal CLK0 is m times of the preset digital delay time.

The delay reference circuit 11 delays the mth delay signal CLKm by a reference time period T _REF to generate the first clock signal CLKA', wherein the reference time period T _REF is slightly greater than the preset time period.

The analog delay circuit 12 delays the mth delay signal CLKm by an analog delay period T _ANA to generate the second clock signal CLKA, wherein the sum of the preset period and the analog delay period T _ANA is not greater than the total delay period T _TOTAL.

The phase comparison circuit 13 performs phase comparison on the first clock signal CLKA 'and the second clock signal CLKA and generates a first phase signal PH'. If the first phase signal PH' is shown in fig. 9, it can be seen from the above that the number of the accessed digital delay units is changed from m to (m+1), where the (m+1) digital delay units delay the zeroth delay signal CLK0 by a preset time length (m+1).

The delay reference circuit 11 delays the (m+1) -th delay signal CLK (m+1) by a reference time period T _REF to generate an adjusted first clock signal.

The analog delay circuit 12 delays the (m+1) -th delay signal CLK (m+1) by the adjusted analog delay time period to generate the adjusted second clock signal CLKB.

The phase comparison circuit 13 performs phase comparison on the adjusted first clock signal and the adjusted second clock signal CLKB to generate an adjusted first phase signal. If the adjusted first clock signal lags behind the adjusted second clock signal CLKB, the number of digital delay units connected to the adjusted first phase signal is kept to be (m+1) as shown in fig. 10. The delay distribution circuit 100 outputs the adjusted second clock signal CLKB.

The above embodiments only describe the case that the adjusted first clock signal lags the adjusted second clock signal after one adjustment, and in other embodiments, the adjusted first clock signal lags the adjusted second clock signal after multiple adjustments may be implemented.

The delay distribution circuit preliminarily completes distribution of the total delay time length, not only can ensure that the adjusted analog delay time length is in a preset time length range, but also can ensure that the adjusted analog delay time length is as small as possible, so that when the delay distribution circuit is applied to other circuits, the delay time range of the analog delay circuit to subsequent signals is as large as possible. In addition, the series adjustable digital delay circuit and the analog delay circuit are used for jointly delaying the signals, on one hand, because the delay time of the analog delay circuit to the signals is continuously adjustable, the delay time of the delay phase-locked loop circuit to the signals is also continuously adjustable, and meanwhile, the time jumping caused by the single use of the digital delay circuit to delay the signals is avoided, and the delay precision is further improved; on the other hand, the number of the digital delay units connected in the series adjustable digital delay circuit can be reduced, so that the power consumption is reduced, and the performance of the chip is improved.

As shown in fig. 11, the present application further provides a delay allocation method 1100, which is applied to the delay allocation circuit 100 in any of the above embodiments. The delay allocation method 1100 includes:

In step 1110, the stage-number adjustable digital delay circuit 10 delays the zeroth delay signal CLK0 by a digital delay time length according to the total delay time length to generate an mth delay signal, wherein the digital delay time length is m times of a preset time length, and the preset time length is a time delay of each digital delay unit in the stage-number adjustable digital delay circuit 10 to the received signal.

In step 1120, the digital delay reference circuit 11 delays the mth delay signal by a reference time period T _REF to generate the first clock signal CLKA', wherein the reference time period T _REF is greater than the preset time period.

In step 1130, the analog delay circuit 12 delays the mth delay signal by an analog delay time period T _ANA to generate the second clock signal CLKA, wherein the sum of the digital delay time period and the analog delay time period T _ANA is not greater than the total delay time period T _TOTAL.

In step 1140, the phase comparison circuit 13 performs phase comparison on the first clock signal CLKA 'and the second clock signal CLKA and generates a first phase signal PH'.

In step 1150, the control circuit 14 generates a plurality of control signals S ₁、S₂、......、S_n according to the first phase signal PH' to control whether the number of digital delay units connected in the series adjustable digital delay circuit 10 is changed from m to (m+1), so as to change the analog delay time T _ANA to an adjusted analog delay time and change the preset time of m to a preset time of (m+1);

In step 1160, the analog delay circuit 12 outputs the adjusted second clock signal CLKB when the adjusted analog delay time is within the preset time range.

The delay distribution method not only ensures that the adjusted analog delay time length is within the preset time length range, but also ensures that the adjusted analog delay time length is as small as possible, so that when the delay distribution circuit is applied to other circuits, the delay time range of the analog delay circuit for subsequent signals is as large as possible. In addition, the series adjustable digital delay circuit and the analog delay circuit are used for jointly delaying the signals, on one hand, because the delay time of the analog delay circuit to the signals is continuously adjustable, the delay time of the delay phase-locked loop circuit to the signals is also continuously adjustable, and meanwhile, the time jumping caused by the single use of the digital delay circuit to delay the signals is avoided, and the delay precision is further improved; on the other hand, the number of the digital delay units connected in the series adjustable digital delay circuit can be reduced, so that the power consumption is reduced, and the performance of the chip is improved.

The present application provides a delay locked loop circuit as shown in fig. 12. The delay locked loop circuit comprises at least a delay distribution circuit 100, a fixed delay circuit 18, a second phase comparator 15 and a voltage generation circuit 16.

The fixed delay circuit 18 is configured to delay the reference clock signal clk_ref by a fixed time period T0 and generate a zero-th delay signal CLK0. In one embodiment, the fixed delay circuit 18 includes a resistor and a capacitor. A first terminal of the resistor receives the reference clock signal clk_ref, a second terminal of the resistor is connected to a first terminal of the capacitor to form an output terminal outputting the zeroth delay signal CLK0, and a second terminal of the capacitor is grounded. The reference clock signal clk_ref is capable of charging and discharging a capacitor such that the zero-delay signal CLK0 output by the output terminal lags the reference clock signal clk_ref by a fixed time period T0.

The delay distribution circuit 100 is configured to receive the zeroth delay signal CLK0, delay the zeroth delay signal CLK0 by m times of a preset time length according to a total delay time length T _TOTAL, generate an mth delay signal, delay the mth delay signal by a reference time length T _REF and an analog delay time length T _ANA respectively to generate a first clock signal CLKA 'and a second clock signal CLKA correspondingly, and determine whether to change the analog delay time length T _ANA to an adjusted analog delay time length and change the m times of the preset time length to a preset time length (m+1) according to a phase relation between the first clock signal CLKA' and the second clock signal CLKA; when the adjusted analog delay time is within the preset time range, the delay distribution circuit 100 outputs the adjusted second clock signal CLKB; the sum of the m times of preset time length and the analog time delay time length T _ANA is not larger than the total time delay time length T _TOTAL, the reference time length T _REF is larger than the preset time length, and the adjusted analog time delay time length is the difference value of the analog time delay time length T _ANA minus the preset time length.

A second phase comparator 15 is coupled to the analog delay circuit 12 and is configured to phase compare the adjusted second clock signal CLKB with the reference clock signal clk_ref and generate a first signal PH _H1 and a second signal PH _H2.

In one embodiment, as shown in fig. 13, the second phase comparator 15 includes a flip-flop 151, a flip-flop 153, and an and gate 152. The clock terminal CK of the flip-flop 151 receives the adjusted second clock signal CLKB, the input terminal D of the flip-flop 151 receives the power supply voltage VDD, the clock terminal CK of the flip-flop 153 receives the reference clock signal clk_ref, the input terminal D of the flip-flop 153 receives the power supply voltage VDD, the output terminal Q of the flip-flop 151 is connected to the first input terminal of the and gate 152, the output terminal Q of the flip-flop 153 is connected to the second input terminal of the and gate 152, and the output terminal of the and gate 152 is connected to the RESET terminal R of the flip-flop 151 and the RESET terminal R of the flip-flop 153, respectively, to output the RESET signal RESET3. In this embodiment, the flip-flop 151 and the flip-flop 153 are both triggered by rising edges, and in other embodiments, those skilled in the art may simply replace the circuit to implement the functions of the circuit when the flip-flop 151 and the flip-flop 153 are triggered by falling edges.

Three operation of the second phase comparator 15 will be described below based on the phase relationship between the adjusted second clock signal CLKB and the reference clock signal clk_ref:

Case (1): the adjusted second clock signal CLKB leads the reference clock signal clk_ref

As can be seen from fig. 13 and 14, before time t1, the first signal PH _H1, the second signal PH _H2 and the RESET signal RESET3 are all at low level. At time t1, the rising edge of the adjusted second clock signal CLKB comes first, and the flip-flop 151 is triggered, at this time, the first signal PH _H1 output by the output terminal Q of the flip-flop 151 jumps from low level to high level. Since the flip-flop 153 is not triggered, the second signal PH _H2 output from the output terminal Q of the flip-flop 153 continues to be at the low level. The RESET signal RESET3 also continues to be at a low level. At time t2, the flip-flop 153 is triggered and the second signal PH _H2 transitions from a low level to a high level. At this time, the RESET signal RESET3 transitions from low level to high level, so that both the flip-flop 151 and the flip-flop 153 are RESET, i.e. the first signal PH _H1 and the second signal PH _H2 at time t3 both transition from high level to low level, and the RESET signal RESET3 also transitions to low level. To this end, the first signal PH _H1, the second signal PH _H2, and the RESET signal RESET3 are all at the first level before the next rising edge of the adjusted second clock signal CLKB comes.

Case (2): the adjusted second clock signal CLKB lags behind the reference clock signal clk_ref

As can be seen from fig. 13 and 15, before time t5, the first signal PH _H1, the second signal PH _H2 and the RESET signal RESET3 are all at low level. At time t5, the rising edge of the reference clock signal CLK_REF comes first, the flip-flop 153 is triggered first, and the second signal PH _H2 transitions from low to high. Since the flip-flop 151 is not triggered, the first signal PH _H1 continues to be at a low level. The RESET signal RESET3 also continues to be at a low level. At time t6, the flip-flop 151 is triggered, and the first signal PH _H1 transitions from low to high. At this time, the RESET signal RESET3 transitions from low to high, so that both the flip-flop 151 and the flip-flop 153 are RESET (i.e., both the first signal PH _H1 and the second signal PH _H2 transition from high to low at time t 7), and the RESET signal RESET3 also transitions to low. To this end, the first signal PH _H1, the second signal PH _H2, and the RESET signal RESET3 are all at low level before the next rising edge of the reference clock signal clk_ref comes.

Case (3): the adjusted second clock signal CLKB is synchronized with the reference clock signal CLK_REF

As can be seen from fig. 13 and 16, before time t9, the first signal PH _H1, the second signal PH _H2 and the RESET signal RESET3 are all at low level. At time t9, the rising edge of the reference clock signal clk_ref and the rising edge of the adjusted second clock signal CLKB arrive at the same time, and the flip-flop 151 and the flip-flop 153 are triggered at the same time, i.e., the first signal PH _H1 and the second signal PH _H2 each transition from low to high. The RESET signal RESET3 also transitions from low to high, so that both flip-flop 151 and flip-flop 153 are RESET (i.e., both the first signal PH _H1 and the second signal PH _H2 transition from high to low at time t 10), and the RESET signal RESET3 also transitions to low at time t 10. To this end, the first signal PH _H1, the second signal PH _H2, and the RESET signal RESET3 are at low level before the next rising edge of the adjusted second clock signal CLKB and the reference clock signal clk_ref comes.

The voltage generating circuit 16 is coupled to the second phase comparator 15 and is configured to generate a regulated voltage Vc according to the first signal PH _H1 and the second signal PH _H2 to readjust the adjusted analog delay time duration until the readjusted second clock signal output by the delay distributing circuit 100 is synchronized with the reference clock signal clk_ref.

In one embodiment, as shown in fig. 13, the voltage generating circuit 16 includes a first current source I ₁, a switch S1, a switch S2, a second current source I ₂, a resistor R1 and a capacitor Cp. The first current source I ₁, the switch S1, the switch S2 and the second current source I ₂ are sequentially connected, the other end of the first current source I ₁ is connected to the power supply voltage VDD, the other end of the second current source I ₂ is grounded, the control end of the switch S1 is connected to the output end Q of the trigger 151 to receive the first signal PH _H1, the control end of the switch S2 is connected to the output end Q of the trigger 153 to receive the second signal PH _H2, the switch S1 is connected to the switch S2 to form a connection point N, the first end of the resistor R1 is connected to the connection point N, the second end of the resistor R1 is connected to the first end of the capacitor Cp to generate the regulated voltage Vc, and the second end of the capacitor Cp is grounded. The switch S1 and the switch S2 may be MOS transistors, junction field effect transistors, or the like, as long as they can be turned on/off according to the level. In this embodiment, the switch S1 and the switch S2 are both NMOS transistors.

The operation principle of the voltage generating circuit 16 will be described in three cases:

For case (1): as can be seen from fig. 13 and 14, at time t1 to t2, the switch S1 is turned on and the switch S2 is turned off, and the capacitor Cp is charged with the first constant current, so that the voltage value of the regulated voltage Vc is increased. At time t2 to time t3, both the switch S1 and the switch S2 are turned on, and since this state is an instantaneous state, it can be considered that the capacitor Cp is continuously charged with the first constant current, and the voltage value of the regulated voltage Vc is continuously increased. At the time t 3-t 4, the switch S1 and the switch S2 are both turned off, the capacitor Cp is neither charged nor discharged externally, and the voltage value of the regulated voltage Vc is kept unchanged. In summary, if the adjusted second clock signal CLKB is ahead of the reference clock signal clk_ref, the voltage value of the regulated voltage Vc will increase.

For case (2): referring to fig. 13 and 15, at time t5 to t6, switch S1 is turned off, switch S2 is turned on, and capacitor Cp is discharged with a second constant current, so that the voltage value of regulated voltage Vc is reduced. At time t6 to t7, both the switch S1 and the switch S2 are turned on, and since this state is an instantaneous state, it can be considered that the capacitor Cp continues to discharge with the second constant current, and the voltage value of the regulated voltage Vc continues to decrease. At the time t 7-t 8, the switch S1 and the switch S2 are both turned off, the capacitor Cp is neither charged nor discharged externally, and the voltage value of the regulated voltage Vc is kept unchanged. In summary, if the adjusted second clock signal CLKB lags behind the reference clock signal clk_ref, the voltage value of the regulated voltage Vc will decrease.

For case (3): referring to fig. 13 and 16, at time t9 to t10, switch S1 and switch S2 are simultaneously turned on, and since this state is an instantaneous state, it can be considered that capacitor Cp is neither charged nor discharged externally, and the voltage value of regulation voltage Vc remains unchanged; at time t10 to time t11, both switch S1 and switch S2 are turned off, and it is considered that capacitor Cp is neither charged nor discharged externally, and the voltage value of regulated voltage Vc remains unchanged. In summary, if the adjusted second clock signal CLKB is synchronized with the reference clock signal clk_ref, the voltage value of the regulated voltage Vc will remain unchanged.

As can be seen from fig. 1-2 and fig. 6, the regulated voltage Vc is fed back to the analog delay circuit 12 to adjust the adjusted analog delay time. When the voltage of the regulated voltage Vc increases, the capacitance values of the first MOS capacitor C1 and the second MOS capacitor C2 increase, and thus the time required for charging and discharging the first MOS capacitor C1 and the second MOS capacitor C2 increases, thereby increasing the adjusted analog delay time until the readjusted second clock signal is synchronized with the reference clock signal clk_ref. When the voltage of the regulated voltage Vc decreases, the capacitance values of the first MOS capacitor C1 and the second MOS capacitor C2 decrease, and thus the time required for charging and discharging the first MOS capacitor C1 and the second MOS capacitor C2 decreases, thereby decreasing the adjusted analog delay time until the readjusted second clock signal is synchronized with the reference clock signal clk_ref. When the voltage of the regulated voltage Vc is kept unchanged, the time required for charging and discharging the first MOS capacitor C1 and the second MOS capacitor C2 is kept unchanged, so that the adjusted analog delay time is also kept unchanged, that is, the adjusted second clock signal CLKB is kept synchronous with the reference clock signal clk_ref.

In summary, the working principle of the delay locked loop circuit is as follows:

as can be seen from the operation principle of the delay distribution circuit 100 described above, the delay distribution circuit 100 finally outputs the adjusted second clock signal CLKB, and the adjusted second clock signal CLKB is input to the second phase comparator 15 in fig. 1.

The second phase comparator 15 phase compares the adjusted second clock signal CLKB with the reference clock signal clk_ref and generates a first signal PH _H1 and a second signal PH _H2.

If the timing relationship between the first signal PH _H1 and the second signal PH _H2 is shown in fig. 15, the voltage generating circuit 16 generates the regulated voltage Vc with the voltage decreasing downward according to the first signal PH _H1 and the second signal PH _H2, so as to decrease the adjusted analog delay time to obtain the readjusted analog delay time.

The analog delay circuit 12 delays the (m+1) -th delay signal CLK (m+1) by the readjusted analog delay time length under the control of the regulation voltage Vc whose voltage decreases downward to output the readjusted second clock signal.

The second phase comparator 15 compares the readjusted second clock signal with the reference clock signal CLK REF and generates a new first signal and a new second signal.

If the timing relationship between the new first signal and the new second signal is shown in fig. 16, the voltage generating circuit 16 generates the regulated voltage Vc with the voltage kept unchanged according to the new first signal and the new second signal, so that the analog delay time after readjustment remains unchanged. At this time, the readjusted second clock signal and the reference clock signal clk_ref have already reached synchronization, and the delay locked loop circuit reaches a locked state.

In this embodiment, the operation principle of the delay phase locked loop circuit is described by taking the example that the adjusted second clock signal CLKB lags behind the reference clock signal clk_ref and the adjusted second clock signal and the reference clock signal clk_ref are synchronized after one adjustment. In addition, the adjusted second clock signal CLKB may also be an unadjusted second clock signal CLKA, and the second clock signal after being adjusted again may also be an adjusted second clock signal CLKB.

As shown in fig. 17, the present application further provides a delay locked loop circuit applied to any one of the above embodiments. The delay lock method 1700 includes:

In step 1710, the delay distribution circuit 100 receives the zeroth delay signal CLK0, delays the zeroth delay signal CLK0 by a preset time length m times according to the total delay time length T _TOTAL and generates an mth delay signal, delays the mth delay signal by a reference time length T _REF and an analog delay time length T _ANA to generate a first clock signal CLKA 'and a second clock signal CLKA respectively, and determines whether to change the analog delay time length T _ANA to an adjusted analog delay time length and to change the preset time length m times to a preset time length (m+1) times according to a phase relation between the first clock signal CLKA' and the second clock signal CLKA, wherein a sum of the preset time length m times and the analog delay time length T _ANA is not greater than the total delay time length T _TOTAL, the reference time length T _REF is greater than the preset time length, and the adjusted analog delay time length is a difference of subtracting the preset time length T _ANA.

At step 1720, the delay distribution circuit 100 outputs the adjusted second clock signal CLKB when the adjusted analog delay duration is within the preset duration range.

In step 1730, the second phase comparator 15 receives the adjusted second clock signal CLKB and the reference clock signal clk_ref, performs phase comparison on the reference clock signal clk_ref and the adjusted second clock signal CLKB, and generates the first signal PH _H1 and the second signal PH _H2.

In step 1740, the voltage generating circuit 16 generates the regulated voltage Vc according to the first signal PH _H1 and the second signal PH _H2 to readjust the adjusted analog delay time duration until the readjusted second clock signal output by the delay allocating circuit 100 is synchronized with the reference clock signal clk_ref.

The delay phase-locked loop circuit and the delay phase-locked method initially adjust the analog delay time length and m times of preset time length so that the adjusted analog delay time length is as small as possible within the range of the preset time length, and then further finely adjust the adjusted analog delay time length by using the regulating voltage. The method can reduce the frequency of phase comparison of the adjusted second clock signal and the reference clock signal, thereby realizing quick locking of the delay phase-locked loop circuit. In addition, the series adjustable digital delay circuit and the analog delay circuit are used for jointly delaying the signals, on one hand, because the delay time of the analog delay circuit to the signals is continuously adjustable, the delay time of the delay phase-locked loop circuit to the signals is also continuously adjustable, and meanwhile, the time jumping caused by the single use of the digital delay circuit to delay the signals is avoided, and the delay precision is further improved; on the other hand, the number of the digital delay units connected in the series adjustable digital delay circuit can be reduced, so that the power consumption is reduced, and the performance of the chip is improved.

The foregoing detailed description and drawings are merely typical examples of the invention. It will be evident that various additions, modifications and substitutions may be made therein without departing from the spirit and scope of the invention as defined in the accompanying claims. It will be appreciated by those of skill in the art that the invention can be varied in form, construction, arrangement, proportions, materials, elements, components and otherwise, used in the practice of the invention, which are particularly adapted to specific environments and operative requirements without departing from the principles of the present invention. Accordingly, the embodiments disclosed herein are meant to be illustrative only and not limiting as to the scope of the invention which is to be given the full breadth of the appended claims and any and all legal equivalents thereof.

Claims

1. A delay locked loop circuit, the delay locked loop circuit comprising at least:

The delay distribution circuit is configured to receive a zeroth delay signal, delay the zeroth delay signal by m times of preset time length according to total delay time length and generate an mth delay signal, delay reference time length and analog delay time length for the mth delay signal respectively to correspondingly generate a first clock signal and a second clock signal, determine whether to change the analog delay time length into an adjusted analog delay time length and change the m times of preset time length into (m+1) times of preset time length according to the phase relation between the first clock signal and the second clock signal, and output the adjusted second clock signal when the adjusted analog delay time length is in the preset time length range; wherein the sum of the m times of preset time length and the analog time delay time length is not greater than the total time delay time length, the reference time length is greater than the preset time length, and the adjusted analog time delay time length is the difference value of the analog time delay time length minus the preset time length;

A second phase comparator coupled to the delay distribution circuit and configured to receive the adjusted second clock signal and a reference clock signal, to phase compare the adjusted second clock signal and the reference clock signal and to generate a first signal and a second signal; and

And the voltage generation circuit is coupled with the second phase comparator and is configured to generate a regulating voltage according to the first signal and the second signal so as to readjust the adjusted analog delay time length until the readjusted second clock signal output by the delay distribution circuit is synchronous with the reference clock signal.

2. The delay locked loop circuit of claim 1, wherein the m times the preset duration is increased when the first clock signal is advanced or synchronized with the second clock signal, thereby reducing the analog delay duration; when the first clock signal lags behind the second clock signal, the m times of preset duration is kept unchanged, so that the analog delay duration is kept unchanged.

3. The delay locked loop circuit of claim 1, wherein the delay distribution circuit comprises:

The series adjustable digital delay circuit is configured to receive the zeroth delay signal and delay the zeroth delay signal by m times of preset time length to generate the mth delay signal, wherein the preset time length is the time delayed by each digital delay unit in the series adjustable digital delay circuit to the received signal;

A delay reference circuit coupled to the series adjustable digital delay circuit and configured to delay the mth delay signal by the reference time period to generate the first clock signal; and

And the analog delay circuit is coupled with the series adjustable digital delay circuit and is configured to receive the mth delay signal, delay the analog delay time length for the mth delay signal to generate the second clock signal, and further adjust the adjusted analog delay time length again according to the regulation voltage.

4. A delay locked loop circuit as claimed in claim 3, wherein said delay distribution circuit further comprises:

A phase comparison circuit coupled to the delay reference circuit and the analog delay circuit, respectively, configured to phase compare the first clock signal and the second clock signal to generate a first phase signal; and

And the control circuit is coupled between the phase comparison circuit and the series adjustable digital delay circuit and is configured to generate a plurality of control signals according to the first phase signal, wherein the plurality of control signals control whether the number of digital delay units connected in the series adjustable digital delay circuit is changed from m to (m+1) or not so as to change the analog delay time length into the adjusted analog delay time length and change the m-time preset time length into the (m+1) -time preset time length, and further enable the analog delay circuit to output the adjusted second clock signal.

5. The delay locked loop circuit of claim 4 wherein when the first phase signal indicates that the first clock signal is advanced or synchronized with the second clock signal, an mth control signal of the plurality of control signals transitions from a second level to a first level, an (m+1) th control signal of the plurality of control signals transitions from the first level to the second level, and the other control signals continue to maintain the first level, thereby changing the number of digital delay cells accessed in the series adjustable digital delay circuit from m to (m+1); when the first phase signal indicates that the first clock signal lags behind the second clock signal, the mth control signal in the plurality of control signals keeps keeping the second level, and other control signals keep keeping the first level, so that the number of digital delay units connected in the series adjustable digital delay circuit is still m.

6. The delay locked loop circuit of claim 4 wherein when the number of digital delay units connected in the series adjustable digital delay circuit changes from m to (m+1), the series adjustable digital delay circuit delays the zeroth delay signal by a predetermined time length (m+1) and generates a (m+1) th delay signal, the analog delay circuit delays the (m+1) th delay signal by the adjusted analog delay time length and generates the adjusted second clock signal, the delay reference circuit delays the (m+1) th delay signal by the reference time length and generates an adjusted first clock signal, the phase comparison circuit phase compares the adjusted first clock signal with the adjusted second clock signal and generates an adjusted first phase signal, wherein when the adjusted first phase signal indicates that the adjusted first clock signal lags the adjusted second clock signal, the phase comparison circuit outputs the adjusted second clock signal.

7. The delay locked loop circuit of claim 4 wherein the series adjustable digital delay circuit comprises a plurality of digital delay units and a plurality of switch circuits correspondingly arranged and connected in sequence, wherein each digital delay unit is correspondingly connected with one switch circuit, an mth switch circuit in the plurality of switch circuits is controlled to be conducted by an mth control signal in the plurality of control signals, and other switch circuits except the mth control signal are controlled to be disconnected by other control signals except the mth switch circuit, so that the mth digital delay unit delays the zeroth delay signal to generate the mth delay signal, and the mth delay signal is output to the analog delay circuit and the delay reference circuit respectively.

8. The delay locked loop circuit of claim 4 wherein the phase comparison circuit comprises a first phase comparator and a reset circuit; wherein the first phase comparator is coupled to the delay reference circuit and the analog delay circuit, respectively, and the reset circuit is coupled to the first phase comparator; the first phase comparator is configured to control the first phase signal to perform a first level shift according to a phase relationship between the first clock signal and the second clock signal, and the reset circuit is configured to generate a reset signal according to the first phase signal and the second clock signal to control the first phase signal to perform a second level shift.

9. The delay locked loop circuit of claim 8 wherein said first phase signal transitions from a first level to a second level when a first rising edge of said first clock signal arrives and said reset signal transitions from a first level to a second level when a first rising edge of said second clock signal arrives under a condition that said first clock signal is either ahead of or synchronous with said second clock signal, thereby controlling said first phase signal to transition from a second level to a first level; the first phase signal and the reset signal are both always at a first level, provided that the first clock signal lags the second clock signal.

10. The delay locked loop circuit of claim 8 wherein the first phase comparator comprises a first flip-flop, a first not gate, a second not gate, a first nor gate, a second flip-flop, a third not gate, a fourth not gate, and a second nor gate, wherein an input of the first not gate receives the second clock signal, an output of the first not gate is connected to an input of the first flip-flop, a clock of the first flip-flop receives the first clock signal, an output of the first flip-flop is connected to the reset circuit to output the first phase signal to the reset circuit, a first input of the second nor gate is connected to an output of the first flip-flop, a second input of the second nor gate is connected to the reset circuit to receive the reset signal generated by the reset circuit, an output of the second nor gate is connected to an input of the fourth not gate, an output of the fourth not gate is connected to an input of the first flip-flop, a second input of the second nor gate is connected to the second input of the second not gate, a second input of the second nor gate is connected to the second input of the second nor gate, a second input of the reset circuit is connected to the second input of the second nor gate, the second input of the second nor gate is connected to the second input of the second nor gate.

11. The delay locked loop circuit of claim 8 wherein the reset circuit comprises a plurality of flip-flops, a third nor gate and a fifth nor gate connected in sequence, wherein an input of a first flip-flop receives the first phase signal, a clock of each flip-flop receives the second clock signal, an output of a last flip-flop is connected to a reset of each flip-flop, an output of each flip-flop is connected to an input of the third nor gate, an output of the third nor gate is connected to the fifth nor gate, the fifth nor gate outputs the reset signal, and the plurality of flip-flops are sequentially triggered according to a plurality of edges of the second clock signal.

12. The delay locked loop circuit of claim 4 wherein the control circuit comprises a plurality of control units, each control unit having the same configuration, an mth control unit of the plurality of control units comprising a nand gate, a nor gate and a flip-flop, wherein the nand gate receives the first phase signal and the (m-1) th control signal, an output of the nand gate is connected to an input of the nor gate, an output of the not gate is connected to a clock of the flip-flop, a supply voltage is connected to an input of the flip-flop, an output of the flip-flop is connected to the mth switching circuit to output the mth control signal to the mth switching circuit, and a reset of the flip-flop is connected to an output of the (m+1) th control unit to receive the (m+1) th control signal.

13. The delay locked loop circuit of claim 1 wherein a voltage value of the regulated voltage increases to increase the adjusted analog delay time period when the adjusted second clock signal leads the reference clock signal; when the adjusted second clock signal lags behind the reference clock signal, the voltage value of the regulating voltage is reduced so as to reduce the adjusted analog delay time; and when the adjusted second clock signal is synchronous with the reference clock signal, the voltage value of the regulating voltage is kept unchanged, so that the adjusted analog delay time length is kept unchanged.

14. A delay locked method applied to the delay locked loop circuit of any one of claims 1-13, the delay locked method comprising:

The delay distribution circuit receives a zeroth delay signal, delays the zeroth delay signal by m times of preset time length according to total delay time length and generates an mth delay signal, delays the mth delay signal by reference time length and analog delay time length respectively to correspondingly generate a first clock signal and a second clock signal, and determines whether to change the analog delay time length into the adjusted analog delay time length and change the m times of preset time length into (m+1) times of preset time length according to the phase relation between the first clock signal and the second clock signal; wherein the sum of the m times of preset time length and the analog time delay time length is not greater than the total time delay time length, the reference time length is greater than the preset time length, and the adjusted analog time delay time length is the difference value of the analog time delay time length minus the preset time length;

When the adjusted analog delay time length is within the preset time length range, the delay distribution circuit outputs an adjusted second clock signal;

The second phase comparator receives the adjusted second clock signal and a reference clock signal, performs phase comparison on the reference clock signal and the adjusted second clock signal, and generates a first signal and a second signal;

The voltage generation circuit generates a regulating voltage according to the first signal and the second signal to readjust the adjusted analog delay time length until the readjusted second clock signal output by the delay distribution circuit is synchronous with the reference clock signal.