CN118366531A

CN118366531A - SPI NAND FLASH chip performance test method and SPI NAND FLASH chip performance test device

Info

Publication number: CN118366531A
Application number: CN202410460369.4A
Authority: CN
Inventors: 徐培根
Original assignee: Guangzhou V Solution Telecommunication Technology Co ltd
Current assignee: Guangzhou V Solution Telecommunication Technology Co ltd
Priority date: 2024-04-17
Filing date: 2024-04-17
Publication date: 2024-07-19

Abstract

The invention discloses a SPI NAND FLASH chip performance test method and a SPI NAND FLASH chip performance test device, wherein the method comprises the following steps: a complex programmable logic device is used for controlling a level conversion module to generate a plurality of signals to be tested aiming at a chip to be tested, wherein the signals to be tested comprise an access area, test voltage and test frequency when the chip to be tested is subjected to read/write operation, and the chip to be tested is SPI NAND FLASH chips; performing read/write operation on the chip to be tested by using the signals to be tested; and verifying the correctness of the read/write operation result. The invention can realize the test of simulating more use scenes in a short time so as to rapidly verify various limit performances of SPI NAND FLASH chips and whether the chips accord with the use of products, thereby greatly improving the test efficiency.

Description

SPI NAND FLASH chip performance test method and SPI NAND FLASH chip performance test device

Technical Field

The invention relates to the technical field of performance test, in particular to a SPI NAND FLASH chip performance test method and device.

Background

SPI NAND FLASH is a memory device that combines SPI (SERIAL PERIPHERAL INTERFACE ) bus AND NAND FLASH (Not AND Flash, nand Flash) memory. The SPI Flash memory has the advantages of high capacity and low cost of NAND FLASH memories, and low power consumption and high speed of the SPI Flash memories, and is widely used as data storage, operating system storage, firmware storage and the like in a plurality of fields including embedded systems, mobile devices and the like.

Since SPI NAND FLASH chips have a large capacity, there are a number of problems such as bad blocks and main chip adaptation, and thus strict testing of the chips is required before SPI NAND FLASH chips are selected and used. In recent years, the development trend of SPI NAND FLASH chips is accelerated, manufacturers for producing Flash chips are rapidly emerging, and the chips can be selected more, and the quality of the chips is uneven, so that the workload of testing the chips is very large, and if the test is insufficient, the problem is easily exposed in mass production or engineering, thereby influencing the quality of products.

However, there is no testing tool related to SPI NAND FLASH chips in the current market, so the product test can only replace different chips into the product to perform the whole software reading test, and the test work is complicated and complicated; moreover, all available chip information can only be derived from the specifications of the chip manufacturer, however, there are some minor usage differences in suitability that may not be found by the chip manufacturer. Therefore, there is a need for a technical solution that can rapidly test SPI NAND FLASH the ultimate performance of a chip in various states to determine whether the product replacement is satisfied.

Disclosure of Invention

In order to overcome the problems in the related art, the invention provides a SPI NAND FLASH chip performance testing method and device, which are used for solving the defects in the related art.

According to a first aspect of the present invention, there is provided a SPI NAND FLASH chip performance test method, which is characterized in that the method includes:

A complex programmable logic device is used for controlling a level conversion module to generate a plurality of signals to be tested aiming at a chip to be tested, wherein the signals to be tested comprise an access area, test voltage and test frequency when the chip to be tested is subjected to read/write operation, and the chip to be tested is SPI NAND FLASH chips;

performing read/write operation on the chip to be tested by using the signals to be tested;

And verifying the correctness of the read/write operation result.

Preferably, the chip to be tested comprises a plurality of blocks, and each block comprises a plurality of pages; the access areas of the signals to be tested are designated pages sequentially selected from all blocks in the chip to be tested according to a designated rule, the test voltage is the standard voltage of the chip to be tested, and the test frequency is the standard clock frequency of the chip to be tested.

Preferably, the chip to be tested comprises N blocks, each block comprising M pages, each page being divided into s sectors; the appointed rule is that the selected accessed area in the nth block is the ith sector of the mth page, wherein N is more than or equal to 1 and less than or equal to N, M is the remainder of dividing N by M and M is m=M when dividing N, i is the remainder of dividing M by s and i=s when dividing s by M.

Preferably, the access areas of the signals to be tested are a plurality of designated blocks of the chip to be tested, the test voltage is a standard voltage of the chip to be tested, and the test frequency is a standard clock frequency of the chip to be tested;

the performing read/write operation on the chip to be tested by using the signals to be tested includes:

and performing a specified number of read/write operations on a specified number of blocks of the chip to be tested by using the signals to be tested.

Preferably, the access areas of the signals to be tested are sequentially selected blocks in the chip to be tested, the test voltage is a standard voltage of the chip to be tested, and the test frequency is sequentially selected from a designated frequency interval according to a designated frequency interval; the specified frequency interval comprises the standard clock frequency of the chip to be tested.

Preferably, the standard clock frequency of the chip to be tested is 50MHz, the specified frequency interval is 20MHz-100MHz, and the specified frequency interval is 5MHz.

Preferably, the access areas of the signals to be tested are sequentially selected blocks in the chip to be tested, the test frequency is the standard clock frequency of the chip to be tested, and the test voltage is sequentially selected voltages according to the specified voltage interval from the specified voltage interval; the specified voltage interval comprises standard voltage of the chip to be tested.

Preferably, the standard voltage of the chip to be tested is 3.3V, the specified voltage interval is 2.7V-3.6V, and the specified voltage interval is 0.1V.

According to a second aspect of the present invention, there is provided SPI NAND FLASH chip performance test apparatus, the apparatus comprising a complex programmable logic device and a level shifting module; wherein,

The complex programmable logic device is used for controlling the level conversion module to generate a plurality of signals to be tested aiming at the chip to be tested so as to realize the SPI NAND FLASH chip performance test method according to any embodiment of the invention;

the level conversion module is used for generating the signals to be tested so as to perform read/write operation on the chip to be tested.

Preferably, the complex programmable logic device comprises a level control module, a clock control module, a data reading module and a data writing module; wherein,

The level control module is used for controlling the level conversion module to generate a plurality of signals to be detected;

The clock control module is used for generating a clock when accessing the chip to be tested so as to control the test frequency of the signals to be tested;

The data reading module is used for reading the data returned by the chip to be tested so as to read the chip to be tested;

The data writing module is used for writing data into the chip to be tested so as to perform writing operation on the chip to be tested.

The invention discloses a SPI NAND FLASH chip performance test method and a SPI NAND FLASH chip performance test device, which can simulate a main control chip by using a complex programmable logic device to perform read/write operation access to a SPI NAND FLASH chip, and can realize the test of simulating more use scenes in a shorter time by controlling an access area, test voltage and test frequency so as to rapidly verify various limit performances of a SPI NAND FLASH chip and whether the chip accords with product use, thereby greatly improving test efficiency.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention as claimed.

Drawings

FIG. 1 is a flow chart illustrating a SPI NAND FLASH chip performance test method according to one embodiment of the present invention.

Fig. 2 is a schematic diagram of a chip under test according to an embodiment of the invention.

Fig. 3 is a schematic structural diagram of a SPI NAND FLASH chip performance testing apparatus according to an embodiment of the present invention.

Detailed Description

Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples do not represent all implementations consistent with the invention. Rather, they are merely examples of apparatus and methods consistent with aspects of the invention as detailed in the accompanying claims.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in this specification and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any or all possible combinations of one or more of the associated listed items.

It should be understood that although the terms first, second, third, etc. may be used herein to describe various information, these information should not be limited by these terms. These terms are only used to distinguish one type of information from another. For example, first information may also be referred to as second information, and similarly, second information may also be referred to as first information, without departing from the scope of the invention. The word "if" as used herein may be interpreted as "at … …" or "at … …" or "in response to a determination" depending on the context.

The invention is described in detail below with reference to the drawings and the detailed description.

Referring to fig. 1, fig. 1 is a flowchart of a SPI NAND FLASH chip performance test method according to an embodiment of the present invention, including the following steps:

Step S101, a complex programmable logic device is used for controlling a level conversion module to generate a plurality of signals to be tested aiming at a chip to be tested, wherein the signals to be tested comprise an access area, test voltage and test frequency when the chip to be tested is subjected to read/write operation, and the chip to be tested is SPI NAND FLASH chips;

step S102, using a plurality of signals to be tested to perform read/write operation on the chip to be tested;

Step S103, verifying the correctness of the read/write operation result.

Specifically, the complex programmable logic device (Complex Programming Logic Device, CPLD) refers to a high-density, high-speed, and low-power-consumption programmable logic device, which is formed by the functions of programmable logic around a programmable interconnection matrix, and interconnects between logic units are implemented by metal lines of a fixed length, and the number and functions of I/O control modules are increased. The basic structure of a CPLD can be seen as consisting of a programmable logic array (Logic Array Block, LAB), programmable I/O control modules, and programmable interconnects (Programmable Interconnect Array, PIA).

Specifically, the chip to be tested in the invention can be SPI NAND FLASH chips with any specification, the chip to be tested can comprise a plurality of blocks (blocks), each Block can comprise a plurality of pages (pages), and the CPLD can access any specified Block in the chip to be tested or any specified Page in any specified Block through the signal to be tested of the specified access area.

Specifically, as shown in fig. 2, fig. 2 shows an architecture diagram of a chip under test according to the present invention, and in some embodiments, the chip under test used in the present invention includes 1024 blocks (blocks), and each Block includes 64 pages (pages). Specifically, in other embodiments, the number of blocks and pages included in the chip to be tested may be other specifications, which may be specifically set according to actual requirements, which is not limited by the present invention.

Specifically, in step S101, the CPLD-simulated main control chip may control the level conversion module to generate an access area, a test voltage, and a plurality of signals to be tested for the chip to be tested with different test frequencies, so as to perform multidimensional read/write operation access on the chip to be tested SPI NAND FLASH, so as to implement a test for simulating more usage scenarios in a shorter time, and to rapidly verify whether the SPI NAND FLASH chip meets product usage.

Specifically, in some embodiments, the chip to be tested comprises a plurality of blocks, and each block comprises a plurality of pages; the access areas of the generated plurality of signals to be tested can be set as designated pages sequentially selected from each block in the chip to be tested according to a designated rule, the test voltage is set as the standard voltage of the chip to be tested, and the test frequency is set as the standard clock frequency of the chip to be tested. That is, when testing is performed, a sampling mode may be adopted for the access area, different page positions may be accessed for each block, and meanwhile, standard voltages and frequencies may be maintained to verify whether a large number of read/write operations are performed at each position of the chip is normal.

Specifically, in the present invention, the standard voltage of the chip to be tested may be determined according to the specific specification of the chip, for example, the standard voltage of some chips to be tested may be 3.3V, and the standard voltage of some chips to be tested may also be other values.

In the present invention, the standard clock frequency of the chip to be tested may be determined according to the specific specification of the chip, for example, the standard clock frequency of some chips to be tested may be 50MHz, and the standard clock frequency of some chips to be tested may be other values.

Specifically, in the above test mode, the specified rule of selecting the pages to be accessed in each Block may be to make a margin for the number of pages contained in the Block according to the sequence number of the current Block, for example, when one Block includes 64 pages, page1 may be selected in Block1 and Block65, page2 may be selected in Block2 and Block66, and so on, so as to ensure that after all blocks have been accessed, each Page position is accessed at least in one Block, so as to avoid missing the case that the chip to be tested fails in the specific Page position area, and to give consideration to full access to all areas of the test chip as long as possible while reducing the test time.

Specifically, in some embodiments, each page of the chip to be tested may be further divided into a plurality of sectors (sectors), and the signal to be tested may access only a certain Sector of the page, instead of accessing the entire page, and after selecting the page of the access area, one designated Sector of the page may be further selected for access according to a designated rule, so as to further reduce the test actual execution time.

Specifically, in some embodiments, if the chip under test includes N blocks, each block includes M pages, and each page is divided into s sectors (sectors); the specification rule for selecting the access area may be that the selected access area in the nth block is the ith sector of the mth page, where 1N, M is the remainder of dividing N by M and M divides N by M m=m, i is the remainder of dividing M by s and s divides M by i=s. By accessing each block only accessing a specific sector of a specific page in the block, the actual execution time of the test can be further reduced to 1/(M x s).

For example, when the chip to be tested includes 1024 blocks, each Block includes 64 pages, and each Page includes 4 sectors, according to the above specified rule, sector1 in Page1 may be selected to access, sector2 in Page2 may be selected to access, sector4 in Page4 may be selected to access, sector1 in Page5 may be selected to access, sector4 in Page64 may be selected to access, sector1 in Page64 may be selected to access in Block65, and so on, and finally the actual execution time of the whole test occupies only 1/256 of the read time of the whole chip to be tested.

Specifically, when the access is performed by sampling in the above manner, different locations may be used to access different sectors, for example, the sampling manner may be: accessing the Sector (remainder of M/4) in Page (remainder of N/64) in BlockN with the corresponding M/4 location in (0 x0,0x5,0xA,0 xF); the method specifically comprises the following steps: for Sector1 under Page1 of Block1, use 0x0 access; for Sector2 under Page2 of Block2, use 0x5 access. Finally, by adopting the sampling mode, whether a large number of read/write operations are normal at all positions in the chip to be tested can be verified, and the actual execution time only occupies 1/256 of the whole chip reading time.

Specifically, in some embodiments, the pages to be accessed may be selected in each block according to other specified rules, which may be specifically set according to actual requirements, which is not limited by the present invention.

Specifically, in addition to the extreme case of accessing a large number of locations in a chip to be tested, there are cases where multiple accesses are made to multiple locations in the chip.

Specifically, in step S101, the access areas of the plurality of signals to be tested may be set as a plurality of designated blocks of the chip to be tested, and the test voltage is set as the standard voltage of the chip to be tested, and the test frequency is set as the standard clock frequency of the chip to be tested; in step S102, when the generated signals to be tested are used to perform the read/write operation on the chip to be tested, the method may include: and performing a specified number of read/write operations on a specified number of blocks of the chip to be tested using the signals to be tested. The specified blocks may be a plurality of blocks uniformly distributed and selected from the chip to be tested, for example, in some embodiments, block1, block512 and Block1024 may be selected from the chip to be tested containing 1024 blocks as a plurality of specified blocks with fixed access. In particular, in other embodiments, other numbers of other blocks may be chosen as the specified blocks for fixed access, as the invention is not limited in this regard. Specifically, the specified number may be a number of orders of magnitude that is relatively large and reasonable, such as 10 tens of thousands or other numbers, to test the performance of the chip under test in extreme cases where read/write accesses are frequent. Specifically, in an example, a standard voltage of 3.3V and a normal clock of 50MHz may be used, and a read/write operation is performed on a fixed Block1, a fixed Block512, and a fixed Block1024 to check whether the chip to be tested can perform the read/write operation for 10 ten thousand times, and the time for the whole read/write operation test is only 3/1024 of the read/write time of the whole chip.

Specifically, the performance of the chip to be tested under different voltage conditions and different frequency conditions is also of great significance in addition to the performance of the chip to be tested under different access positions and different access times.

Specifically, in step S101, the access areas of the signals to be tested may be set as sequentially selected blocks in the chip to be tested, the test voltage is set as the standard voltage of the chip to be tested, and the test frequency is set as sequentially selected frequencies from the specified frequency interval at the specified frequency interval; the specified frequency interval may include a standard clock frequency of the chip to be tested.

Specifically, in some embodiments, if the standard clock frequency of the chip to be tested is 50MHz, the specified frequency interval may be 20MHz-100MHz, and the specified frequency interval may be 5MHz. The standard voltage of 3.3V can be adopted, the clock sequentially adopts different frequencies to respectively read/write according to 20MHz-100MHz and one gear per 5MHz by taking Block as a unit. If Block0 adopts 20MHz to verify the correctness of read/write, block1 adopts 25MHz to verify the correctness of read/write.

Specifically, in step S101, the access areas of the signals to be tested may be set as sequentially selected blocks in the chip to be tested, the test frequency is set as the standard clock frequency of the chip to be tested, and the test voltage is set as sequentially selected voltages in the specified voltage interval according to the specified voltage interval; the specified voltage interval may include a standard voltage of the chip to be tested.

Specifically, in some embodiments, if the standard voltage of the chip to be tested is 3.3V, the specified voltage interval may be 2.7V-3.6V, and the specified voltage interval may be 0.1V. The normal clock 50MHz can be adopted, the control level is 2.7V-3.6V, the CPLD performs read/write operation on the whole chip by controlling the level conversion module according to the interval of 0.1V and taking Block as a unit, so as to verify the correctness of the read/write of the chip under different voltages. If Block0 adopts 2.7V to verify the correctness of the read/write, block1 adopts 2.8V to verify the correctness of the read/write.

In summary, according to the SPI NAND FLASH chip performance test method disclosed by the invention, the main control chip is simulated by using the complex programmable logic device, the SPI NAND FLASH chip is accessed in a read/write operation, and the access area, the test voltage and the test frequency are controlled, so that the test of simulating more use scenes in a shorter time can be realized, various limit performances of the SPI NAND FLASH chip can be rapidly verified, whether the chip meets the use of products or not, and the test efficiency is greatly improved.

Compared with a normal burner, about 30s is needed for reading and writing a complete chip, and more than one month is needed for 10 ten thousand times of operation. The invention can realize various limit tests in a short time by controlling the clock and the access area, realize the access of SPI NAND FLASH chips in various environments by controlling the signal driving capability and the current level, and finally complete a large number of read-write experiments of various scenes in 1 day, thereby saving a large number of test time and realizing more complete tests.

Corresponding to the SPI NAND FLASH chip performance test method embodiment, the invention also provides a SPI NAND FLASH chip performance test device.

Referring to fig. 3, fig. 3 is a schematic structural diagram of a SPI NAND FLASH chip performance test device according to one embodiment of the present invention, where the device includes a Complex Programmable Logic Device (CPLD) 310 and a level shifter 320; wherein,

The complex programmable logic device 310 is used for controlling the level conversion module 320 to generate a plurality of signals to be tested for the chip to be tested 330, so as to implement the SPI NAND FLASH chip performance test method according to any embodiment of the present invention;

The level conversion module 320 is configured to generate a plurality of signals to be tested to perform a read/write operation on the chip 330 to be tested.

Specifically, the complex programmable logic device 310 may be a CPLD device of any specification that can simulate a master control, and the level conversion module 320 may be any level conversion circuit that can be used to control the level and current of the CPLD to SPI NAND FLASH chip signals.

Specifically, in some embodiments, complex programmable logic device 310 may include a level control module 311, a clock control module 312, a data read module 313, and a data write module 314; wherein,

The level control module 311 is configured to control the level conversion module 320 to generate the plurality of signals to be tested;

The clock control module 312 is configured to generate a clock when accessing the chip 330 to be tested, so as to control the test frequencies of the signals to be tested;

The data reading module 313 is configured to read data returned by the chip 330 to be tested, so as to perform a reading operation on the chip 330 to be tested;

The data writing module 324 is configured to write data to the chip 330 to be tested, so as to perform a writing operation on the chip 330 to be tested.

Specifically, the data reading module 313 may be responsible for receiving the data returned by the chip 330 under test through a clock/chip select/RX on the CPLD device; the data writing module 314 is responsible for writing data into the chip 330 to be tested through clock/chip select/TX on the CPLD device; the clock control module 312 is responsible for generating various clocks required for access; the level control module 311 is responsible for controlling the level conversion module 320 to provide level control of the signal to be tested to the signal of the chip 330 to be tested, so as to realize the test under different levels.

Specifically, the implementation process of the functions and roles of each module in the above device is specifically shown in the implementation process of the corresponding steps in the above method, and will not be described herein again.

For the device embodiments, reference is made to the description of the method embodiments for the relevant points, since they essentially correspond to the method embodiments. The apparatus embodiments described above are merely illustrative, wherein the modules illustrated as separate components may or may not be physically separate, and the components shown as modules may or may not be physical, i.e., may be located in one place, or may be distributed over a plurality of network modules. Some or all of the modules may be selected according to actual needs to achieve the purposes of the present invention. Those of ordinary skill in the art will understand and implement the present invention without undue burden.

The embodiments of the present invention are described in a progressive manner, and the same and similar parts of the embodiments are all referred to each other, and each embodiment is mainly described in the differences from the other embodiments. In particular, for the device embodiments, since they are substantially similar to the method embodiments, the description is relatively simple, and reference is made to the description of the method embodiments for relevant points. The apparatus embodiments described above are merely illustrative, wherein the modules illustrated as separate components may or may not be physically separate, and the functions of the modules may be implemented in the same piece or pieces of software and/or hardware when implementing the aspects of the present invention. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment. Those of ordinary skill in the art will understand and implement the present invention without undue burden.

It is to be understood that the above examples of the present invention are provided by way of illustration only and not by way of limitation of the embodiments of the present invention. Any modification, equivalent replacement, improvement, etc. which come within the spirit and principles of the invention are desired to be protected by the following claims.

Claims

1. A SPI NAND FLASH chip performance test method, the method comprising:

And verifying the correctness of the read/write operation result.

2. The method of claim 1, wherein the chip to be tested comprises a plurality of blocks, each block comprising a plurality of pages; the access areas of the signals to be tested are designated pages sequentially selected from all blocks in the chip to be tested according to a designated rule, the test voltage is the standard voltage of the chip to be tested, and the test frequency is the standard clock frequency of the chip to be tested.

3. The method of claim 2, wherein the chip to be tested comprises N blocks, each block comprising M pages, each page divided into s sectors; the appointed rule is that the selected accessed area in the nth block is the ith sector of the mth page, wherein N is more than or equal to 1 and less than or equal to N, M is the remainder of dividing N by M and M is m=M when dividing N, i is the remainder of dividing M by s and i=s when dividing s by M.

4. The method of claim 1, wherein the access areas of the plurality of signals to be tested are a plurality of designated blocks of the chip to be tested, the test voltage is a standard voltage of the chip to be tested, and the test frequency is a standard clock frequency of the chip to be tested;

5. The method of claim 1, wherein the access areas of the plurality of signals to be tested are sequentially selected blocks in the chip to be tested, the test voltage is a standard voltage of the chip to be tested, and the test frequency is sequentially selected frequencies from a specified frequency interval at specified frequency intervals; the specified frequency interval comprises the standard clock frequency of the chip to be tested.

6. The method of claim 5, wherein the standard clock frequency of the chip to be tested is 50MHz, the specified frequency interval is 20MHz-100MHz, and the specified frequency interval is 5MHz.

7. The method of claim 1, wherein the access areas of the plurality of signals to be tested are sequentially selected blocks in the chip to be tested, the test frequency is a standard clock frequency of the chip to be tested, and the test voltage is sequentially selected voltages from a specified voltage interval at specified voltage intervals; the specified voltage interval comprises standard voltage of the chip to be tested.

8. The method of claim 7, wherein the standard voltage of the chip to be tested is 3.3V, the specified voltage interval is 2.7V-3.6V, and the specified voltage interval is 0.1V.

9. A SPI NAND FLASH chip performance testing device, which is characterized by comprising a complex programmable logic device and a level conversion module; wherein,

The complex programmable logic device is used for controlling the level conversion module to generate a plurality of signals to be tested aiming at the chip to be tested so as to realize the SPI NAND FLASH chip performance test method according to any one of claims 1-8;

10. The apparatus of claim 9, wherein the complex programmable logic device comprises a level control module, a clock control module, a data reading module, and a data writing module; wherein,