CN118366410A - Driving circuit, driving method thereof and display device - Google Patents

Abstract

The present application belongs to the field of optoelectronic technology, and provides a driving circuit and a driving method thereof, and a display device. The driving circuit includes a timing controller, a source driver, and a plurality of data lines, wherein the source driver is electrically connected to the timing controller and the plurality of data lines respectively, and each data line is also electrically connected to a column of sub-pixels; the timing controller is configured to calculate the influence factor and value of each sub-pixel in a row on a target sub-pixel, and uses the sum of the influence factor and value and the original data signal as an output data signal, and provides the output data signal to the source driver; the source driver is configured to receive the output data signal and convert it into an analog voltage, and provide the analog voltage to the data line; the data line is configured to receive the analog voltage and provide it to the sub-pixel. The driving circuit of the present application can perform different brightness compensation on different sub-pixels, thereby effectively improving crosstalk, improving product quality, and increasing market competitiveness.

Description

Driving circuit and driving method thereof, and display device

Technical Field

The present application belongs to the field of optoelectronic technology, and in particular, relates to a driving circuit and a driving method thereof, and a display device.

Background technique

Liquid Crystal Display (LCD) has been increasingly widely studied and applied due to its advantages over traditional cathode ray tube (CRT) displays, such as low power consumption, power saving, environmental protection, low radiation index, large viewing area, almost no increase in volume, and much lighter weight than traditional displays with the same display area.

In LCD, pixels are formed by the intersection of data lines and gate lines, and the pixels include thin film transistors (TFTs) connected to the intersection of the data lines and the gate lines. Thus, in response to the gate pulse from the gate line, each TFT provides the data voltage provided via the data line to the pixel electrode of the liquid crystal unit, and generates an electric field according to the voltage difference between the pixel electrode voltage and the common voltage Vcom applied to the common electrode to drive the liquid crystal unit to deflect. However, due to the electrical coupling with the pixel electrode, the common voltage Vcom is easily disturbed by the data line, and Vcom may experience voltage jitter, which can cause abnormalities such as crosstalk on the screen, resulting in poor performance of the LCD.

Therefore, there is an urgent need to provide an LCD to solve the above problems.

Summary of the invention

In view of this, the embodiments of the present application provide a driving circuit and a driving method thereof, and a display device. The driving circuit can perform different brightness compensations on different sub-pixels, thereby effectively improving the crosstalk phenomenon, thereby improving product quality and increasing market competitiveness.

A first aspect of an embodiment of the present application provides a driving circuit, which is applied to a display device, wherein the display device includes a display panel, wherein the display panel includes a plurality of sub-pixels arranged in an array, and the driving circuit includes: a timing controller, a source driver, and a plurality of data lines, wherein the source driver is electrically connected to the timing controller and the plurality of data lines, respectively, and each of the data lines is also electrically connected to a column of the sub-pixels;

The timing controller is configured to: calculate the influence factor and value of each sub-pixel in a row on a target sub-pixel, take the sum of the influence factor and value and the original data signal as the output data signal, and provide the output data signal to the source driver;

The source driver is configured to: receive the output data signal and convert it into an analog voltage, and provide the analog voltage to the data line;

The data line is configured to receive the analog voltage and provide the analog voltage to the sub-pixel.

In one embodiment, calculating the influence factor and value of each sub-pixel in a row on a target sub-pixel, taking the sum of the influence factor and value and the original data signal as the output data signal, and providing the output data signal to the source driver comprises:

determining the polarity of each of the sub-pixels in each row;

Obtaining a data signal for each of the sub-pixels according to the polarity and the grayscale of the display panel;

Acquire a data signal difference between two adjacent rows of sub-pixels connected to a column of data lines;

The influence factor and value of each sub-pixel in a row on a target sub-pixel are calculated according to the data signal difference, and the sum of the influence factor and value and the original data signal is used as an output data signal, and the output data signal is provided to the source driver.

In one embodiment, obtaining the data signal of each sub-pixel according to the polarity and the grayscale of the display panel includes:

Determine a first polarity of each of the sub-pixels in the Lth row; wherein L is an integer greater than or equal to 1;

Obtaining a first data signal for each of the sub-pixels in the Lth row according to the first polarity and the grayscale of the display panel;

Determining a second polarity of each of the sub-pixels in the L+1th row;

Obtaining a second data signal for each of the sub-pixels in the L+1th row according to the second polarity and the grayscale of the display panel;

The obtaining of the data signal difference of the sub-pixels in two adjacent rows connected to a column of the data lines comprises:

The first data signal is subtracted from the second data signal to obtain the data signal difference.

In one embodiment, when the Lth row is the first row, the grayscales of all the sub-pixels in the L-1th row are 0 grayscale.

In one embodiment, the calculation formula for the influence factor and value of each sub-pixel in a row on a target sub-pixel is:

in,

Xn is the position information of other sub-pixels in a row that affect one target sub-pixel;

Xm is the position information of the target sub-pixel in the horizontal direction;

is the difference between the first data signal and the second data signal.

In one embodiment, before determining the polarity of each of the sub-pixels in each row, the timing controller is further configured to:

According to all gray scales and polarities displayed by the display panel, a data signal of each sub-pixel is obtained.

In one embodiment, obtaining the data signal of each sub-pixel according to all grayscales and polarities displayed by the display panel includes:

Taking the common voltage as the boundary, negative polarity and positive polarity are obtained respectively;

A data signal is obtained according to a gray scale of -255 to 0 and a negative polarity, and a data signal is obtained according to a gray scale of 0 to 255 and a positive polarity;

The data signal of each sub-pixel is obtained according to the gray scale and polarity displayed by the display panel.

In one embodiment, the driving circuit further includes a total polarity reversal control signal line, a column direction polarity reversal control signal line, and a row direction polarity reversal control signal line, and the total polarity reversal control signal line, the column direction polarity reversal control signal line, and the row direction polarity reversal control signal line are electrically connected to the timing controller respectively;

Determining the polarity of each of the sub-pixels in each row includes:

The polarity of each sub-pixel in each row is determined jointly according to the total polarity inversion control signal of the total polarity inversion control signal line, the column polarity inversion control signal of the column direction polarity inversion control signal line, and the row polarity inversion control signal of the row direction polarity inversion control signal line.

A second aspect of the embodiments of the present application provides a display device, including a display panel and the above-mentioned driving circuit, wherein the driving circuit is electrically connected to the display panel.

A third aspect of the embodiments of the present application provides a driving method of the driving circuit described above, wherein the driving circuit is applied to a display device, wherein the display device includes a display panel, wherein the display panel includes a plurality of sub-pixels arranged in an array, and wherein the driving circuit includes: a timing controller, a source driver, and a plurality of data lines, wherein the source driver is electrically connected to the timing controller and the plurality of data lines, respectively, and each of the data lines is also electrically connected to a column of the sub-pixels;

The driving method comprises:

The timing controller calculates the influence factor and value of each sub-pixel in a row on a target sub-pixel, takes the sum of the influence factor and value and the original data signal as an output data signal, and provides the output data signal to the source driver;

The source driver receives the output data signal and converts it into an analog voltage, and provides the analog voltage to the data line;

The data line receives the analog voltage and provides it to the sub-pixel.

The first aspect of the embodiment of the present application provides a driving circuit, in which a timing controller calculates the influence factor and value of each sub-pixel in a row on a target sub-pixel, and provides the sum of the influence factor and value and the original data signal as an output data signal to a source driver. Different influence factors and values can be obtained for different sub-pixels, so that different brightness compensation can be performed on different sub-pixels, thereby effectively improving the crosstalk phenomenon, thereby improving product quality and increasing market competitiveness.

It can be understood that the beneficial effects of the second and third aspects mentioned above can be found in the relevant description of the first aspect mentioned above, and will not be repeated here.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

FIG1 is a schematic diagram of a driving method of a TFT-LCD in a related art provided in Example 1 of the present application;

FIG2 is a simplified schematic diagram of the structure of each sub-pixel in FIG1 ;

FIG3 is a waveform diagram of data S-out in the related art provided in the first embodiment of the present application;

FIG4 is a schematic diagram of the “+” and “-” polarity principles in the related art provided in Example 1 of the present application;

FIG5 is a schematic diagram showing the principle of generating a parasitic capacitance Cg according to the related art provided in the first embodiment of the present application;

FIG6 is a schematic diagram showing the principle of Vcom jitter generation in the related art provided in the first embodiment of the present application;

FIG7 is a schematic structural diagram of a display device provided in Embodiment 2 of the present application;

8 is a schematic diagram of a structure in which a gate line and a data line form a sub-pixel according to a second embodiment of the present application;

FIG. 9 is a flow chart of a driving method of a driving circuit provided in Embodiment 3 of the present application.

Figure Number:

100 - display panel, AA - display area, P - sub-pixel, 210 - timing controller, 240 - source driver, S - data line, 220 - power module, level shifter - 231, gate driver - 232.

Detailed ways

In order to enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work should fall within the scope of protection of the present application.

The term "comprising" and any variations thereof in the specification and claims of the present application and the above-mentioned drawings are intended to cover non-exclusive inclusions. For example, a process, method or system, product or device comprising a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units that are not listed, or may optionally include other steps or units that are inherent to these processes, methods, products or devices. In addition, the terms "first" and "second" and the like are used to distinguish different objects, rather than to describe a specific order. The term "at least one" means "one or more than one". In addition, the term "electrically connected" may refer to a direct electrical connection between two components, or may refer to an electrical connection between two components via one or more other components; "electrically connected" may refer to an electrical connection through a wire, or may refer to an electrical connection through a radio signal.

Embodiment 1

The current TFT-LCD is driven in a line-by-line mode. Referring to FIG1 , when the TFT type is P-type and the Gn signal on the gate line (Gate, abbreviated as G) of the nth row is at a high level, such as 25V in FIG1 , the TFT of this row can be controlled to turn on (On), and at this time, the data voltage in the column direction can be written into the sub-pixel of the nth row through the data line (Source, abbreviated as S).

It should be noted that the type of TFT is P-type. When the Gn-1 signal on the Gate line of the n-1th row and the Gn+1 signal on the Gate line of the n+1th row are at a low level, for example, both the Gn-1 signal and the Gn+1 signal are -5V, the TFT of this row can be controlled to be turned off (Off). At this time, the data voltage in the column direction will not be written into the sub-pixels of the n-1th row and the n+1th row through the S line.

It should be noted that there is no specific limitation on the polarity of the data voltage on the S line. For example, in FIG1 , the Sn-1 line is V1 ⁺ (for example, it can control the red sub-pixel), the Sn line is ^V2- (for example, it can control the green sub-pixel), and the Sn+1 line is V3 ⁺ (for example, it can control the blue sub-pixel).

Each sub-pixel in FIG1 can be simplified as the schematic diagram of FIG2. Referring to FIG2, each sub-pixel includes a control switch TFT, a liquid crystal capacitor Clc, a storage capacitor Cst, a G line responsible for transmitting a switch signal, and an S line responsible for transmitting a data voltage, wherein one end of the liquid crystal capacitor Clc and the storage capacitor Cst is a pixel electrode and the other end is a common electrode.

As shown in Figure 2, the charging and discharging of liquid crystal is a capacitor structure. If a direct current (DC) circuit is used to drive the sub-pixel, residual charges will inevitably be generated at both ends of the capacitor, and afterimages may appear when the picture is displayed. In order to avoid the afterimage phenomenon, the DC is changed to an alternating current (AC) circuit to drive the sub-pixel, and the liquid crystal works by rotating the voltage difference at both ends to obtain different light transmittances.

FIG3 shows the polarity reversal method of the dot reversal corresponding to the entire display screen. FIG3 and FIG4 show that “+” and “-” are voltages compared to the common voltage (Vcom). Specifically, the voltage of the display electrode higher than Vcom is the positive polarity display drive signal “+” (high potential point), and the voltage of the display electrode lower than Vcom is the negative polarity display drive signal “-” (low potential point).

As shown in FIG5 , there is a parasitic capacitance Cg between the S line and the common electrode. During the line switching process of the TFT-LCD, the data voltage on the S line changes to At this time, due to the bootstrap effect of the parasitic capacitor Cg (the capacitor charge is conserved, and the voltage difference between the two ends will not change transiently), the Vcom on the common electrode will also be affected. When the bank is charging and discharging, the TFT in Figure 2 is in the open state, the charge is not conserved, and the voltage at the pixel electrode is the theoretical Data voltage, but Vcom is affected by This causes the voltage difference between the two ends of the liquid crystal to be not the theoretical Data-Vcom, but The voltage difference across the liquid crystal changes, causing the brightness of the sub-pixel to change.

FIG6 shows a waveform diagram of the S line, in which H-active represents the on time of a line, and H-blank represents the off time of a line. Referring to FIG6 , Vcom is easily disturbed by the S line. Compared with the optimal Vcom, the actual Vcom often has voltage jitter. This voltage jitter of Vcom will cause abnormalities such as crosstalk on the display screen, affecting the performance of TFT-LCD.

In one example, an attempt is made to uniformly compensate a row of sub-pixels with the same brightness according to a same brightness difference. However, this compensation is not suitable for the case where the brightness of sub-pixels in a row is inconsistent, because this may cause interference, resulting in some sub-pixels being darker and some sub-pixels being brighter.

Based on the above content, an embodiment of the present application provides a driving circuit, as shown in reference figures 7-8, the driving circuit is applied to a display device, the display device includes a display panel 100, the display panel includes a plurality of sub-pixels P arranged in an array, the driving circuit includes: a timing controller 210, a source driver 240 and a plurality of data lines S, the source driver 240 is electrically connected to the timing controller 210 and the plurality of data lines S, respectively, and each data line S is also electrically connected to a column of sub-pixels P; the timing controller 210 is configured to: calculate the influence factor and value of each sub-pixel P in a row on a target sub-pixel P, take the sum of the influence factor and the original data signal as the output data signal, and provide the output data signal to the source driver 240; the source driver 240 is configured to: receive the output data signal and convert it into an analog voltage, and provide the analog voltage to the data line S; the data line S is configured to: receive the analog voltage and provide it to the sub-pixel P.

The display panel may be an LCD display panel, and the specific type of the display panel is not limited here.

The above sub-pixels may be any one of red sub-pixels, green sub-pixels, blue sub-pixels, etc. The display panel may include three sub-pixels, namely, red sub-pixels, green sub-pixels, or blue sub-pixels; of course, it may also include only one sub-pixel, for example, only multiple red sub-pixels, or only multiple green sub-pixels, or only multiple blue sub-pixels, which may be determined according to actual requirements.

There is no specific limitation on the type and quantity of the above-mentioned source drivers. Exemplarily, the source driver may include a source integrated circuit (SIC), and the number of source drivers may be one or more. When the number of source drivers is one, one source driver may be electrically connected to all data lines; when the number of source drivers is multiple, one source driver may be electrically connected to one data line, or one source driver may be electrically connected to multiple data lines, so that the display panel can be controlled by multiple source drivers in different regions to achieve more accurate regional control. In applications, the source driver is used to provide data signals for displaying images to the data lines, so that the display panel can display images.

The timing controller may be a central control chip (Timer Control Register, Tcon), etc. In applications, the timing controller may transmit a control signal to a source driver through mini-LVDS technology, etc., so as to control the source driver to drive the display panel.

The first embodiment of the present application provides a driving circuit, in which the timing controller in the driving circuit calculates the influence factor and value of each sub-pixel in a row on a target sub-pixel, and provides the sum of the influence factor and value and the original data signal as an output data signal to the source driver, so that different influence factors and values can be obtained for different sub-pixels, so that different brightness compensation can be performed on different sub-pixels, improving the current situation where the brightness of a row cannot be compensated for some pictures due to uniform compensation. Therefore, the data compensation provided in the first embodiment of the present application can effectively improve the crosstalk phenomenon, and is very effective for the brightness compensation of sub-pixels with uneven brightness in a row, thereby improving product quality and increasing market competitiveness.

In one embodiment, referring to FIGS. 7-8 , the timing controller 210 is configured to: determine the polarity of each sub-pixel in each row; obtain the data signal of each sub-pixel P according to the polarity and the grayscale of the display panel 100; obtain the data signal difference between two adjacent rows of sub-pixels P connected to a column of data lines S; calculate the influence factor and value of each sub-pixel P in a row on a target sub-pixel P according to the data signal difference, use the sum of the influence factor and the original data signal as the output data signal, and provide the output data signal to the source driver 240.

Further, the timing controller is configured to: determine the first polarity of each sub-pixel in the Lth row, and obtain the first data signal Data1 of each sub-pixel in the Lth row according to the first polarity and the grayscale of the display panel; determine the second polarity of each sub-pixel in the L+1th row, and obtain the second data signal Data2 of each sub-pixel in the L+1th row according to the second polarity and the grayscale of the display panel; and perform a subtraction between the first data signal and the second data signal to obtain a data signal difference. Right now Then through the formula Calculate the influence factor and value of each sub-pixel in a row on a target sub-pixel; The sum of the original data signal DATA is used as the output data signal DATA_out, and the output data signal DATA_out is provided to the source driver. Wherein, L is an integer greater than or equal to 1; Xn is the position information of other sub-pixels in a row that affect a target sub-pixel; Xm is the position information of the target sub-pixel in the horizontal direction.

At this time, when the Lth row is the first row, the grayscales of all sub-pixels in the L-1th row are 0 grayscale.

The following takes the vertical alignment (VA) type normally black liquid crystal as an example to illustrate how the timing controller provided in the first embodiment of the present application obtains the data signal. Of course, it is not limited to the VA type normally black liquid crystal. Although the "+" and "-" in Figure 4 represent the two polarities of the liquid crystal and separate the voltage, in essence the voltage still has a trend of increasing or decreasing successively. Therefore, the timing controller or external processor in the first embodiment of the present application makes a sequence of the voltage from the high potential point to the low potential point in Figure 4, and the data in this sequence is arranged in descending or ascending order. In other words, one gray scale in the first embodiment of the present application corresponds to one voltage.

The analog voltage and digital signal are summarized to obtain Table 1.

Table 1

V01 V02 V01 V02 V11 V12 V11 V12 5.95 50 … 2.20896838 18 7.35 62 … 12.5629129 106 5.56398438 47 … 2.17797583 18 7.94766 67 … 12.6060993 107 5.2738662 44 … 2.14516018 18 8.27993 70 … 12.651826 107 5.07982612 43 … 2.11052145 17 8.50216 71 … 12.7000931 107 4.90462489 41 … 2.07588271 17 8.70282 73 … 12.7483602 107 4.75391415 40 … 2.04124397 17 8.87543 75 … 12.7966273 108 4.63146167 39 … 2.00478214 16 9.01567 76 … 12.8474347 108 4.53349969 38 … 1.96832031 16 9.12787 77 … 12.8982422 109 4.45626044 37 … 1.93003539 16 9.21633 78 … 12.95159 109 4.39220837 37 … 1.89175047 16 9.28969 78 … 13.0049379 110 4.34322738 36 … 1.85164246 15 9.34578 79 … 13.0608261 110 4.30366581 36 … 1.80971136 15 9.39109 79 … 13.1192547 111 4.26975589 36 … 1.76595716 14 9.42993 79 … 13.1802236 111 4.23961375 35 … 1.72220297 14 9.46445 80 … 13.2411926 112 4.21512325 35 … 1.67662568 14 9.4925 80 … 13.3047019 112 4.19440052 35 … 1.6292253 13 9.51623 80 … 13.3707516 113 4.1736778 35 … 1.58000184 13 9.53997 80 … 13.4393417 113 4.15672284 35 … 1.52713218 12 9.55939 80 … 13.5130125 114 4.14165177 35 … 1.47243944 12 9.57665 81 … 13.5892237 115 4.12658069 34 … 1.41592361 11 9.59391 81 … 13.6679753 115 4.1133935 34 … 1.35758468 11 9.60901 81 … 13.7492673 116 4.10020631 34 … 1.29559957 10 9.62411 81 … 13.8356399 117 4.08890301 34 … 1.23179137 10 9.63706 81 … 13.924553 117 4.0775997 34 … 1.16251389 9 9.65001 81 … 14.0210872 118 4.06818028 34 … 1.08959024 9 9.66079 81 … 14.1227021 119 4.05876086 34 … 1.0130204 8 9.67158 81 … 14.2293978 120 4.04934144 34 … 0.93280437 7 9.68237 82 … 14.3411742 121 4.03992202 34 … 0.84711908 7 9.69316 82 … 14.4605718 122 4.03050259 34 … 0.7559645 6 9.70395 82 … 14.5875904 123 4.02108317 34 … 0.66298684 5 9.71473 82 … 14.7171495 124 4.01354764 33 … 0.61011719 5 9.72336 82 … 14.7908203 125 3.99847656 33 … 0.46 3 9.74063 82 … 15 127

In the above Table 1, V01 and V02 are low voltage parts, corresponding to "-", and V11 and V12 are high voltage parts, corresponding to "+". Among them, V01 is the grayscale voltage calculated based on the gamma voltage (Gamma Corrected Voltage, Gamma voltage) and the resistor string (Resistor String, R-string) inside the source driver, and V02 is the digital voltage value corresponding to the grayscale voltage when the timing controller is calculated inside (the internal calculation of the timing controller is digital, but the grayscale voltage is analog).

As can be seen from Table 1, the grayscale ranges from 0 to -255, V01 is in a decreasing sequence, and V02 corresponding to V01 is negatively correlated with the grayscale, that is, the higher the grayscale, the smaller the value of V02, which meets the actual requirement of "the grayscale is negatively correlated with the voltage in - polarity". Among them, V02 = (corresponding to V01/Gamma1) × K, Gamma1 is the 255 grayscale voltage under the "+" polarity, V01 is the target sub-pixel display grayscale voltage, and K is a constant, such as 127/255.

Moreover, as the grayscale ranges from 0 to 255, V11 is in an increasing sequence, and the corresponding V12 is positively correlated with the grayscale, that is, the higher the grayscale, the larger the V12 value, which meets the actual requirement of "the grayscale in the + polarity is positively correlated with the voltage".

It should be noted that the values of V01, V02, V11 and V12 in Table 1 are only examples and are not limited to the above. The units of V01 and V11 are volts (V), while V02 and V12 have no units.

Moreover, Table 1 only shows a part of the data. For example, in Table 1, V01 is 5.95V at gray scale 0, and is 0.46V at gray scale -255; V11 is 7.35V at gray scale 0, and is 15V at gray scale 255.

In addition, the timing controller may determine the polarity of each sub-pixel in each row according to the total polarity inversion control signal (POL), the column polarity inversion control signal (POLC), and the row polarity inversion control signal (SQINV). Alternatively, after the processor determines the polarity of each sub-pixel in each row according to POL, POLC, and SQINV, the timing controller obtains the polarity of each sub-pixel from the processor.

Since the cause of horizontal crosstalk is the change in the voltage on the data line, in Table 1, V01 or V11, that is, the voltage on the data line, is mapped to the internal operation of the timing controller, that is, V02 or V12, and they are completely one-to-one corresponding. Therefore, in turn, after the timing controller obtains V02 or V12 and the "+" polarity or "-" polarity, it can provide the corresponding analog voltage to the source driver.

Embodiment 1 of the present application provides a driving circuit, in which a timing controller provides the sum of an influencing factor and an original data signal as an output data signal to a source driver, thereby obtaining different influencing factors and values for different sub-pixels, thereby being able to perform different effective compensations for the brightness of different sub-pixels with uneven brightness in a row, thereby improving crosstalk, thereby improving product quality, and increasing market competitiveness.

Embodiment 2

A second embodiment of the present application provides a display device. Referring to FIGS. 7-8 , the display device includes a display panel 100 and the driving circuit in the first embodiment of the present application. The driving circuit is electrically connected to the display panel 100 .

The display panel may be a display panel with a touch function, which is not limited here. The display panel may be a rigid display panel (i.e., a display screen that cannot be bent), which is not limited here. Exemplarily, the display panel may be an LCD display panel. Referring to FIG. 7 , the display panel 100 has a display area AA, which refers to an area for realizing display.

The above-mentioned display device can be any product or component with display function, such as a television, a digital camera, a mobile phone, a tablet computer, etc.; the above-mentioned display device can also be applied to the fields of identity recognition, medical equipment, etc., and the products that have been promoted or have good promotion prospects include security identity authentication, smart door locks, medical image acquisition, etc.

It should be noted that, referring to FIG. 7 , the display device may further include a power module 220, a level shifter 231, and a gate driver 232. The Vcom generated by the power module 220 is provided to the common electrode in the display panel 100 through the common line. The level shifter 231 receives a driving voltage such as a gate high voltage VGH and a gate low voltage VGL, and receives a start pulse ST and a gate clock signal GCLK from the timing controller 210, and outputs a start pulse VST and a clock signal CLK swinging between the gate high voltage VGH and the gate low voltage VGL, wherein VGH is a high level voltage of a scan pulse provided to the G line, and VGL is a low level voltage of a scan pulse provided to the G line.

Only the contents related to the invention are introduced here. The rest can be obtained by referring to the relevant technologies and will not be described in detail here.

The display device provided in the second embodiment of the present application has the advantages of being able to improve crosstalk, low cost, good display effect, long life, high stability, high contrast, good imaging quality, and high product quality.

Embodiment 3

Embodiment 3 of the present application provides a driving method for the above-mentioned driving circuit, wherein the driving circuit is applied to a display device, wherein the display device includes a display panel, and the display panel includes a plurality of sub-pixels arranged in an array; the driving circuit includes: a timing controller, a source driver, and a plurality of data lines, wherein the source driver is electrically connected to the timing controller and the plurality of data lines, respectively, and each data line is also electrically connected to a column of sub-pixels.

Referring to FIG9 , the driving method includes:

S1. The timing controller calculates the influence factor and value of each sub-pixel in a row on a target sub-pixel, takes the sum of the influence factor and value and the original data signal as an output data signal, and provides the output data signal to the source driver.

S2. The source driver receives the output data signal and converts it into an analog voltage, and provides the analog voltage to the data line.

S3. The data line receives the analog voltage and provides it to the sub-pixel.

Embodiment 3 of the present application provides a driving method for a driving circuit. The driving method provides the sum of the influencing factor and the original data signal as an output data signal to a source driver through a timing controller. Different influencing factors and values can be obtained for different sub-pixels, so that different effective compensations can be made for the brightness of different sub-pixels with uneven brightness in a row to improve crosstalk.

Referring to FIG8 , a specific driving method is given below:

In the first step, the polarity of each sub-pixel in the G1 row is determined to be "+" or "-" according to the three signals POL, POLC and SQINV that control the polarity.

The second step is to record V021 of each sub-pixel in the G1 row connected to a data line.

It should be noted that, if it is the first row, all sub-pixels in the previous row are at grayscale 0. At this time, if the polarity is judged to be “-”, V02 is 50.

In the third step, the polarity of each sub-pixel in the G2 row is determined to be "+" or "-" according to the three signals POL, POLC, and SQINV that control the polarity.

The fourth step is to record V022 of each sub-pixel in the G2 row connected to the same data line.

Step 5: Calculate

Step 6: Calculate the sum of the effects of each sub-pixel in a row on the target sub-pixel

For example, referring to FIG8 , the distance between S1 and S5 is 5−1+1=5.

Step 7: Add the impact amount to the displayed data.

Only the contents related to the invention are introduced here. The rest can be obtained by referring to the relevant technologies and will not be described in detail here.

The above are only preferred embodiments of the present application and are not intended to limit the present application. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims (10)

1. A driving circuit, characterized by being applied to a display device including a display panel including a plurality of sub-pixels arranged in an array, comprising: the display device comprises a time sequence controller, a source driver and a plurality of data lines, wherein the source driver is respectively and electrically connected with the time sequence controller and the data lines, and each data line is also electrically connected with a column of the sub-pixels;

The timing controller is configured to: calculating an influence factor sum value of each sub-pixel in a row on one target sub-pixel, taking the sum value of the influence factor sum value and an original data signal as an output data signal, and providing the output data signal for the source driver;

the source driver is configured to: receiving the output data signal and converting the output data signal into an analog voltage, and providing the analog voltage to the data line;

The data line is configured to: the analog voltage is received and provided to the sub-pixel.

2. The driving circuit as recited in claim 1 wherein said calculating an impact factor sum value for each of said subpixels in a row on a target subpixel, taking a sum of said impact factor sum value and an original data signal as an output data signal, providing said output data signal to said source driver comprises:

determining the polarity of each of the sub-pixels in each row;

obtaining a data signal of each sub-pixel according to the polarity and the gray scale of the display panel;

acquiring data signal differences of two adjacent rows of sub-pixels connected with a column of the data lines;

And calculating the influence factor sum value of each sub-pixel in a row to one target sub-pixel according to the data signal difference, taking the sum value of the influence factor sum value and an original data signal as an output data signal, and providing the output data signal to the source driver.

3. The driving circuit according to claim 2, wherein said deriving a data signal for each of said sub-pixels from said polarity and gray scale of said display panel comprises:

Determining a first polarity of each of the subpixels in the L-th row; wherein L is an integer greater than or equal to 1;

Obtaining a first data signal of each sub-pixel in an L-th row according to the first polarity and the gray scale of the display panel;

Determining a second polarity for each of the subpixels in row L+1;

obtaining a second data signal of each sub-pixel in the L+1 row according to the second polarity and the gray scale of the display panel;

The step of obtaining the data signal difference between two adjacent rows of the sub-pixels connected with one column of the data lines comprises the following steps:

And performing difference on the first data signal and the second data signal to obtain the data signal difference.

4. The driving circuit as recited in claim 3 wherein when said L-1 row is the first row, then all of said sub-pixels in L-1 row have a gray level of 0.

5. The driving circuit as claimed in claim 3 or 4, wherein the calculation formula of the influence factor and value of each of the sub-pixels in a row on one target sub-pixel is:

Wherein,

Xn is the position information of other subpixels within a row that affect one of the target subpixels;

Xm is positional information of the target subpixel in a horizontal direction;

is the difference between the first data signal and the second data signal.

6. The drive circuit of claim 2, wherein prior to the determining the polarity of each of the subpixels in each row, the timing controller is further configured to:

and obtaining the data signal of each sub-pixel according to all gray scales and polarities displayed by the display panel.

7. The driving circuit as recited in claim 6 wherein said deriving a data signal for each of said sub-pixels based on all gray scales and polarities displayed by said display panel comprises:

respectively obtaining a negative polarity and a positive polarity by taking the public voltage as a boundary;

Obtaining a data signal according to the gray scales-255-0 and the negative polarity, and obtaining the data signal according to the gray scales 0-255 and the positive polarity;

and acquiring the data signal of each sub-pixel according to the gray scale and the polarity displayed by the display panel.

8. The drive circuit according to claim 2, further comprising a total polarity inversion control signal line, a column direction polarity inversion control signal line, a row direction polarity inversion control signal line, the total polarity inversion control signal line, the column direction polarity inversion control signal line, the row direction polarity inversion control signal line being electrically connected to the timing controller, respectively;

the determining the polarity of each of the subpixels in each row includes:

The polarity of each sub-pixel in each row is determined according to the total polarity inversion control signal of the total polarity inversion control signal line, the column polarity inversion control signal of the column direction polarity inversion control signal line and the row polarity inversion control signal of the row direction polarity inversion control signal line.

9. A display device comprising a display panel and a drive circuit according to any one of claims 1-8, the drive circuit being electrically connected to the display panel.

10. A driving method of a driving circuit according to any one of claims 1 to 8, wherein the driving circuit is applied to a display device including a display panel including a plurality of sub-pixels arranged in an array, the driving circuit comprising: the display device comprises a time sequence controller, a source driver and a plurality of data lines, wherein the source driver is respectively and electrically connected with the time sequence controller and the data lines, and each data line is also electrically connected with a column of the sub-pixels;

the driving method includes:

The time schedule controller calculates the influence factor sum value of each sub-pixel in a row on one target sub-pixel, takes the sum value of the influence factor sum value and an original data signal as an output data signal, and provides the output data signal for the source driver;

The source driver receives the output data signal and converts the output data signal into an analog voltage, and provides the analog voltage to the data line;

the data line receives the analog voltage and supplies the analog voltage to the sub-pixel.