CN1183588C - Ball grid array package substrate and manufacturing method thereof - Google Patents
Ball grid array package substrate and manufacturing method thereof Download PDFInfo
- Publication number
- CN1183588C CN1183588C CN 02101667 CN02101667A CN1183588C CN 1183588 C CN1183588 C CN 1183588C CN 02101667 CN02101667 CN 02101667 CN 02101667 A CN02101667 A CN 02101667A CN 1183588 C CN1183588 C CN 1183588C
- Authority
- CN
- China
- Prior art keywords
- substrate
- pattern
- ball
- copper foil
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 156
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 25
- 229910000679 solder Inorganic materials 0.000 claims abstract description 79
- 239000003292 glue Substances 0.000 claims abstract description 31
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 58
- 239000011889 copper foil Substances 0.000 claims description 51
- 238000000034 method Methods 0.000 claims description 51
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 28
- 229910052759 nickel Inorganic materials 0.000 claims description 14
- 229910052737 gold Inorganic materials 0.000 claims description 13
- 239000010931 gold Substances 0.000 claims description 13
- 238000009713 electroplating Methods 0.000 claims description 10
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 9
- -1 polyethylene Polymers 0.000 claims description 8
- 229910052802 copper Inorganic materials 0.000 claims description 7
- 239000010949 copper Substances 0.000 claims description 7
- 238000000059 patterning Methods 0.000 claims description 6
- 229920006267 polyester film Polymers 0.000 claims description 6
- 239000004698 Polyethylene Substances 0.000 claims description 5
- 229920000573 polyethylene Polymers 0.000 claims description 5
- 229920000178 Acrylic resin Polymers 0.000 claims description 4
- 239000004925 Acrylic resin Substances 0.000 claims description 3
- 239000004743 Polypropylene Substances 0.000 claims description 3
- 229920001155 polypropylene Polymers 0.000 claims description 3
- 230000000994 depressogenic effect Effects 0.000 claims 6
- 210000004400 mucous membrane Anatomy 0.000 claims 6
- 238000010422 painting Methods 0.000 claims 2
- 238000001259 photo etching Methods 0.000 claims 1
- 230000005855 radiation Effects 0.000 claims 1
- 230000017525 heat dissipation Effects 0.000 abstract description 71
- 239000010410 layer Substances 0.000 description 117
- 239000002313 adhesive film Substances 0.000 description 22
- 229920002120 photoresistant polymer Polymers 0.000 description 19
- 238000000206 photolithography Methods 0.000 description 12
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 11
- 238000005530 etching Methods 0.000 description 8
- 230000001681 protective effect Effects 0.000 description 8
- 239000000853 adhesive Substances 0.000 description 6
- 230000001070 adhesive effect Effects 0.000 description 6
- 239000011248 coating agent Substances 0.000 description 5
- 238000000576 coating method Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 238000012536 packaging technology Methods 0.000 description 5
- 238000007650 screen-printing Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 239000011347 resin Substances 0.000 description 4
- 229920005989 resin Polymers 0.000 description 4
- 238000010020 roller printing Methods 0.000 description 4
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- 229910052709 silver Inorganic materials 0.000 description 3
- 239000004332 silver Substances 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000005553 drilling Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 238000007790 scraping Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000004952 Polyamide Substances 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- NIXOWILDQLNWCW-UHFFFAOYSA-N acrylic acid group Chemical group C(C=C)(=O)O NIXOWILDQLNWCW-UHFFFAOYSA-N 0.000 description 1
- 239000012790 adhesive layer Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000009429 electrical wiring Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000003365 glass fiber Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 229920003023 plastic Polymers 0.000 description 1
- 229920002647 polyamide Polymers 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
技术领域technical field
本发明揭露一种有关于BGA(ball grid array)的封装技术,特别是指具有散热层(heat sink layer)之BGA基板的封装技术,该散热层可利用导电穿孔与接地焊锡球(Solder ball for ground)或电源焊锡球(solderball for power)相连接,或者可包含电源图案和接地图案,并分别利用导电穿孔与电源焊锡球(Solder ball for Power)和接地焊锡球(Solder ballfor ground)相连接。The present invention discloses a packaging technology related to BGA (ball grid array), especially the packaging technology of a BGA substrate with a heat sink layer. ground) or power solder balls (solder ball for power), or may include power patterns and ground patterns, and use conductive vias to connect with power solder balls (Solder ball for Power) and ground solder balls (Solder ball for ground) respectively.
背景技术Background technique
随着集成电路制程的进步,藉由芯片(die)整体尺寸缩小,降低单位成本,已成趋势,半导体业者更期待某些方面的性能,例如执行速度,可因此获得显著改善,而且单一芯片可以注入更多的功能。然而,芯片尺寸缩小,虽增加芯片功能,组件却不减反增的情况下,导致连接导线更加密集,因此,衍生的寄生电容与内联机阻值的增加,都使芯片性能下降。With the advancement of the integrated circuit manufacturing process, it has become a trend to reduce the unit cost by reducing the overall size of the chip (die). The semiconductor industry expects some aspects of performance, such as execution speed, to be significantly improved, and a single chip can Inject more functionality. However, as the size of the chip shrinks, although the functions of the chip increase, the number of components increases instead of decreasing, resulting in denser connecting wires. Therefore, the resulting parasitic capacitance and the increase in the resistance of the interconnection lead to a decrease in chip performance.
为解决上述问题,半导体制造业,除了利用低阻值的铜导线取代传统的铝导线来降低导线阻值,更寻求低介电常数介电层解决寄生电容的问题。另一具有对成本与性能有直接关键性影响的是封装技术。因为可以想到当芯片组件增加以注入新的功能时,势必大量增加输出入端子来与系统进行连接的问题,同时芯片的功率消耗与散热问题也因此更加突显。为克服上述问题,即便是新一代的倒装式芯片封装技术与球栅格阵列的BGA封装技术也需要加以研讨。In order to solve the above problems, the semiconductor manufacturing industry, in addition to using low-resistance copper wires to replace traditional aluminum wires to reduce wire resistance, also seeks a low-k dielectric layer to solve the problem of parasitic capacitance. Another area that has a direct and critical impact on cost and performance is packaging technology. Because it is conceivable that when the chip components are added to inject new functions, the problem of increasing the number of input and output terminals to connect with the system is bound to be increased, and at the same time, the power consumption and heat dissipation problems of the chip are also more prominent. In order to overcome the above problems, even the new generation of flip-chip packaging technology and BGA packaging technology of ball grid array need to be studied.
图1-8,为习知包含散热层的BGA封装基板制程。步骤如下:首先请参考图1,一基板5压合一铜箔8,并形成TAB贯通孔10(sprocket hole),于基板5的边界内,TAB贯通孔10有利于基板5在输送带上的传输。基板5可以是BT(bismaleimide-triazine)或玻璃纤维、强化环氧树脂、聚醯氨等绝缘性材料之一。对T-BGA而言,典型的基板上都只有一层金属图案,铜箔8是用以定义导线图案及锡球的连接图案。Figures 1-8 show the conventional BGA package substrate manufacturing process including heat dissipation layer. The steps are as follows: first please refer to FIG. 1, a
随后如图2所示,TAB贯通孔10表面先去毛边(desmear)、化学抛光等。接着,形成光阻(图中未示)于铜箔8上,并施以光刻制程以定义图案。经显影后,再以光阻图案作为蚀刻罩幕以蚀刻铜箔形成电导线图案及/或焊锡球之连接图案20,最后再剥除光阻。Subsequently, as shown in FIG. 2 , the surface of the TAB through-
随后,如图3所示,再覆盖一背胶膜25于基板5背面,用以防止阻焊剂(solder mask)粘附。随后再形成具绝缘性及防止粘附焊锡的阻焊剂30于铜箔8上。再经光刻制程及显影步骤将铜箔8焊锡球的连接图案20上的阻焊剂去除。Subsequently, as shown in FIG. 3 , a back adhesive film 25 is covered on the back of the
请参见图4,接着,进行电镀制程,在铜箔8上依序形成镍膜层及金膜层35。紧接着再去除背胶膜25。Please refer to FIG. 4 , and then, an electroplating process is performed to sequentially form a nickel film layer and a
请参见图5,将基板划割,随后,再粘贴一粘着层42于基板5背面,再将基板核心区域材料切除,以形成容置芯片的凹陷区40。必要时也可形成总线贯穿孔及组件贯穿孔,最后,再将焊锡球以网板印刷方式形成于金膜层35上。其结果如图6所示。Referring to FIG. 5 , the substrate is diced, and then an
传统制程为形成散热层,需要再将散热片一片接一片粘贴上去。因此,不但耗时,且效果有限。因为散热片55是隔着一层绝缘基板与正面图案层的电源电导线或接地电导线遥对,彼此没有连接。In order to form a heat dissipation layer in the traditional manufacturing process, heat sinks need to be pasted one by one. Therefore, it is not only time-consuming, but also has limited effect. Because the
图6、7所示,为3M公司的方法,3M公司在TAB贯穿孔10形成后,TAB贯穿孔10内再利用挤入导电胶的方式使基板图案正面与散热层导通。不过,上述连接也并未充分使图案层的散热效果发挥,毕竟,连接电压的电导线或接地的电导线并没有连接至散热层。As shown in Figures 6 and 7, it is the method of 3M Company. After the TAB through
因此,习知技术所制作的BGA基板散热层效果不佳,未加以进一步利用。本发明将提供新的BGA基板架构,改善上述问题,并提供相应的制造方法。Therefore, the heat dissipation layer of the BGA substrate produced by the conventional technology has poor effect and has not been further utilized. The present invention will provide a new BGA substrate structure, improve the above problems, and provide a corresponding manufacturing method.
发明内容Contents of the invention
本发明的目的是要提供一种球栅格阵列封装基板及其制造方法。The object of the present invention is to provide a ball grid array package substrate and a manufacturing method thereof.
本发明的另一目的,是应用贯穿孔使BGA基板图案层与散热层的接地图案与/或电源图案相连接。由于散热层的导通,使BGA基板图案的接地图案与/或电源图案分散于散热层,进而增加导线布线面积或减少BGA基板面积。Another object of the present invention is to use through holes to connect the pattern layer of the BGA substrate with the ground pattern and/or power pattern of the heat dissipation layer. Due to the conduction of the heat dissipation layer, the ground pattern and/or the power supply pattern of the BGA substrate pattern are scattered on the heat dissipation layer, thereby increasing the wire wiring area or reducing the BGA substrate area.
本发明的技术方案是:一种球栅格阵列封装基板,在BGA基板的一面具有连接焊锡球的单一图案层,而散热层结合于该基板的另一面,其特征在于:该散热层除提供BGA基板散热外,同时也提供该BGA基板的接地及/或电源图案,用以分散该BGA基板图案层的接地和/或电源图案所需之面积,其中该BGA基板的接地和/或电源锡球是利用填满导电胶的贯穿孔来与该散热层相连接。其中:The technical solution of the present invention is: a ball grid array packaging substrate, which has a single pattern layer connected with solder balls on one side of the BGA substrate, and the heat dissipation layer is combined with the other side of the substrate, and is characterized in that: the heat dissipation layer not only provides In addition to the heat dissipation of the BGA substrate, the grounding and/or power pattern of the BGA substrate is also provided to disperse the area required for the grounding and/or power pattern of the BGA substrate pattern layer, wherein the grounding and/or power supply tin of the BGA substrate The balls are connected to the heat dissipation layer through holes filled with conductive glue. in:
所述导电胶至少包含银胶、铜胶其中之一。The conductive glue includes at least one of silver glue and copper glue.
所述不粘膜是与导电胶不具亲和性的薄膜。The non-adhesive film is a film that has no affinity with the conductive adhesive.
所述不粘膜至少包含聚乙烯膜、聚丙烯膜、聚脂膜或亚克力树脂其中之一种。The non-adhesive film comprises at least one of polyethylene film, polypropylene film, polyester film or acrylic resin.
一种球栅格阵列封装基板的制作方法,至少包含以下步骤:A method for manufacturing a ball grid array package substrate, at least including the following steps:
提供一BGA基板,该基板上、下两面各有一层不粘膜;Provide a BGA substrate with a layer of non-adhesive film on the upper and lower sides of the substrate;
在该基板中形成若干个贯穿孔及一凹陷区,该贯穿孔形成于该基板预定的接地焊锡球位置,而凹陷区用来置放一芯片;Forming several through holes and a recessed area in the substrate, the through holes are formed at the predetermined ground solder ball position of the substrate, and the recessed area is used to place a chip;
该基板的贯穿孔中注满导电胶;The through hole of the substrate is filled with conductive glue;
去除不粘膜;removal of non-mucosal membranes;
在该基板上、下两面分别形成一散热层及一铜箔;A heat dissipation layer and a copper foil are respectively formed on the upper and lower surfaces of the substrate;
在该铜箔上形成该BGA基板焊锡球连接的图案与导线图案;Forming the pattern and wire pattern connected by solder balls of the BGA substrate on the copper foil;
在该散热层上涂布黑色油墨;coating black ink on the heat dissipation layer;
在该凹陷区内形成一黑色油墨;forming a black ink in the recessed area;
在包含该BGA基板焊锡球连接的图案与导线图案上涂布阻焊剂;Coating a solder resist on the pattern and the wire pattern including the solder ball connection of the BGA substrate;
施以光刻制程,用以裸露该BGA基板焊锡球连接的铜箔图案;A photolithography process is applied to expose the copper foil pattern connected by the solder balls of the BGA substrate;
施以电镀制程,用以在该铜箔图案上镀镍膜及金膜;Applying an electroplating process to plate a nickel film and a gold film on the copper foil pattern;
在该金膜上形成焊锡球;forming solder balls on the gold film;
将该芯片置于黑色油墨上,并用导线将该芯片上的接触垫与该BGA基板焊锡球连接的图案与导线图案相连接。其中:The chip is placed on the black ink, and the contact pad on the chip is connected with the solder ball of the BGA substrate to connect the pattern and the wire pattern with the wire. in:
所述至少包含银胶、铜胶其中之一的导电胶,是以刮刀或滚筒印刷其中之一种注入于贯穿孔中。The conductive glue containing at least one of silver glue and copper glue is injected into the through hole by scraping or roller printing.
所述散热层是在涂布黑色油墨之前,先在散热层镀上镍层。The heat dissipation layer is coated with a nickel layer on the heat dissipation layer before coating the black ink.
一种球栅格阵列封装基板的制作方法,至少包含以下步骤:A method for manufacturing a ball grid array package substrate, at least including the following steps:
提供一基板,该基板的一面包含有一层铜箔,且上、下两面各有一层不粘膜;A substrate is provided, one side of the substrate includes a layer of copper foil, and a layer of non-adhesive film is provided on the upper and lower sides;
在该基板中形成若干个贯穿孔及一凹陷区,该贯穿孔形成于该基板预定的接地焊锡球及电源焊锡球位置,该凹陷区用来置放一芯片;Forming a plurality of through holes and a recessed area in the substrate, the through holes are formed at the predetermined positions of the ground solder ball and the power solder ball of the substrate, and the recessed area is used to place a chip;
该基板的贯穿孔中形成导电胶;Conductive glue is formed in the through holes of the substrate;
去除不粘膜;removal of non-mucosal membranes;
在该基板不含铜箔的另一面形成一散热层;forming a heat dissipation layer on the other side of the substrate that does not contain copper foil;
在该凹陷区形成一黑色油墨;forming a black ink in the recessed area;
对该铜箔图案化,以形成信号图案及连接电源锡球与接地锡球的图案于其中;Patterning the copper foil to form a signal pattern and a pattern connecting the power solder ball and the ground solder ball therein;
对该散热层图案化,以形成接地图案及电源图案于其中;patterning the heat dissipation layer to form a ground pattern and a power pattern therein;
在该散热层上形成黑色油墨;forming black ink on the heat dissipation layer;
在该基板包含信号图案的一面上形成阻焊剂;forming a solder resist on one side of the substrate containing signal patterns;
施以光刻制程,以裸露部分之铜箔图案,该部分之铜箔图案是用以连接电源锡球与接地锡球;Apply a photolithography process to expose a part of the copper foil pattern, which is used to connect the power solder ball and the ground solder ball;
施以电镀制程,用以在该裸露的铜箔图案上依序镀镍膜及金膜;Applying an electroplating process to sequentially plate a nickel film and a gold film on the exposed copper foil pattern;
在该金膜上形成锡球,使该基板的接地锡球及电源锡球可通过该基板贯穿孔的导电胶,分别连接至该散热层的接地图案及电源图案;Solder balls are formed on the gold film, so that the ground solder balls and power solder balls of the substrate can be connected to the ground pattern and power pattern of the heat dissipation layer through the conductive glue in the through hole of the substrate;
将该芯片置于黑色油墨上,并用导线将该芯片上的接触垫与该BGA基板焊锡球连接的图案与导线图案相连接。其中:The chip is placed on the black ink, and the contact pad on the chip is connected with the solder ball of the BGA substrate to connect the pattern and the wire pattern with the wire. in:
所述对该铜箔图案化及该散热层图案化,是利用光刻及蚀刻制程进行的。The patterning of the copper foil and the patterning of the heat dissipation layer are carried out by photolithography and etching processes.
所述至少包含银胶、铜胶其中之一的导电胶,是以刮刀或滚筒印刷其中的一种导电胶注入该贯穿孔。The conductive glue containing at least one of silver glue and copper glue is injected into the through hole by scraping or roller printing one of the conductive glue.
本发明的有益效果:Beneficial effects of the present invention:
1.将基板上接地/或接电源的导电锡球和电导线利用若干个贯穿孔与散热片连接,因此,有利于基板的散热。1. Connect the conductive solder balls and electric wires on the substrate to the ground/or to the power supply with the heat sink through several through holes, so it is beneficial to the heat dissipation of the substrate.
2.上述连接基板正反面的贯穿孔是利用挤入导电胶的方式,比一般贯通孔采用电镀方式更加方便和便宜。其中为防止不需要连接的部分粘上导电胶,使用不粘膜层。因此勿须担心,铜箔正面粘上导电胶。2. The above-mentioned through holes connecting the front and back of the substrate are made by extruding conductive glue, which is more convenient and cheaper than the general through holes using electroplating. Among them, in order to prevent the parts that do not need to be connected from sticking to the conductive adhesive, a non-adhesive film layer is used. So don't worry, the front side of the copper foil is glued with conductive glue.
3.由于本发明是以热压合方式将基板上所需要的图案和散热层(包含其图案)一气呵成。不需要将散热片一片片的粘附于基板。故可节省人力和物料。3. Because the present invention forms the required pattern on the substrate and the heat dissipation layer (including the pattern) in one go by thermocompression bonding. There is no need to attach the heat sink piece by piece to the substrate. Therefore, manpower and materials can be saved.
4.本发明的散热层不仅是散热层,同时可作为接地图案及电源图案,因此,可分散BGA基板图案层所需要的接地及电源图案所需的面积。可增加布局设计的弹性。4. The heat dissipation layer of the present invention is not only a heat dissipation layer, but also can be used as a grounding pattern and a power supply pattern. Therefore, the area required for the grounding and power supply patterns required by the BGA substrate pattern layer can be dispersed. Can increase the flexibility of layout design.
附图说明Description of drawings
图1-6、为传统BGA基板的制作工艺流程图,散热层与BGA图案层之间并没有连接。Figure 1-6 is a flow chart of the manufacturing process of a traditional BGA substrate, and there is no connection between the heat dissipation layer and the BGA pattern layer.
图7、8,为另一种习知技术所制作的BGA基板的制作工艺流程图,基板的BGA图案层仅由TAB贯通孔连接散热层。7 and 8 are flow charts of the manufacturing process of a BGA substrate produced by another conventional technology. The BGA pattern layer of the substrate is only connected to the heat dissipation layer by TAB through holes.
图9-20,为本发明第一实施例之方法的制作工艺流程图,其BGA图案层中,散热层由若干个导电贯穿孔连接BGA图案层的接地焊锡球。9-20 are the flow charts of the manufacturing process of the method according to the first embodiment of the present invention. In the BGA pattern layer, the heat dissipation layer is connected to the ground solder ball of the BGA pattern layer by several conductive through-holes.
图21,为本发明第一、二实施例之方法制作的BGA基板之架构图。FIG. 21 is a structural diagram of a BGA substrate manufactured by the method of the first and second embodiments of the present invention.
图22-25,为本发明第二实施例之方法制作BGA基板的工艺流程图,图中仅显示与第一实施例工艺流程不同的部分。22-25 are process flow charts for manufacturing BGA substrates by the method of the second embodiment of the present invention, and only the parts different from the process flow of the first embodiment are shown in the figures.
图26-35,为本发明第三实施例之方法制作BGA基板的工艺流程图,BGA图案层中,接地焊锡球及电源焊锡球由贯穿孔分别连接至散热层的接地图案与电源图案。26-35 are the process flow diagrams for manufacturing BGA substrates according to the third embodiment of the present invention. In the BGA pattern layer, the ground solder balls and power solder balls are respectively connected to the ground pattern and power pattern of the heat dissipation layer through through holes.
图36,为本发明第三实施例之方法制作的BGA基板之架构图。Fig. 36 is a structure diagram of a BGA substrate manufactured by the method of the third embodiment of the present invention.
具体实施方式Detailed ways
有鉴于发明背景技术所述,习知技术中粘贴于基板的散热层,是隔着基板与图案层相对,因此,可达到的散热效果必定有限。传统BGA基板即使有连接,例如,3M公司的专利,一片基板也只利用了传送带上所保留的约8个贯通孔(sprocket hole)而已,可增加的散热效果有限。有鉴于此,In view of the background of the invention, in the prior art, the heat dissipation layer pasted on the substrate is opposed to the pattern layer through the substrate, so the achievable heat dissipation effect must be limited. Even if the traditional BGA substrate is connected, for example, 3M's patent, a substrate only utilizes about 8 through holes (sprocket holes) reserved on the conveyor belt, and the heat dissipation effect that can be increased is limited. In view of this,
本发明提供改良的球栅格阵列封装基板及其制造方法,可以解决上述问题。The invention provides an improved ball grid array packaging substrate and a manufacturing method thereof, which can solve the above problems.
参见图9-20,本发明第一实施例之方法制作BGA基板的工艺流程如下:Referring to Figures 9-20, the process flow for manufacturing a BGA substrate according to the first embodiment of the present invention is as follows:
首先,参见图9,在基板205的两面先各粘贴一层不粘膜(releasefilm)210a,210b。不粘膜选用与导电胶不具亲和性的薄膜,例如聚乙烯膜(polyethylenefilm)、聚丙烯膜polyacryline film)、聚脂膜(PET)或亚克力(acrylic)树脂,其中的任一种皆可。随后,以CO2激光钻孔,以形成贯穿孔215、切割基板以便在基板205之中形成凹陷区220。请注意贯穿孔215之位置设于预定的接地焊锡球(solder ball for ground)位置。接着,如图10所示,将导电胶225以滚筒印刷方式或刮刀挤入贯穿孔215内。由于基板205上具有不粘膜210a、210b,因此只有贯穿孔215粘附导电胶225,而形成如图10所示的铆钉状之后,以刮板移除高于基板205表面的导电胶225。紧接着,再去除不粘膜210a,保留不粘膜210b,结果如图11所示。请参见图12、13,利用热压合法,在基板205上形成一较厚的铜箔,作为散热层230。接着在凹陷区220表面形成一黑色油墨235,黑色油墨235具有增加芯片固定于凹陷区的固定功能。First, referring to FIG. 9 , a layer of release film (release film) 210a, 210b is pasted on both sides of the
请参见图14,接着,去除不粘膜层210b。将第二铜箔206压合于基板205不具散热层的一面,作为BGA基板的导电图案层。随后如图15所示,形成负型光阻245,并以掩膜250a及250b作为光刻罩幕,再施以曝光制程以定义图案。再经显影制程形成如图16所示的光阻图案245c、245a、245b。请注意由于散热层230上是透光的掩膜250a,因此光阻照光后光阻图案245c将不会被显影去除。而第二铜箔206上除了焊锡球连接的光阻图案245a外,并有电导线(conductive trace)的光阻图案245b作为蚀刻罩幕。Please refer to FIG. 14 , next, the
请参见图17,再以光阻图案245c、245a、245b为罩幕,以酸性溶液或电浆蚀刻第二铜箔206以形成图案层206a。最后再移除光阻图案245c、245a、245b。Referring to FIG. 17 , using the
紧接着,如图18所示,以黑色油墨252涂布于散热层230上作为绝缘层。请注意涂布黑色油墨于散热层之前,可选择性的先在散热层230镀上镍层。接着再涂布阻焊剂255(solder mask)于图案层206a上。Next, as shown in FIG. 18 ,
请参见图19,再以掩膜图案260进行曝光及显影制程,裸露锡球所要连接的铜箔处。最后以电镀制程依序镀镍及金膜270于裸露的铜箔上,其结果如图20所示。最后将锡球以网板印刷方式接种于镀金膜层270上。芯片275安置于凹陷区220,并将芯片275上的接触垫以导线引脚280连接于图案层206a上。最后,再以树脂285将芯片275及导线包覆,得到如图21所示的结构。Referring to FIG. 19 , the exposure and development processes are performed with the mask pattern 260 to expose the copper foil to be connected by the solder balls. Finally, nickel and
上述的制程程序中,部分步骤是可以更换先后顺序而不影响最后的结果。In the above-mentioned process procedure, some steps can be changed in sequence without affecting the final result.
请参见图22,发明第二实施例之方法,在将导电胶225注入贯通孔215,并以刮板移除高于基板205表面的导电胶和去除不粘膜210a,210b后(参见图10),即将铜箔206及散热层230同时压合于基板205的两面。Please refer to FIG. 22, the method of the second embodiment of the invention, after injecting the
接着,如图23所示,利用光刻技术,形成光阻图案245a、245b及245c。Next, as shown in FIG. 23 ,
随后,如图24所示,再进行蚀刻,以光阻图案245a、245b及245c为罩幕形成图案层206a,用以形成连接焊锡球的图案层及导线图案层。Subsequently, as shown in FIG. 24 , etching is performed again, and the
接着,如图25所示,涂布黑色油墨252于散热层230上作为绝缘层。再将一护膜232粘贴于图案层206a上。随后,再形成黑色油墨235于凹陷区220之中。Next, as shown in FIG. 25 ,
随后,将护膜232撕去。如第一实施例所述方法涂布阻焊剂255及进行光刻制程,以裸露连接焊锡的铜箔,再镀镍及金膜,并进行焊锡球的连接。其结果如图21所示。Subsequently, the
既然基板的散热层与图案层可由导电贯穿孔相连接,BGA基板上图案层的若干电源图案和接地图案则可分配至基板的散热层上。因此,本发明第三实施例的方法,详述如下:Since the heat dissipation layer and the pattern layer of the substrate can be connected by conductive through holes, several power supply patterns and ground patterns of the pattern layer on the BGA substrate can be distributed to the heat dissipation layer of the substrate. Therefore, the method of the third embodiment of the present invention is described in detail as follows:
首先,请参见图26,在包含一层铜箔206(基板正面)的基板205的两面先各粘贴一层不粘膜层(release film)210a、210b。不粘膜是选用与导电胶不具亲和性的薄膜。例如:聚乙烯膜(polyethylene film)、聚丙烯膜(polyacryline film)、聚脂膜(PET)或亚克力(acrylic)树脂其中之一种皆可。随后,以CO2激光钻孔,以形成贯穿孔215,及切割基板以便在基板205之中形成凹陷区220,如图27所示。请注意贯穿孔215之位置是设于预定的球脚接地(ball-grid for ground)位置及预定的球脚电源(ball-grid for power)位置。接着,如图28所示,将导电胶225以滚筒印刷方式或刮刀挤入贯穿孔215内。由于基板205上、下两面分别含不粘膜层210a、210b,因此只有贯穿孔215粘附导电胶225,而形成如图28所示的铆钉状。First, referring to FIG. 26 , a layer of release film (release film) 210a, 210b is pasted on both sides of the
随后,以刮板移除高于基板205表面的导电胶。紧接着,再去除不粘膜层210b,210a,结果如图29所示。Subsequently, the conductive glue higher than the surface of the
请参见图30,利用热压合法,在基板上形成另一较厚之铜箔作为散热层230。接着,在基板205的铜箔206及散热层230上各粘贴一护膜232。随后,再将黑色油墨235涂布于凹陷区220表面,黑色油墨235具有粘附芯片并使其固定于凹陷区220的功能。Referring to FIG. 30 , another thicker copper foil is formed on the substrate as a
请参见图31,接着,在去除护膜232后,再分别在散热层230及铜箔206上涂布负型光阻245,再以掩膜250a及250b作为光刻罩幕,再施以曝光制程以定义图案。请注意,掩膜250a的图案包含电源图案/接地图案。而掩膜250b的图案包含信号图案及电源/接地图案。Please refer to FIG. 31, and then, after removing the
如图32所示,经显影制程形成的光阻图案245a、245b。在散热层230上的光阻图案245a为电源图案与接地图案。而铜箔206上的光阻图案245b则为信号连接的导电图案,以及连接焊锡球的电源图案与接地图案。随后以光阻图案245a、245b为罩幕,施以蚀刻制程而形成图案层230a和206a。换言之,利用本发明的方法,可将BGA图案层中所需的电源图案与接地图案移至散热层230,由散热层230承担。而铜箔206只安排信号图案及连接焊锡球必要的图案即可。因此,由于信号导线在基板一面,而接地及电源等导电图案在基板另一面,不但可缩小整个BGA所需的面积,且可降低噪声。As shown in FIG. 32 , the
如图33所示,将残留的光阻图案剥除,随后再涂布黑色油墨252于散热图案层230a上作为绝缘层。请注意涂布黑色油墨于该散热层之前,可先选择性地在散热层230a镀上镍层。紧接着,再涂布阻焊剂255(solder mask)于图案层206a上。As shown in FIG. 33 , the remaining photoresist pattern is stripped off, and then
请参见图34,以掩膜图案260a、260b为罩幕,进行曝光及显影制程,以裸露锡球所要连接的铜箔处。裸露的铜箔206a用以与电源及接地焊锡球连接。再以阻焊剂及黑色油墨为罩幕,施以电镀制程,依序镀上镍及金膜层270,其结果如图35所示。Referring to FIG. 34 , using the mask patterns 260a and 260b as masks, the exposure and development processes are performed to expose the copper foils to be connected by the solder balls. The exposed
请参见图36,将锡球以网板印刷方式形成于镀金膜层上。芯片275安置于凹陷区220,并将芯片上的接触垫以导线280连接于图案层206a上。最后,再以树脂285将芯片275及导线包覆。得到如图36所示的结构。Referring to FIG. 36 , solder balls are formed on the gold-plated film layer by screen printing. The
综上所述,该BGA基板具有单一图案层,用以焊锡球连接于导线图案。一散热层结合于基板的另一面,而散热层同时也是接地层,用以分散该BGA基板的接地导电图案所需面积,其中该BGA基板的接地焊锡球是利用填满导电胶的贯穿孔来连接散热层。或者,散热层也可以是电源图案层,用以分散该BGA基板的电源图案所需面积。To sum up, the BGA substrate has a single pattern layer for connecting solder balls to the wire pattern. A heat dissipation layer is combined on the other side of the substrate, and the heat dissipation layer is also a ground layer to disperse the area required for the ground conductive pattern of the BGA substrate, wherein the ground solder balls of the BGA substrate are sealed by through holes filled with conductive glue Connect the heat sink. Alternatively, the heat dissipation layer may also be a power supply pattern layer, which is used to disperse the required area of the power supply pattern of the BGA substrate.
再者,散热层亦可同时提供BGA基板的接地及电源图案,用以分散该BGA基板图案层的接地及电源图案所需面积,其中该BGA基板的接地焊锡球和电源焊锡球是利用填满导电胶的贯穿孔来分别连接散热层的接地及电源图案。Furthermore, the heat dissipation layer can also provide the grounding and power patterns of the BGA substrate at the same time, so as to disperse the area required for the grounding and power patterns of the BGA substrate pattern layer, wherein the grounding solder balls and power soldering balls of the BGA substrate are filled with The through-holes of the conductive glue are used to connect the grounding and power patterns of the heat dissipation layer respectively.
本发明制造球栅格阵列封装基板的方法:是先在基板上下两面各覆盖一层不粘膜,然后,对基板钻孔及切割以形成若干个贯穿孔与凹陷区,再在贯穿孔中填入导电胶。The method for manufacturing the ball grid array package substrate of the present invention is to first cover the upper and lower sides of the substrate with a layer of non-adhesive film, then drill and cut the substrate to form several through holes and depressions, and then fill the through holes Conductive plastic.
在本发明的第一实施例中,先去除基板一面的不粘膜,以贴合散热层于该面上,利用保留的不粘膜遮蔽基板表面,再形成黑色油墨于凹陷区,待去除其余一面的不粘膜后,再形成一铜箔于基板表面。利用光刻与蚀刻技术在铜箔面形成BGA图案,包含导线图案与形成焊锡球连接的图案。之后再涂布黑色油墨于散热层表面,用以绝缘,而BGA图案面则将阻焊剂覆盖于导线图案。最后进行镍、金膜电镀及网板印刷连接焊锡球,及将芯片安置于凹陷区作最后芯片,随后利用引脚与BGA图案连接,再注入树脂封住芯片与引脚等步骤。In the first embodiment of the present invention, the non-adhesive film on one side of the substrate is first removed to attach the heat dissipation layer to the surface, and the remaining non-adhesive film is used to cover the surface of the substrate, and then black ink is formed on the recessed area, and the other side is to be removed. After the non-adhesive film is formed, a copper foil is formed on the surface of the substrate. The BGA pattern is formed on the surface of the copper foil by photolithography and etching technology, including the pattern of the wire and the connection pattern of the solder ball. Afterwards, black ink is applied to the surface of the heat dissipation layer for insulation, and the BGA pattern surface is covered with solder resist on the wire pattern. Finally, nickel and gold film electroplating and screen printing are performed to connect solder balls, and the chip is placed in the recessed area to make the final chip, and then the pin is connected to the BGA pattern, and then resin is injected to seal the chip and the pin.
本发明的第二实施例中,是在第一实施例的导电胶注入贯穿孔后,同时移去基板上下两面不粘膜,再将铜箔与散热层同时贴合于基板上。再将铜箔以光刻及蚀刻技术形成BGA图案,然后,在BGA图案面上贴上一护膜,再形成黑色油墨于凹陷区后除去护膜。以后步骤如第一实施例中所述。In the second embodiment of the present invention, after the conductive glue of the first embodiment is injected into the through holes, the non-adhesive films on the upper and lower sides of the substrate are removed simultaneously, and then the copper foil and the heat dissipation layer are attached to the substrate at the same time. The copper foil is then formed into a BGA pattern by photolithography and etching techniques, and then a protective film is pasted on the surface of the BGA pattern, and then black ink is formed on the recessed area to remove the protective film. Subsequent steps are as described in the first embodiment.
而制造同时具有提供接地及电源图案的散热层的制造球栅格阵列封装基板的方法步骤,亦即本发明的第三实施例,是对包含一铜箔面的基板的上下两面各覆盖一层不粘膜,之后,对基板钻孔形成若干个贯穿孔及切割基板以形成凹陷区。再填入导电胶于贯穿孔中,利用不粘膜防止导电胶与基板的粘附。待除去不粘膜后,将散热层粘贴于基板背面。再形成护膜于基板正反表面,再形成黑色油墨于凹陷区。接着,在去除其余护膜后,利用光刻与蚀刻技术在铜箔面形成BGA图案,包含导线图案,与形成焊锡球连接的图案。并且在散热层上形成接地图案与导电图案。然后再涂布黑色油墨于散热层表面,用以绝缘,而BGA图案面则将阻焊剂覆盖于导线图案。最后进行镍、金膜电镀及网板印刷连接焊锡球,将芯片安置于凹陷区作最后芯片,利用引脚与BGA图案连接,再注入树脂封住芯片与引脚等步骤。And the method steps of manufacturing a ball grid array package substrate with a heat dissipation layer providing grounding and power supply patterns at the same time, that is, the third embodiment of the present invention, is to cover the upper and lower sides of the substrate including a copper foil surface with a layer After that, the substrate is drilled to form a plurality of through holes and the substrate is cut to form recessed areas. Then fill the conductive glue into the through hole, and use the non-stick film to prevent the conductive glue from adhering to the substrate. After removing the non-adhesive film, paste the heat dissipation layer on the back of the substrate. Then form a protective film on the front and back surfaces of the substrate, and then form black ink on the recessed area. Next, after removing the rest of the protective film, use photolithography and etching techniques to form BGA patterns on the copper foil surface, including wire patterns, and patterns connected to solder balls. And a ground pattern and a conductive pattern are formed on the heat dissipation layer. Then apply black ink on the surface of the heat dissipation layer for insulation, and the BGA pattern surface covers the wire pattern with solder resist. Finally, nickel and gold film electroplating and screen printing are performed to connect solder balls, the chip is placed in the recessed area as the final chip, the pin is connected to the BGA pattern, and resin is injected to seal the chip and the pin.
Claims (10)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN 02101667 CN1183588C (en) | 2002-01-15 | 2002-01-15 | Ball grid array package substrate and manufacturing method thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN 02101667 CN1183588C (en) | 2002-01-15 | 2002-01-15 | Ball grid array package substrate and manufacturing method thereof |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1359150A CN1359150A (en) | 2002-07-17 |
CN1183588C true CN1183588C (en) | 2005-01-05 |
Family
ID=4739593
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN 02101667 Expired - Lifetime CN1183588C (en) | 2002-01-15 | 2002-01-15 | Ball grid array package substrate and manufacturing method thereof |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN1183588C (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN100481420C (en) * | 2005-09-08 | 2009-04-22 | 南茂科技股份有限公司 | Stacked chip packaging structure, chip packaging body and manufacturing method thereof |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN100350821C (en) * | 2004-06-08 | 2007-11-21 | 威盛电子股份有限公司 | Signal transmission device with through holes and solder balls |
CN100350819C (en) * | 2005-06-13 | 2007-11-21 | 威盛电子股份有限公司 | Ball Grid Array Package Substrate Structure |
CN101449373B (en) * | 2006-05-26 | 2010-09-22 | 株式会社村田制作所 | Semiconductor device, electronic parts module, and method for manufacturing the semiconductor device |
EP2881978A1 (en) * | 2013-12-06 | 2015-06-10 | Ka Wa Cheung | System and method for manfacturing a fabricated carrier |
US9786518B2 (en) * | 2013-12-06 | 2017-10-10 | Enablink Technologies Limited | System and method for manufacturing a cavity down fabricated carrier |
US9735032B2 (en) * | 2013-12-06 | 2017-08-15 | Enablink Technologies Limited | System and method for manufacturing a fabricated carrier |
CN110312348B (en) * | 2019-08-07 | 2024-05-24 | 深圳市炫鼎光电科技有限公司 | Three-point type flip constant current driving chip and LED lamp |
CN118588651A (en) * | 2024-06-27 | 2024-09-03 | 睿思微系统(烟台)有限公司 | Chip heat dissipation packaging structure and production method thereof, and chip packaging module |
-
2002
- 2002-01-15 CN CN 02101667 patent/CN1183588C/en not_active Expired - Lifetime
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN100481420C (en) * | 2005-09-08 | 2009-04-22 | 南茂科技股份有限公司 | Stacked chip packaging structure, chip packaging body and manufacturing method thereof |
Also Published As
Publication number | Publication date |
---|---|
CN1359150A (en) | 2002-07-17 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN1099711C (en) | Semiconductor device and manufacturing method thereof | |
CN1146040C (en) | Substrate for semiconductor device, method of manufacturing the same, semiconductor device, card type module, and information storage device | |
CN1235275C (en) | Semiconductor module and method for mfg. semiconductor module | |
CN1264923A (en) | Semiconductor device and its mfg. method | |
CN1525544A (en) | Package substrate manufactured using electrolytic leadless plating process, and method for manufacturing the same | |
CN1352804A (en) | High-density electronic package and method for making same | |
CN1405867A (en) | Semiconductor chip, semiconductor device and manufacture method thereof | |
JP2004193549A (en) | Package substrate plated without plated lead-in wire and its manufacturing method | |
CN1320846C (en) | Circuit board and its manufacturing method | |
CN1183588C (en) | Ball grid array package substrate and manufacturing method thereof | |
CN1638072A (en) | Stress relaxation electronic part, stress relaxation wiring board, and stress relaxation electronic part mounted body | |
TWI429043B (en) | Circuit board structure, packaging structure and method for making the same | |
CN1301542C (en) | Semiconductor wafer, semiconductor device and its producing method, circuit base board and electronic machine | |
CN1230897C (en) | Semiconductor package structure and manufacturing method thereof | |
CN1210789C (en) | Semiconductor package element with heat dissipation structure | |
JP2005268453A (en) | Circuit device and manufacturing method thereof | |
CN1627489A (en) | Semiconductor chip carrier substrate and manufacturing method thereof | |
CN1416169A (en) | Resin sealed semiconductor device | |
CN1705099A (en) | Semiconductor device | |
CN1700459A (en) | Semiconductor chip package | |
CN111863737B (en) | Embedded device packaging substrate and manufacturing method thereof | |
CN1567577A (en) | Semiconductor package with high heat dissipation performance and manufacturing method thereof | |
CN1441487A (en) | Wiring base board and its producing method, electronic parts and electronic instrument | |
CN1591805A (en) | Method for mfg. heat reinforced ball grid array IC packaging substrate and packaging substrate | |
CN2706862Y (en) | chip-in-package structure |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C06 | Publication | ||
PB01 | Publication | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
CX01 | Expiry of patent term | ||
CX01 | Expiry of patent term |
Granted publication date: 20050105 |