CN118352397B - SiC MOS with sloped J-FET region and method of making - Google Patents

Abstract

The invention relates to a SiC MOS with an inclined J-FET region and a preparation method thereof; the SiC MOS comprises a substrate, an N-drift region, a Pbody region and an N+ region; the N-drift region is arranged on the first surface of the substrate, the Pbody region is arranged above the N-drift region and arranged on two sides, and a J-FET region is formed between the Pbody regions on two sides; the width of the Pbody area on both sides is gradually increased in the direction away from the substrate, the side of the Pbody area for forming the J-FET area is inclined or stepped, and the N+ area is positioned above and contacted with the Pbody area; according to the invention, the sides of the Pbody region and the P+ region form inclined planes through multiple ion implantation, the J-FET region is provided with the inclined sides, the width of the J-FET region is not changed when the dimension of a primitive cell is reduced, and the resistance of the J-FET region is not changed; the overall on-resistance is controlled to be reduced by the reduction of the resistance of the drift region, so that the on-loss of the device is reduced.

Description

SiC MOS with inclined J-FET region and preparation method thereof

Technical Field

The present invention relates to the field of semiconductor technology, and in particular to a SiC MOS with an inclined J-FET region and a preparation method thereof.

Background Art

As a third-generation semiconductor material, silicon carbide has the characteristics of wide band gap and high breakdown field strength, which makes silicon carbide devices have higher voltage resistance than silicon devices of the same power level. It also has the advantages of high input impedance and fast switching speed. It can be used at higher operating frequencies and has better high-temperature stability.

The resistance between the drain and source of SiC MOS in the on state is called the on-resistance, which directly affects the power consumption and temperature of the device. The smaller the on-resistance, the smaller the power loss of the device when it is working. Therefore, reducing the on-resistance is a hot topic in the research and development of power devices. In the existing technology, the on-resistance is controlled by shrinking the size of the primitive cell, but the effect is not significant.

Summary of the invention

To this end, the technical problem to be solved by the present invention is to overcome the technical difficulty of large power loss caused by high on-resistance of silicon carbide devices in the prior art, and to provide a SiC MOS with an inclined J-FET region and a preparation method, which can reduce the resistance of the drift region without increasing the resistance of the J-FET region, thereby controlling the on-resistance of the device.

In a first aspect, in order to solve the above technical problems, the present invention provides a SiCMOS with a tilted J-FET region, which comprises:

a substrate having a first surface;

An N-drift region, wherein the N-drift region is disposed on the first surface of the substrate;

Pbody regions, the Pbody regions are located above the N-drift region and are respectively arranged on both sides, and a J-FET region is formed between the Pbody regions on both sides; the widths of the Pbody regions on both sides increase in a direction away from the substrate, and the sides of the Pbody regions used to form the J-FET region are inclined or stepped;

An N+ region is located above the Pbody region, and at least a portion of a surface of the N+ region is in contact with the Pbody region.

In one embodiment of the present invention, a P+ region is further included. The P+ region is formed inside the Pbody region and is located on a side of the Pbody region away from the J-FET region. The P+ region contacts a portion of the N+ region.

In one embodiment of the present invention, a source is further included. The source is disposed on both sides and is located above the P+ region. A side of the source facing the P+ region contacts the P+ region and the N+ region.

In one embodiment of the present invention, it also includes a gate, a gate dielectric layer and a gate oxide layer; the gate oxide layer is deposited in a trench, the trench is located between the Pbody regions on both sides and extends downward from the N+ region, the gate is located in the gate oxide layer, and the gate dielectric layer is formed above the gate and the N+ region.

In one embodiment of the present invention, a drain is further included, and the drain is located on a second surface of the substrate, and the second surface is arranged opposite to the first surface.

In one embodiment of the present invention, the substrate, the N-drift region, the Pbody region and the N+ region are all made of SiC material.

In a second aspect, the present invention further provides a method for preparing a SiC MOS having a tilted J-FET region, which is used to prepare the SiC MOS having a tilted J-FET region described in any of the above embodiments, and the preparation method comprises the following steps:

S1, epitaxially growing an epitaxial layer on a first surface of a substrate, and etching the epitaxial layer to form an N-drift region;

S2, ion implantation is performed through a mask to obtain a Pbody region, and then ion implantation is performed to obtain a P+ region;

S3, injecting N+ ions into the N-drift region to obtain an N+ region;

S4, etching the N+ region to form a trench, and depositing a gate oxide layer and a gate in the trench;

S5, depositing a gate dielectric layer on the gate, etching the gate dielectric layer and then depositing metal to obtain a source electrode;

S6, depositing metal on the second surface of the substrate to obtain a drain.

In one embodiment of the present invention, step S2 includes,

S201, performing ion implantation through a mask to obtain a Pbody region;

S202, repeatedly performing n ion implantation on the Pbody region through a mask to obtain n+1 Pbody region regions sequentially arranged in a vertical direction, thereby forming the Pbody region;

S203, performing ion implantation on each of the Pbody regions to obtain n+1 P+ region regions arranged in sequence along a vertical direction to form the P+ region.

In one embodiment of the present invention, in step S202, 2≤n≤5.

In one embodiment of the present invention, in step S202, the implantation energy of the ion implantation is gradually reduced; the width of the Pbody region is smaller than the width of the Pbody region adjacent to and located above it.

The above technical solution of the present invention has the following beneficial effects compared with the prior art:

The SiC MOS with an inclined J-FET region and the preparation method described in the present invention form inclined surfaces on the sides of the Pbody region and the P+ region through multiple ion implantations, thereby making the J-FET region have inclined sides, while reducing the size of the original cell without changing the width of the J-FET region, and thus without changing the resistance of the J-FET region; the overall on-resistance is controlled to be reduced by decreasing the resistance of the drift region after high doping, thereby reducing the conduction loss of the device.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to make the content of the present invention more clearly understood, the present invention is further described in detail below according to specific embodiments of the present invention in conjunction with the accompanying drawings, wherein:

FIG1 is a schematic structural diagram of a SiC MOS with an inclined J-FET region in Embodiment 1 of the present invention;

FIG2 is a schematic flow chart of a method for preparing a SiC MOS having an inclined J-FET region in a second embodiment of the present invention;

FIG3 is a schematic diagram of the process of step S2 in FIG2 ;

FIG4 is a schematic diagram of the structure after S1 is completed in Embodiment 2 of the present invention;

FIG5 is a schematic diagram of a structure after S2021 is completed in the second embodiment of the present invention;

FIG6 is a schematic diagram of a structure after S2022 is completed in the second embodiment of the present invention;

FIG7 is a schematic diagram of a structure after S2023 is completed in the second embodiment of the present invention;

FIG8 is a schematic diagram of a structure after S2024 is completed in the second embodiment of the present invention;

FIG9 is a schematic diagram of a structure after S2025 is completed in the second embodiment of the present invention;

FIG10 is a schematic diagram of the structure after S203 is completed in the second embodiment of the present invention;

FIG11 is a schematic diagram of the structure after S3 is completed in Embodiment 2 of the present invention;

12 is a schematic diagram of the structure of the gate oxide layer after being deposited in S4 in the second embodiment of the present invention;

FIG13 is a schematic diagram of the structure after S4 is completed in the second embodiment of the present invention;

14 is a schematic diagram of the structure after the gate dielectric layer is deposited in S5 in the second embodiment of the present invention;

15 is a schematic diagram of the structure after etching the gate dielectric layer in S5 in the second embodiment of the present invention;

FIG16 is a schematic diagram of the structure after S5 is completed in the second embodiment of the present invention;

FIG. 17 is a schematic diagram of the structure after S6 is completed in the second embodiment of the present invention.

Explanation of the reference numerals in the specification: 1. substrate; 2. N-drift region; 3. Pbody region; 31. first Pbody region; 32. second Pbody region; 33. third Pbody region; 34. fourth Pbody region; 35. fifth Pbody region; 4. P+ region; 41. first P+ region; 42. second P+ region; 43. third P+ region; 44. fourth P+ region; 45. fifth P+ region; 5. N+ region; 61. gate oxide layer; 62. gate; 7. gate dielectric layer; 8. source; 9. drain.

DETAILED DESCRIPTION

The present invention is further described below in conjunction with the accompanying drawings and specific embodiments so that those skilled in the art can better understand the present invention and implement it, but the embodiments are not intended to limit the present invention.

Embodiment 1

The on-resistance of an existing SiC MOSFET usually includes substrate resistance, N-drift region resistance, J-FET region resistance, Pbody region resistance and N+ region resistance; among which, the J-FET region resistance and the N-drift region resistance have a greater influence on the on-resistance; the existing SiC MOSFET structure is ion-implanted from a vertical direction, and the sides of its Pbody region and P+ region are parallel to the gate trench structure. After the implantation, the Pbody region and the P+ region are symmetrically square structures on both sides of the trench. On this basis, some existing technologies control the on-resistance by shrinking the pitch size; the inventors of this case have found that although the current density increases after the pitch size is reduced, the doping concentration of the N-drift region increases accordingly, and the drift region resistance decreases; however, due to the shrinkage of the J-FET region, the resistance of the J-FET region will also increase, compensating for the reduced resistance of the drift region, and the solution of shrinking the pitch size does not significantly improve the on-resistance of the device.

Accordingly, referring to FIG. 1 , a first embodiment of the present invention provides a SiC MOS with an inclined J-FET region, wherein multiple ion implantations are performed to form slopes on the sides of the Pbody region and the P+ region, thereby allowing the J-FET region to have inclined sides. Compared with a structure parallel to the trench, the resistance of the J-FET region will not be increased while the size of the unit cell is shrunk, and the resistance of the drift region can be reduced, thereby reducing the on-resistance of the overall device and reducing the power loss of the device during operation.

Specifically, as shown in Fig. 1, the SiC MOS includes a substrate 1, an N-drift region 2, a Pbody region 3, a P+ region 4 and an N+ region 5; and also includes three electrodes for realizing electrical connection, namely, a gate 62, a source 8 and a drain 9. The substrate 1, the N-drift region 2, the Pbody region 3, the P+ region 4 and the N+ region 5 are all set to SiC material.

Furthermore, the substrate 1 has a first surface and a second surface that are oppositely arranged, the N-drift region 2 is arranged on the first surface of the substrate 1 , and the Pbody region 3 , the P+ region 4 and the N+ region 5 are all located above the N-drift region 2 .

Further, as shown in FIG. 1 , the Pbody region 3 is symmetrically arranged on both sides, the P+ region 4 is formed inside the Pbody region 3 and is located on the side of the Pbody region 3 away from the axis; the P+ region 4 is a body diode P region, which is used to improve the ohmic contact; it should be noted that the widths of the two groups of the Pbody regions 3 increase in the direction away from the substrate 1, and accordingly, the widths of the P+ regions 4 on both sides also increase in the direction away from the substrate 1; the sides of the Pbody region 3 and the P+ region 4 close to the axis direction are set as steps shaped or inclined structure, a J-FET region is formed between the Pbody regions 3 on both sides; the factors affecting the resistance of the J-FET in the variable resistance region mainly include doping concentration, channel width, channel length and material type, etc. In the prior art, when the size of the primitive cell is shrunk, the channel width is correspondingly reduced, so that the resistance value of the variable resistor is increased; in the first embodiment of the present invention, since the J-FET region is set as a trapezoidal structure with inclined sides, compared with the structure parallel to the groove, when the size of the primitive cell is reduced, the change in the channel width is smaller, and the resistance increase of the J-FET region can be avoided; and the drift region of the SiC MOS described in the first embodiment has a higher doping concentration, so the on-resistance is smaller.

Specifically, as shown in Figure 1, the N+ region 5 is located above the Pbody region 3, and at least a portion of the surface of the N+ region 5 on one side facing the Pbody region 3 is in contact with the Pbody region 3 to form an inversion layer conductive channel; the surface of the N+ region 5 on one side facing the Pbody region 3 is in contact with the P+ region 4 in an area outside the inversion channel.

Specifically, as shown in Figure 1, the gate 62 is deposited on the gate oxide layer 61, and the gate oxide layer 61 is deposited in the trench, and the trench is located between the Pbody regions 3 on both sides and extends downward from the N+ region 5; it also includes a gate dielectric layer 7, and the gate dielectric layer 7 is formed above the gate 62 and the N+ region 5; the source 8 is set on both sides of the gate dielectric layer 7, and the source 8 is located above the P+ region 4, and at least a portion of the surface of the source 8 on one side facing the P+ region 4 contacts the N+ region 5 to form electrical conduction.

Next, the drain 9 is located on the second surface of the substrate 1, and the second surface is arranged opposite to the first surface; when the SiC MOS is working, the drain 9 and the gate 62 are simultaneously connected to a positive voltage, and the current is conducted from the drain 9 to the channel where the N+ region 5 contacts the Pbody region 3, and then to the source 8 for operation.

Embodiment 2

2 to 17 , a second embodiment of the present invention provides a method for preparing a SiC MOS having an inclined J-FET region, which is used to prepare the SiC MOS having an inclined J-FET region described in the first embodiment. The method comprises the following steps:

S1, as shown in FIG. 4 , epitaxially growing an epitaxial layer on a first surface of a substrate 1, and etching the epitaxial layer to form an N-drift region 2;

S2, ion implantation is performed through a mask to obtain a Pbody region 3, and then ion implantation is performed to obtain a P+ region 4;

Specifically, step S2 includes:

S201, performing ion implantation through a mask to obtain a Pbody region;

S202, repeatedly performing n ion implantation on the Pbody region through a mask to obtain n+1 Pbody region regions sequentially arranged in a vertical direction, forming the Pbody region 3;

S203 , performing ion implantation on each of the Pbody regions to obtain n+1 P+ region regions arranged in sequence along a vertical direction, forming the P+ region 4 .

In the preferred implementation manner of the second embodiment, in order to enable n+1 Pbody regions to be arranged in sequence to form the inclined side of the J-FET region, in step S202, 2≤n≤5; when the number of ion implantation times is too low, the number of Pbody regions and P+ regions obtained is small, and it is difficult to form an implantation width gradient; when the number of ion implantation times is large, it is difficult to control the preparation accuracy and preparation efficiency; preferably, n is set to 4; when n is set to 4, step S202 specifically includes:

S2021, as shown in FIG. 5, ion implantation is performed through a mask to form a first Pbody region 31;

S2022, as shown in FIG. 6, ion implantation is performed above the first Pbody region 31 through a mask to form a second Pbody region 32;

S2023, as shown in FIG. 7, ion implantation is performed above the second Pbody region 32 through a mask to form a third Pbody region 33;

S2024, as shown in FIG. 8 , ion implantation is performed through a mask on the third Pbody region 33 to form a fourth Pbody region 34;

S2025, as shown in FIG. 9, ion implantation is performed above the fourth Pbody region 34 through a mask to form a fifth Pbody region 35;

The energy of ion implantation in steps S2021 to S2025 is gradually reduced so as to form a width gradient of each Pbody region; the width of the Pbody region is smaller than the width of the Pbody region adjacent to and located above it, specifically, the width of the first Pbody region 31 is smaller than the width of the second Pbody region 32, the width of the second Pbody region 32 is smaller than the width of the third Pbody region 33, the width of the third Pbody region 33 is smaller than the width of the fourth Pbody region 34, and the width of the fourth Pbody region 34 is smaller than the width of the fifth Pbody region 35;

When n is set to 4, step S203 specifically includes:

S2031, performing ion implantation through a mask along the upper portion of the first Pbody region 31 to form a first P+ region 41;

S2032, performing ion implantation through a mask along the upper portion of the second Pbody region 32 to form a second P+ region 42;

S2033, performing ion implantation through a mask along the third Pbody region 33 to form a third P+ region 43;

S2034, performing ion implantation through a mask along the upper portion of the fourth Pbody region 34 to form a fourth P+ region 44;

S2035, performing ion implantation through a mask along the upper portion of the fifth Pbody region 35 to form a fifth P+ region 45;

10 , in steps S2031 to S2035, each P+ region body forms a width gradient consistent with the Pbody region 3. Specifically, the width of the first P+ region 41 is smaller than the width of the second P+ region 42, the width of the second P+ region 42 is smaller than the width of the third P+ region 43, the width of the third P+ region 43 is smaller than the width of the fourth P+ region 44, and the width of the fourth P+ region 44 is smaller than the width of the fifth P+ region 45.

S3, as shown in FIG. 11 , N+ ions are injected into the N-drift region 2 to obtain an N+ region 5;

S4, as shown in FIG. 12 and FIG. 13, the N+ region 5 is etched to form a trench, and a gate oxide layer 61 and a gate 62 are deposited in the trench;

S5, as shown in FIGS. 14 to 16 , depositing an oxide layer as a gate dielectric layer 7 on the gate 62, etching the gate dielectric layer 7 and then depositing metal to obtain a source electrode 8;

S6, as shown in FIG. 17 , depositing metal on the second surface of the substrate 1 to obtain a drain electrode 9.

In the second embodiment of the present invention, a stepped Pbody region 3 and a P+ region 4 are formed by multiple ion implantations, and after the implantation, ion diffusion is performed to form a device structure as shown in FIG1 . While reducing the size of the unit cell, the width of the J-FET region is not changed, and thus the resistance of the J-FET region is not changed. The overall on-resistance is reduced by decreasing the resistance of the drift region after high doping, thereby reducing the conduction loss of the device.

Obviously, the above embodiments are merely examples for the purpose of clear explanation and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection of the present invention.

Claims (9)

1. A SiC MOS having an inclined J-FET region, comprising,

A substrate having a first surface;

An N-drift region disposed on the first surface of the substrate;

The Pbody region is positioned above the N-drift region and is respectively arranged at two sides, and a J-FET region is formed between the Pbody regions at two sides; the width of the Pbody region at both sides is gradually increased in a direction away from the substrate, and the side of the Pbody region used for forming the J-FET region is inclined or stepped;

an n+ region located above the Pbody region, and at least a partial region of the n+ region surface being in contact with the Pbody region;

the semiconductor device further comprises a grid electrode, a grid dielectric layer and a grid oxide layer; the gate oxide layer is deposited in the trench, the trench is positioned between the Pbody regions at two sides and extends downwards from the N+ region, the gate is positioned in the gate oxide layer, and the gate dielectric layer is formed above the gate and the N+ region.

2. The SiC MOS with sloped J-FET region of claim 1, characterized in that: and a P+ region formed inside the Pbody region and located on one side of the Pbody region away from the J-FET region, the P+ region contacting a partial region of the N+ region.

3. The SiC MOS with sloped J-FET region of claim 2, characterized in that: the source electrode is arranged on two sides and is positioned above the P+ region; one surface of the source electrode facing the P+ region contacts the P+ region and the N+ region.

4. The SiC MOS with sloped J-FET region of claim 1, characterized in that: the semiconductor device further comprises a drain electrode, wherein the drain electrode is positioned on a second surface of the substrate, and the second surface is opposite to the first surface.

5. The SiC MOS with sloped J-FET region of any one of claims 1 to 4, characterized in that: the substrate, the N-drift region, the Pbody region, and the N+ region are all provided as SiC materials.

6. A method for producing a SiC MOS having an inclined J-FET region, characterized by being used for producing a SiC MOS having an inclined J-FET region according to any one of claims 1 to 5, comprising the steps of:

s1, obtaining an epitaxial layer on a first surface of a substrate by epitaxy, and etching the epitaxial layer to form an N-drift region;

s2, performing ion implantation through a mask plate to obtain a Pbody region, and performing ion implantation to obtain a P+ region;

s3, injecting N+ ions into the N-drift region to obtain an N+ region;

s4, etching the N+ region to form a groove, and depositing a gate oxide layer and a gate in the groove;

S5, depositing a gate dielectric layer above the gate, etching the gate dielectric layer, and depositing metal to obtain a source electrode;

And S6, depositing metal on the second surface of the substrate to obtain a drain electrode.

7. The method of manufacturing a SiC MOS having an inclined J-FET region of claim 6, characterized in that: the step S2 includes the steps of,

S201, performing ion implantation through a mask plate to obtain a Pbody distinguishing body;

s202, repeatedly performing n times of ion implantation on the upper part of the Pbody distinguishing body through a mask plate to obtain n+1 Pbody distinguishing bodies which are sequentially arranged along the vertical direction, and forming the Pbody area;

S203, performing ion implantation on each Pbody distinguishing body to obtain n+1 P+ distinguishing bodies which are sequentially arranged along the vertical direction, so as to form the P+ region.

8. The method of manufacturing a SiC MOS having an inclined J-FET region of claim 7, characterized in that: in step S202, n is more than or equal to 2 and less than or equal to 5.

9. The method of manufacturing a SiC MOS having an inclined J-FET region of claim 7, characterized in that: in step S202, the implantation energy of ion implantation is successively reduced; the width of the Pbody distinction pieces is smaller than the width of the Pbody distinction pieces adjacent to and above the Pbody distinction pieces.