CN118349286A - Processor, instruction processing device, electronic equipment and instruction processing method - Google Patents

Abstract

Disclosed are a processor, an instruction processing device, an electronic device, and an instruction processing method, which belong to the field of computers. The processor includes: an instruction fetch unit, an instruction parsing unit, a DQ instruction execution unit, and a CA instruction execution unit; wherein the instruction fetch unit, the instruction parsing unit, and the first target unit form a first instruction pipeline; the instruction fetch unit, the instruction parsing unit, and the second target unit form a second instruction pipeline; when the target condition is met, the first instruction pipeline and the second instruction pipeline are executed in parallel, wherein the first target unit includes a DQ instruction execution unit, and the second target unit includes the CA instruction execution unit.

Description

Processor, instruction processing device, electronic device and instruction processing method

Technical Field

The present application belongs to the field of computers, and specifically relates to a processor, an instruction processing device, an electronic device, and an instruction processing method.

Background technique

In order to meet the requirements of data storage, flash memory technology came into being. As the bandwidth requirements of flash memory interface become higher and higher, the data transmission rate of flash memory interface continues to increase, while the command/address transmission rate of flash memory interface has not changed. In the traditional flash memory interface transmission protocol (ONFi or Toggle), command/address and data are transmitted on the same set of transmission lines. As the data transmission rate increases, the proportion of command/address transmission time increases, which becomes the bottleneck of flash memory interface bandwidth. In order to solve the problem of improving flash memory interface bandwidth, new flash memory particle protocols, such as the Separate Command Address (SCA) protocol, separate command/address and data transmission and put them on two different transmission buses. Command/address is transmitted on the Command and Address (CA) bus; data is transmitted on the Data (DATA, also called DQ) bus, so that the command/address is transmitted on the CA bus while the data is transmitted on the DQ bus.

In the process of processing instructions of flash memory chip, the related technology usually implements the SCA protocol through a dedicated state machine, which has the problem of low efficiency in processing instructions.

Summary of the invention

The embodiments of the present application provide a processor, an instruction processing device, an electronic device, and an instruction processing method, which can solve the problem of low instruction processing efficiency caused by implementing the SCA protocol through a state machine in the related art.

In a first aspect, an embodiment of the present application provides a processor, including:

An instruction fetch unit, used to fetch a target instruction and send it to an instruction parsing unit, wherein the target instruction is an instruction adapted to the flash memory chip;

An instruction parsing unit, configured to determine an instruction type of the target instruction by parsing the target instruction, wherein the instruction type includes a command/address CA operation instruction or a data DQ operation instruction;

A DQ instruction execution unit, used for sending target data to the flash memory particle chip through the DQ bus when the instruction type is a DQ operation instruction;

A CA instruction execution unit, configured to send CA information or CA-related configuration information to the flash memory chip through a CA bus when the instruction type is a CA operation instruction;

Wherein, the instruction fetch unit, the instruction parsing unit and the first target unit form a first instruction pipeline; the instruction fetch unit, the instruction parsing unit and the second target unit form a second instruction pipeline;

When a target condition is met, the first instruction pipeline and the second instruction pipeline are executed in parallel, wherein the first target unit includes the DQ instruction execution unit, and the second target unit includes the CA instruction execution unit.

In a second aspect, an embodiment of the present application provides an instruction processing device, comprising a flash memory particle chip and the processor described in the first aspect, wherein the processor is connected to the flash memory particle chip via a CA bus, and the processor is connected to the flash memory particle chip via a DQ bus.

In a third aspect, an embodiment of the present application provides a storage device, wherein the storage device comprises the apparatus according to the second aspect.

In a fourth aspect, an embodiment of the present application provides an electronic device, comprising the storage device according to the third aspect.

In a fifth aspect, an embodiment of the present application provides an instruction processing method, which is executed by a processor and includes:

Get target instructions;

Parsing the target instruction and determining the instruction type of the target instruction, where the instruction type includes a command/address CA operation instruction or a data DQ operation instruction;

When the instruction type is a DQ operation instruction, sending target data to the flash memory particle chip through the DQ bus;

When the instruction type is a CA operation instruction, CA information or configuration information related to CA is sent to the flash memory chip through the CA bus;

When the DQ operation instruction needs to be written back, first information is obtained from the flash memory chip through the DQ bus, and written into the data storage space in the processor;

When the CA operation instruction needs to be written back, the second information is obtained from the flash memory chip through the CA bus and written into the data storage space in the processor.

In a sixth aspect, an embodiment of the present application provides a storage medium, which stores a program, and when the program is executed, implements the method described in the fifth aspect.

In an embodiment of the present application, a processor is provided, comprising: an instruction fetch unit, for fetching a target instruction and sending it to an instruction parsing unit, wherein the target instruction is an instruction adapted to a flash memory particle chip; an instruction parsing unit, for determining the instruction type of the target instruction by parsing the target instruction, wherein the instruction type includes a CA operation instruction or a DQ operation instruction; a DQ instruction execution unit, for sending target data to the flash memory particle chip through a DQ bus when the instruction type is a DQ operation instruction; a CA instruction execution unit, for sending CA information or configuration information related to CA to the flash memory particle chip through a CA bus when the instruction type is a CA operation instruction; wherein the instruction fetch unit, the instruction parsing unit and the first target unit form a first instruction pipeline; the instruction fetch unit, the instruction parsing unit and the second target unit form a second instruction pipeline; when the target condition is met, the first instruction pipeline and the second instruction pipeline are executed in parallel, wherein the first target unit includes the DQ instruction execution unit and the second target unit includes the CA instruction execution unit. In this way, the SCA protocol can be implemented in the process of processing the instructions of the flash memory particle chip by means of a processor, thereby improving the processing speed of the target instruction. When the target conditions are met, the processor can flexibly process instructions in parallel through the first instruction pipeline and the second instruction pipeline, further improving the efficiency of instruction processing. In addition, on the processor provided in the embodiment of the present application, the first instruction pipeline and the second instruction pipeline share the instruction fetch unit and the instruction parsing unit, which can reduce the number of components and hardware area on the processor to a certain extent.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

FIG1-1 is a structural block diagram of a processor provided in an embodiment of the present application;

FIG1-2 is a structural block diagram of another processor provided in an embodiment of the present application;

FIG2 is an architecture diagram of a target format provided in an embodiment of the present application;

FIG3 is a structural block diagram of an instruction processing device provided in an embodiment of the present application;

FIG4 is a flow chart of an instruction processing method provided in an embodiment of the present application;

FIG5 is a diagram of an external environment architecture of a processor provided in an embodiment of the present application;

FIG6 is an architecture diagram of a processor provided in an embodiment of the present application;

FIG. 7 is an architectural diagram of a target instruction processing process provided in an embodiment of the present application.

Detailed ways

In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

The terms "first", "second", etc. in the specification and claims of this application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, "and/or" in the specification and claims represents at least one of the connected objects, and the character "/" generally indicates that the objects associated with each other are in an "or" relationship.

Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

As described in the background art, in the process of processing instructions of flash memory chip, the related art usually implements the SCA protocol through a dedicated state machine, which has the problem of low efficiency in processing instructions.

In an embodiment of the present application, a processor is provided, comprising: an instruction fetch unit, an instruction parsing unit, a DQ instruction execution unit and a CA instruction execution unit; wherein the instruction fetch unit, the instruction parsing unit and the first target unit form a first instruction pipeline; the instruction fetch unit, the instruction parsing unit and the second target unit form a second instruction pipeline; when the target condition is met, the first instruction pipeline and the second instruction pipeline are executed in parallel, wherein the first target unit includes a DQ instruction execution unit and the second target unit includes a CA instruction execution unit. In this way, the SCA protocol can be implemented in the process of processing the instructions of the flash particle chip by means of a processor, thereby improving the processing speed of the target instructions. When the target condition is met, the processor can flexibly process instructions in parallel through the first instruction pipeline and the second instruction pipeline, further improving the efficiency of instruction processing. In addition, on the processor provided in the embodiment of the present application, the first instruction pipeline and the second instruction pipeline share the instruction fetch unit and the instruction parsing unit, which can reduce the number of components and hardware area on the processor to a certain extent.

In addition, in the related art, instructions are usually processed through a scalar pipeline design (an instruction pipeline) before being transmitted through two transmission buses. The processor provided in the embodiment of the present application can implement a superscalar design through a first instruction pipeline and/or a second instruction pipeline, thereby completing the processing of target instructions more flexibly and efficiently.

In the related art, when considering the instructions for adapting to a variety of flash memory particle chips, a large number of hardware circuits are often pre-designed. Even so, it is still not compatible with new instructions that have not been designed in advance, and there will still be problems of poor compatibility, large area and cost. However, in the embodiment of the present application, the processor has an instruction storage space for storing various instructions adapted to the flash memory particle chip, and the instruction storage space is used to store the target instruction. In this way, the processor can be adapted to different flash memory particle chips of different storage manufacturers by modifying the target instruction in the instruction storage space in the processor, so that the processor can be adapted to flash memory particle chips of more manufacturers. Compared with the related art, the processor provided in the embodiment of the present application has better compatibility and adaptability, and can also reduce costs.

In the embodiment of the present application, the target instruction is an instruction that conforms to the target format; wherein the target format includes: a bus type field, a data field, a write-back indication field, a length field, a waveform indication field, and a lock field. Through the target format, the processor can better control the execution behavior between the CA bus and the DQ bus (the waveform between the interface of the CA bus and/or the DQ bus, that is, the signal behavior of the target instruction), data, parallel or exclusive operations, etc.

In the embodiment of the present application, the processor can further realize simultaneous control of the CA bus and/or the DQ bus by simultaneously controlling the first instruction pipeline and/or the second instruction pipeline. And because the processor controls the CA bus and/or the DQ bus simultaneously, the behavior of any transmission bus can be reasonably arranged based on the behavior of the other transmission bus, making it easier to control the mutually exclusive relationship between the instruction operations of the two transmission buses.

It should be understood that the discussion of the same noun or situation in the embodiments of the present application can be referenced before and after. That is to say, the discussion of a certain noun or situation in one embodiment can also be applied to the description of the noun or situation in other embodiments, as long as there is no logical contradiction.

The method provided in the embodiment of the present application is described in detail below through specific embodiments and their application scenarios in conjunction with the accompanying drawings.

In an embodiment of the present application, the flash memory particle chip can be a Not And flash (NAND flash for short), and the processor provided in the embodiment of the present application can be used to control the behavior of the flash memory particle chip, such as implementing the read and write operations of the application layer on the flash memory particle chip, or implementing the configuration of the flash memory particle chip and other operations.

FIG1-1 is a block diagram of a processor provided in an embodiment of the present application. As shown in FIG1-1, a processor 100 provided in an embodiment of the present application includes:

The instruction fetching unit 110 is used to fetch a target instruction and send it to the instruction parsing unit. The target instruction is an instruction adapted to the flash memory chip.

The instruction parsing unit 120 is used to determine the instruction type of the target instruction by parsing the target instruction, where the instruction type includes a CA operation instruction or a DQ operation instruction;

A DQ instruction execution unit 130, configured to send target data to the flash memory chip through a DQ bus when the instruction type is a DQ operation instruction;

A CA instruction execution unit 140, configured to send CA information or CA-related configuration information to the flash memory chip through a CA bus when the instruction type is a CA operation instruction;

Wherein, the instruction fetch unit, the instruction parsing unit and the first target unit form a first instruction pipeline; the instruction fetch unit, the instruction parsing unit and the second target unit form a second instruction pipeline;

When a target condition is met, the first instruction pipeline and the second instruction pipeline are executed in parallel, wherein the first target unit includes the DQ instruction execution unit, and the second target unit includes the CA instruction execution unit.

In the embodiment of the present application, the processor 100 may be a hardware device, and each unit in the processor 100 may also have a corresponding hardware module. In the processor provided in the embodiment of the present application, the hardware modules corresponding to each unit may be connected by a circuit so that data can be transmitted between the units.

In the embodiment of the present application, for the same operation, such as "write operation", different flash memory chip manufacturers have different instruction expressions. The target instruction in the embodiment of the present application can be any operation for the flash memory chip, and can be adapted to the flash memory chip, such as read and write operations for the flash memory chip, or self-configuration operation instructions for the flash memory chip. The instruction fetch unit 110 in the processor 100 can obtain the target instruction from outside the processor 100, for example, it can obtain the target instruction from the application layer; the instruction fetch unit 110 can also obtain the target instruction from inside the processor 100, for example, it can obtain the target instruction from the place where the instructions are stored inside the processor 100 (that is, the instruction storage space mentioned later). The embodiment of the present application does not specifically limit how the instruction fetch unit 110 obtains the target instruction adapted to the flash memory chip.

In the embodiment of the present application, the target instruction may be one instruction or multiple instructions, and the embodiment of the present application does not impose a specific limit on the number of target instructions. Further, the target instruction may be one instruction of a flash memory particle chip, or multiple instructions of a flash memory particle chip, or multiple instructions of multiple flash memory particle chips, and the embodiment of the present application does not impose a specific limit on the correspondence between the number of target instructions and the number of flash memory particle chips.

In an embodiment of the present application, the processor provided in the embodiment of the present application can process operation instructions for the flash memory particle chip based on the SCA protocol, and classify the operation instructions for the flash memory particle chip into CA operation instructions and DQ operation instructions. Specifically, the instruction parsing unit 120 parses and processes the target instruction to determine the instruction type of the target instruction, and the instruction type includes a CA operation instruction or a DQ operation instruction. The CA operation instruction can be an operation instruction related to the configuration of the flash memory particle chip itself, such as an instruction to read the state of the flash memory particle chip, and an instruction to modify the state of the register on the flash memory particle chip. The DQ operation instruction can be an instruction related to the data information stored on the flash memory particle chip, such as a read and write operation instruction for the flash memory particle chip.

In an embodiment of the present application, the target instruction may include a field that directly indicates the instruction type, and the instruction parsing unit 120 parses the target instruction and determines the instruction type of the target instruction according to the field that directly indicates the instruction type included in the target instruction. The instruction parsing unit 120 may also parse the target instruction and determine the instruction type of the target instruction based on the data ratio in the target instruction. The embodiment of the present application does not specifically limit how the instruction parsing unit 120 determines the instruction type group of the target instruction.

As shown in FIG. 1-1 provided in the embodiment of the present application, after the instruction parsing unit 120 determines the instruction type of the target instruction, the target instruction can be executed by different instruction execution units based on the instruction type. The processor 100 can control the flash memory particle chip by controlling the waveform behavior on the input/output (I/O) interface on the flash memory particle chip.

In the embodiment of the present application, when the instruction type of the target instruction is a DQ operation instruction, the DQ instruction execution unit 130 converts the operation content of the target instruction into the waveform behavior of the I/O interface on the processor, thereby converting the digital signal of the target instruction into an analog signal, and transmits the waveform behavior of the I/O interface on the processor 100 to the I/O interface on the flash memory particle chip through the DQ bus, so that the flash memory particle chip obtains the target data based on the waveform behavior of the I/O interface on the flash memory particle chip.

In the embodiment of the present application, the target data may be any data that is intended to be stored on the flash memory chip. The target data may come from the target instruction itself, or may be obtained from the processor 100 by the DQ instruction execution unit 130 based on the instruction of the target instruction. For example, a storage space for storing data (such as the data storage space described below) is provided inside the processor 100, and the target data may be obtained from the storage space for storing data inside the processor 100 by the DQ instruction execution unit 130 based on the instruction of the target instruction.

Correspondingly, when the instruction type of the target instruction is a CA operation instruction, the CA instruction execution unit 140 converts the operation content of the target instruction into the waveform behavior of the I/O interface on the processor, realizes the conversion of the digital signal of the target instruction into an analog signal, and transmits the waveform behavior of the I/O interface on the processor 100 to the I/O interface on the flash memory particle chip through the CA bus, so that the flash memory particle chip obtains CA information or configuration information related to CA based on the waveform behavior of the I/O interface on the flash memory particle chip, and completes CA-related commands.

In an embodiment of the present application, the CA information may be configuration information related to the flash memory particle chip itself, such as the modified register information of the flash memory particle chip. After the flash memory particle chip obtains the CA information or configuration information related to CA through the waveform behavior of the I/O interface, the flash memory particle chip performs operations corresponding to the CA instructions, such as modifying the register information.

In an embodiment of the present application, the first target unit (DQ instruction execution unit 130) on the first instruction pipeline is associated with the DQ bus. Correspondingly, the second target unit of the second instruction pipeline is associated with the CA bus. The target condition can characterize whether the DQ bus and the CA bus can process the target instruction in parallel. Specifically, the target condition can be that the first instruction pipeline and the second instruction pipeline process the target instructions of different flash memory particle chips respectively, or the target condition can be that the instruction currently processed by the first instruction pipeline does not have an exclusive relationship with the instruction currently processed by the second instruction pipeline, then the first instruction pipeline can be executed in parallel with the second instruction pipeline to improve the efficiency of processing the target instruction. In an embodiment of the present application, when the first instruction pipeline and the second instruction pipeline are executed in parallel, the target instruction on the first instruction pipeline and the target instruction on the second instruction pipeline can be instructions of different flash memory particle chips, or instructions of the same flash memory particle chip, and the embodiment of the present application does not impose specific restrictions on this.

In the embodiment of the present application, when the first instruction pipeline and the second instruction pipeline are executed in parallel, it can be indicated that any unit on the first instruction pipeline (such as the instruction fetch unit 110) can be executed in parallel with any unit on the second instruction pipeline that is different from the unit that is working on the first instruction pipeline (such as the instruction parsing unit 120 or the second target unit). For example, while the instruction fetch unit on the first instruction pipeline obtains the X target instruction, the second target unit (CA instruction execution unit 140) on the second instruction pipeline can execute the Y target instruction. In the embodiment of the present application, any letter description for the target instruction represents a different target instruction, such as the X target instruction and the Y target instruction mentioned above, the A target instruction and the B target instruction mentioned below, and so on.

In the embodiment of the present application, when the DQ instruction execution unit on the first instruction pipeline is executing the target instruction, if the instruction fetch unit and/or the instruction parsing unit are in an idle period, the instruction fetch unit and/or the instruction parsing unit can execute other instructions in parallel, and the other instructions and the target instruction can be instructions of the same flash memory particle chip, or instructions of different flash memory particle chips. For example, after the instruction fetch unit sends the target instruction A for the flash memory particle chip A to the instruction parsing unit, it can obtain the target instruction B for the flash memory particle chip A again, so that the first instruction pipeline and the second instruction pipeline become two parallel instruction pipelines for heterogeneous processing. In addition, the instruction fetch unit can not only obtain the target instruction B for the flash memory particle chip A again, but also obtain the target instruction A for the flash memory particle chip B, and the embodiment of the present application does not impose specific restrictions on this.

In the embodiment of the present application, when the target condition is met, the CA instruction execution unit on the second instruction pipeline executes the target instruction A. At the same time, the DQ instruction execution unit on the first instruction pipeline receives the target instruction B for processing, so that the first instruction pipeline and the second instruction pipeline are executed in parallel.

In an embodiment of the present application, when the target condition is not met, it may indicate that the DQ bus and the CA bus cannot process the target instructions in parallel. For example, the instruction currently processed by the first instruction pipeline (which can be regarded as the instruction corresponding to the target data currently transmitted by the DQ bus) is exclusive of the instruction currently processed by the second instruction pipeline and cannot be processed in parallel. The CA instruction execution unit in the second target unit on the second instruction pipeline may wait for the target instruction on the first instruction pipeline to be completed.

For example, in the embodiment of the present application, the CA instruction execution unit executes the C target instruction. Since the target condition is not met, the DQ instruction execution unit cannot execute the D target instruction in parallel, and the DQ instruction execution unit of the first instruction pipeline can wait until the C target instruction on the second instruction pipeline is executed before executing the D target instruction.

In the embodiment of the present application, the SCA protocol can be implemented in the process of processing the instructions of the flash memory particle chip by means of a processor to improve the processing speed of the target instructions. When the target conditions are met, the processor can implement a heterogeneous pipeline through the first instruction pipeline and the second instruction pipeline to further improve the efficiency of instruction processing. In addition, on the processor provided in the embodiment of the present application, the first instruction pipeline and the second instruction pipeline share the instruction fetch unit 110 and the instruction parsing unit 120, which can reduce the number of components and hardware area on the processor to a certain extent.

FIG1-2 is a block diagram of a processor provided in an embodiment of the present application. As shown in FIG1-2, the processor 100 provided in an embodiment of the present application also includes: a DQ write-back unit 150 and a CA write-back unit 160. The DQ write-back unit 150 is used to obtain first information from the flash memory particle chip through the DQ bus when the DQ operation instruction needs to be written back, and write the first information into the data storage space within the processor. The CA write-back unit 160 is used to obtain second information from the flash memory particle chip through the CA bus when the CA operation instruction needs to be written back, and write the second information into the data storage space within the processor. Among them, the first target unit also includes the DQ write-back unit 150, and the second target unit also includes the CA write-back unit 160.

In an embodiment of the present application, the target instruction may also include a write-back operation, which is used to write the configuration information or data information of the flash memory chip back to the processor 100 for the processor 100 to perform the next step of processing. For example, the processor 100 saves the configuration information written back by the flash memory chip, or sends the data information written back by the flash memory chip to the user. In an embodiment of the present application, if the DQ operation instruction needs to be written back, it can be executed by the DQ write-back unit 150; if the CA operation instruction needs to be written back, it can be executed by the CA write-back unit 160.

In the embodiment of the present application, when the DQ operation instruction needs to be written back, the DQ write-back unit 150 can obtain the first information from the flash memory particle chip through the DQ bus. The DQ write-back unit 150 converts the analog signal transmitted by the flash memory particle chip into a data signal of the first information through the DQ bus, thereby obtaining the first information. In the embodiment of the present application, the first information can be any data stored on the flash memory particle chip, for example, the first information can be valid data information stored by the user on the flash memory particle chip.

After the DQ write-back unit 150 obtains the first information, the first information can be written into the data storage space 170 in the processor 100. The data storage space 170 can be a space dedicated to storing data content in the processor 100, and any data in the processor can be stored in the data storage space 170. The data storage space 170 can not only be written with data information, but also can write data information out to the outside of the processor 100. For example, the outside of the processor 100 includes a transmission route and a data path dedicated to processing data, and the data storage space 170 writes data information that is not related to the processor 100 to the data path outside the processor 100. Further, in the process of the DQ instruction execution unit 130 sending target data to the flash memory particle chip through the DQ bus, the target data can come from the data storage space 170. If the data storage space 170 cannot provide the target data, the target data can also obtain data information from outside the processor 100 through the data storage space 170.

Accordingly, in the embodiment of the present application, when the CA operation instruction needs to be written back, the CA write-back unit 160 can obtain the second information from the flash memory particle chip through the CA bus. The CA write-back unit 160 converts the analog signal transmitted by the flash memory particle chip into a data signal of the second information through the CA bus, thereby obtaining the second information. In the embodiment of the present application, the second information can be configuration information related to the flash memory particle chip.

After the CA write-back unit 160 obtains the second information, the second information may be written into the data storage space 170 in the processor 100. Since the data storage space 170 includes the second information related to the CA operation instruction, during the process of the instruction parsing unit 120 parsing the target instruction, the instruction parsing unit 120 may also obtain data information from the data storage space 170, for example, obtain the register information of the modified flash memory particle chip.

In the embodiment of the present application, the write back operation of the target instruction can be implemented through the DQ write back unit and the CA write back unit, so that the target instruction for the flash memory particle chip has a wider indication range, enabling the flash memory particle chip to perform more operations.

In the embodiment of the present application, the instruction fetch unit 110, instruction parsing unit 120, DQ instruction execution unit 130 and DQ write-back unit 150 shown in FIG. 1-2 form a first instruction pipeline; the instruction fetch unit 110, instruction parsing unit 120, CA instruction execution unit 140 and CA write-back unit 160 form a second instruction pipeline. When the target condition is met, the first designated unit in the first target unit on the first instruction pipeline and the second designated unit in the second target unit on the second instruction pipeline are executed in parallel, wherein the first designated unit includes at least one of the DQ instruction execution unit 130 and the DQ write-back unit 150, and the second designated unit includes at least one of the CA instruction execution unit 140 and the CA write-back unit 160.

In an embodiment of the present application, when the target condition is met, in the first clock cycle, the CA write-back unit on the second instruction pipeline executes the E target instruction. At the same time, the DQ instruction execution unit on the first instruction pipeline executes the F target instruction, and the F target instruction also includes a write-back operation. In the second clock cycle, the CA write-back unit on the second instruction pipeline still executes the E target instruction, and the DQ write-back unit on the first instruction pipeline executes the F target instruction, thereby achieving the parallel execution of the first designated unit in the first target unit on the first instruction pipeline and the second designated unit in the second target unit on the second instruction pipeline.

In an embodiment of the present application, when the target condition is not met, during the period when the target instruction is executed by any instruction pipeline (e.g., the first instruction pipeline), another instruction pipeline (e.g., the second instruction pipeline) will not execute the instruction. For example, the DQ write-back unit of the first instruction pipeline executes the G target instruction. Since the target condition is not met, the CA instruction execution unit in the second instruction pipeline cannot execute the H target instruction. The CA instruction execution unit can execute the H target instruction after the G target instruction is executed.

In an embodiment of the present application, by executing in parallel the first designated unit in the first target unit on the first instruction pipeline and the second designated unit in the second target unit on the second instruction pipeline, the processor can process the target instruction more efficiently. At the same time, due to the limitation of the target conditions, the processor provided in the embodiment of the present application can more reasonably arrange the processing logic order of the target instruction.

In an embodiment of the present application, the processor may also have an instruction storage space for storing various instructions adapted to the flash memory particle chip, and the instruction storage space is used to store the target instruction. The instruction storage space may include the logic of the instructions adapted to the flash memory particle chip preset in advance according to the instructions of the flash memory particle chip manufacturer. For example, according to the instructions of the flash memory particle chip manufacturer, the code of the target instruction is written and assembled, and finally the target instruction corresponding to the instructions is obtained, that is, the target instruction adapted to the flash memory particle chip. The instruction storage space can store target instructions adapted to multiple flash memory particle chip manufacturers, so as to adapt to more flash memory particle chips.

In the embodiment of the present application, the instruction of the application layer can be obtained from the instruction storage space, and the corresponding target instruction can be matched, so that the instruction fetching unit (such as 110 shown in any one of Figures 1-1 or 1-2) can obtain the target instruction from the instruction storage space. In the embodiment of the present application, the instruction fetching unit can also obtain the instruction from the application layer and then match it in the instruction storage space to obtain the target instruction corresponding to the application layer instruction.

By modifying the target instructions stored in the instruction storage space of the processor, the processor can be more flexibly adapted to different flash memory chips of different storage manufacturers. Compared with the related art, the processor provided by the embodiment of the present application has better compatibility and adaptability, and can also reduce costs.

In an embodiment of the present application, the target instruction is an instruction that conforms to the target format. Figure 2 is an architectural diagram of a target format provided in an embodiment of the present application. As shown in Figure 2, the target format of the target instruction provided in an embodiment of the present application includes a bus type field, a data field, a write-back indication field, a length field, a waveform indication field, and a lock field; the bus type field (BUS_type) is used to indicate whether the bus type used by the target instruction is a CA bus or a DQ bus; the data field (Data) indicates the data content to be sent, and the data content comes from the target instruction and/or the data storage space; the write-back indication field (R/W) is used to indicate whether the target instruction has a write-back operation; the length field (Length) is used to indicate the length of the current operation; the waveform indication field (BUS_wave) is used to indicate the signal timing behavior of the target instruction; the lock field (Lock) indicates whether the target instruction is executed synchronously with the next instruction of a different bus.

In an embodiment of the present application, the instruction parsing unit of the processor can determine the instruction type of the target instruction according to the bus type field in the target format. If the bus type field indicates that the bus type used by the target instruction is a CA bus, the target instruction can be sent to the CA instruction execution unit; if the bus type field indicates that the bus type used by the target instruction is a DQ bus, the target instruction can be sent to the DQ instruction execution unit.

In an embodiment of the present application, the data field (Data) indicates the data content to be sent, and the data content may also come from the data storage space according to the indication. If there is no data content that the target instruction needs to send in the data storage space, the instruction parsing unit may obtain the target data from outside the processor (for example, the data path) through the data storage space.

In an embodiment of the present application, the write-back indication field (R/W) is used to indicate whether the target instruction has a write-back operation. If the write-back indication field (R/W) is used to indicate that the target instruction has a write-back operation, then after the instruction execution unit (DQ instruction execution unit and/or CA instruction execution unit) executes, the write-back unit (DQ write-back unit and/or CA write-back unit) obtains the information to be written back (the first information and/or the second information) from the flash memory particle chip; if the write-back indication field (R/W) is used to indicate that the target instruction does not require a write-back operation, after the instruction execution unit completes execution, the target instruction can be deemed to have been executed.

In the embodiment of the present application, the length field (Length) is used to indicate the length of the current operation. Further, the length field may indicate the length of the waveform behavior of the I/O interface of the DQ bus and/or CA bus on the processor side.

In an embodiment of the present application, the waveform indication field (BUS_wave) is used to indicate the signal timing behavior of the target instruction, control the jump of each physical line on the transmission bus connected to the flash memory particle, and form different waveform behaviors by causing the jump of different physical lines, thereby further enabling the flash memory particle chip to execute different target instructions.

In the embodiment of the present application, the waveform behavior of the I/O interface of the DQ bus and/or CA bus on the processor side can be determined by at least one of the length field (Length) and the waveform indication field (BUS_wave).

In the embodiment of the present application, the lock field (Lock) indicates whether the target instruction is executed synchronously with the next instruction of a different bus. The next instruction of a different bus and the target instruction can be instructions of a flash memory particle chip or instructions of different flash memory particle chips. The embodiment of the present application does not impose specific restrictions on this. If the lock field of the target instruction indicates that the target instruction is not executed synchronously with the next instruction of a different bus, it can be understood that the target instruction currently being processed locks the transmission bus at the current moment, and does not allow instructions of different transmission buses to be executed at the same time.

In an embodiment of the present application, through the target format, the processor can better control the execution behavior between the CA bus and the DQ bus (the waveform between the interfaces of the CA bus and/or the DQ bus, that is, the signal behavior of the target instruction), data, parallel or exclusive operations, etc.

In an embodiment of the present application, the target condition may be associated with the lock field, and the target condition may include the lock field indicating that the target instruction and the next instruction of a different bus can be executed synchronously. If the lock field indicates that the target instruction and the next instruction of a different bus can be executed synchronously, then the first target unit on the first instruction pipeline provided by the embodiment of the present application and the second target unit on the second instruction pipeline can be executed in parallel, that is, the DQ bus and the CA bus can transmit data information at the same time, and efficiently process the target instruction of the flash memory particle chip.

In the embodiment of the present application, the instruction parsing unit can determine the instruction type and, at the same time, determine whether the target condition is met through a lock field (BUS lock) to solve the problem of exclusion between instructions.

In the embodiment of the present application, the processor can further realize simultaneous control of the CA bus and/or the DQ bus by simultaneously controlling the first instruction pipeline and/or the second instruction pipeline. And because the processor controls the CA bus and/or the DQ bus simultaneously, the behavior of any transmission bus can be reasonably arranged based on the behavior of the other transmission bus, making it easier to control the mutually exclusive relationship between the instruction operations of the two transmission buses.

In the embodiment of the present application, each unit on the first instruction pipeline can execute multiple first target instructions in parallel, and the multiple first target instructions are different instructions for different flash memory particle chips. For example, the CA instruction execution unit is executing the first target instruction for the first flash memory particle chip, the instruction parsing unit can be executing the first target instruction for the second flash memory particle chip, and the instruction fetching unit can execute the first target instruction for the third flash memory particle chip. Correspondingly, each unit on the second instruction pipeline can execute multiple second target instructions in parallel, and the multiple second target instructions are different instructions for different flash memory particle chips, and the target instructions include the first target instruction and the second target instruction.

In an embodiment of the present application, each unit on the first instruction pipeline sequentially executes a plurality of third target instructions, and the plurality of third target instructions are different instructions for the same flash memory particle chip (i.e., instructions for one die (DIE)). For example, for the same flash memory particle chip, it may include a CA instruction for starting data read transmission, a DQ instruction for data read transmission, and a CA instruction for ending data read transmission. In the first clock cycle, the instruction fetch unit obtains the CA instruction for starting data read transmission. In the second clock cycle, the instruction parsing unit parses the CA instruction for starting data read transmission, and the instruction fetch unit obtains the DQ instruction for data read transmission. In the third clock cycle, the CA instruction execution unit of the second instruction pipeline executes the CA instruction for starting data read transmission, the instruction parsing unit parses the DQ instruction for data read transmission, and the instruction fetch unit obtains the CA instruction for ending data read transmission. In this way, each unit on the first instruction pipeline sequentially executes a plurality of third target instructions, and the plurality of third target instructions are different instructions for the same flash memory particle chip; and accordingly, each unit on the second instruction pipeline sequentially executes a plurality of fourth target instructions, and the plurality of fourth target instructions are different instructions for the same flash memory particle chip. In the embodiment of the present application, the target instruction can be processed more efficiently through heterogeneous processing of the first instruction pipeline and/or the second instruction pipeline in the processor.

FIG3 is a block diagram of a device for instruction processing provided in an embodiment of the present application. As shown in FIG3 , the device for instruction processing 300 provided in an embodiment of the present application includes a flash memory particle chip 320 and a processor 310. The processor 310 is connected to the flash memory particle chip 320 via a CA bus, and the processor 310 is connected to the flash memory particle chip 320 via a DQ bus. The processor 310 in the device for instruction processing 300 provided in an embodiment of the present application may be the processor 100 shown in any one of FIG. 1-1 or FIG. 1-2. Therefore, the specific implementation of this embodiment may refer to the implementation of the corresponding processor in the foregoing text, and the repeated parts will not be repeated. In an embodiment of the present application, the device for instruction processing may be a device including a hardware device of the processor shown in any one of FIG. 1-1 or FIG. 1-2 and a hardware device of the flash memory particle chip.

In the instruction processing device shown in FIG. 3 provided in the embodiment of the present application, the number of the flash memory particle chips is N, each of the N flash memory particle chips is connected to the processor via a CA bus, and each of the N flash memory particle chips is connected to the processor via a DQ bus, and N is a positive integer greater than or equal to 1. One flash memory particle chip corresponds to one grain (DIE), and the target instruction for one flash memory particle chip can be executed in sequence. When the CA bus executes the CA instruction of the first flash memory particle chip, the DQ bus can execute the DQ instruction of the second flash memory particle chip, realizing parallel transmission and efficiently processing the target instruction.

In an embodiment of the present application, the waveform indication field in the target instruction includes a chip select indication field, and the chip select indication field is used for the processor to determine the target flash memory particle chip from N flash memory particle chips, and the chip select indication field is used to instruct the target flash memory particle chip to execute the target instruction. The instruction parsing unit in the processor determines the chip select line of the target flash memory particle chip in the bus according to the chip select indication segment, and controls the chip select line to generate fluctuations so that the pin of the target flash memory particle chip can receive the signal, so that the processor determines the target flash memory particle chip from the N flash memory particle chips. When the target flash memory particle chip receives the waveform of the target instruction through the pin, it can execute the target instruction. Through the chip select indication field, the target flash memory particle chip is determined from the N flash memory particle chips, and the accuracy of determining the target flash memory particle chip is improved.

In an embodiment of the present application, the instruction processing device shown in Figure 3 can be a controller including the processor and flash memory particle chip shown in any one of Figures 1-1 or 1-2.

An embodiment of the present application further provides a storage device, which may be a solid state disk (SSD), a universal flash storage (UFS), etc. including the above-mentioned controller.

In an embodiment of the present application, an electronic device is also provided, the electronic device comprising the above-mentioned storage device. The electronic device may be a terminal device storing the above-mentioned solid-state hard disk or universal flash memory, such as a personal mobile computer, or a server comprising the above-mentioned storage device.

In addition, in an embodiment of the present application, an instruction processing method is also provided, which is executed by a processor. The processor may be a processor provided in an embodiment of the present application as shown in any one of Figures 1-1 or 1-2, or may be other processors capable of implementing the SCA protocol. Figure 4 is a flow chart of an instruction processing method provided in an embodiment of the present application. As shown in Figure 4, the instruction processing method provided in an embodiment of the present application includes the following steps:

Step 410, obtaining the target instruction.

Step 420: parse the target instruction and determine the instruction type of the target instruction, where the instruction type includes a CA operation instruction or a DQ operation instruction.

If the instruction type is a CA operation instruction, step 440 may be executed; if the instruction type is a DQ operation instruction, step 430 may be executed.

In step 420 provided in the embodiment of the present application, the target instruction is an instruction that conforms to the target format. The target format includes a lock field indicating whether the target instruction is executed synchronously with the next instruction of a different bus. While determining the instruction type of the target instruction, it is also possible to confirm whether step 430 and step 440 can be executed in parallel based on the lock field of the target instruction. If the lock field indicates lock, then step 430 and step 440 cannot be executed in parallel; if the lock field indicates unlock, then step 430 and step 440 can be executed in parallel.

Step 430: When the instruction type is a DQ operation instruction, the target data is sent to the flash memory chip through the DQ bus.

Step 440: When the instruction type is a CA operation instruction, CA information or CA-related configuration information is sent to the flash memory chip through the CA bus.

If the CA operation instruction needs to be written back, step 460 may be executed; if the DQ operation instruction needs to be written back, step 450 may be executed.

Step 450: When the DQ operation instruction needs to be written back, first information is obtained from the flash memory chip through the DQ bus and written into the data storage space in the processor.

Step 460, when the CA operation instruction needs to be written back, obtain the second information from the flash memory particle chip through the CA bus and write it into the data storage space in the processor.

In an embodiment of the present application, the above method can be executed by the processor provided in the embodiment of the present application to improve the processing speed of the target instruction, control the exclusive relationship between the DQ bus and the CA bus, and solve the problem of mutual exclusion between instructions.

In order to better understand the processor provided in the embodiments of the present application, examples are given below. It should be understood that the examples are not limitations.

FIG5 is an external environment architecture diagram of a processor provided in an embodiment of the present application. As shown in FIG5, in an embodiment of the present application, after the SCA protocol processor shown in FIG1-1 or FIG1-2 receives an operation request from the application layer, it converts the application layer operation into the operation behavior of the DQ bus and the CA bus. The processor can realize synchronous control of the flash memory particle interface CA bus and the DQ bus, and the transmission on the two buses can be executed in parallel. In the process of the SCA protocol processor processing the target instruction as shown in FIG1-1 or FIG1-2, the target data can be obtained from the data path. The SCA protocol processor obtains the digital signal after the execution of the target instruction, converts the digital signal into an analog signal through the physical layer bus (DQ bus and CA bus), and further enables the flash memory particle chip to read. Correspondingly, during the write-back process, the physical layer bus converts the analog signal fed back by the flash memory particle chip into a digital signal.

FIG6 is an architecture diagram of a processor provided in an embodiment of the present application. As shown in FIG6 , in the processor provided in an embodiment of the present application (i.e., the SCA protocol processor shown in FIG6 ), two different instruction pipeline controls are included through a superscalar pipeline design method. The division of labor of each unit of the processor shown in FIG6 may include:

The instruction fetch unit reads instructions from the instruction storage space;

The instruction parsing unit processes the instruction, determines whether the instruction type is a CA operation instruction or a DQ operation instruction, and then sends the instruction to the CA instruction execution unit and the DQ instruction execution unit respectively according to the instruction type;

The processor shown in FIG6 has two execution units that can execute in parallel: a DQ instruction execution unit that sends data to the flash memory particles through the DQ bus physical layer; and a CA instruction execution unit that sends command and address configuration data to the flash memory particles through the CA bus physical layer.

The processor shown in FIG6 has two write-back units that can execute in parallel: a DQ write-back unit that reads data from flash memory particles through the DQ bus physical layer and writes it to the internal storage space of the main control chip (i.e., the data storage space shown in FIG6 ); and a CA write-back unit that reads configuration, ID and other data information from flash memory particles through the CA bus physical layer and writes it to the internal space of the main control chip (i.e., the data storage space shown in FIG6 ).

An example of the pipeline operation of instruction execution in the processor shown in FIG6 is as follows:

The operation of the application layer on the flash memory particles is executed according to the instructions in the SCA protocol processor shown in FIG6 .

Instructions in the processor follow the order of instruction fetch > instruction parsing > instruction execution > write back, and are executed in a 4-stage pipeline.

The processor's instructions can be divided into two types: CA bus operations and DQ bus operations.

The instruction execution stage controls the CA bus and DQ bus that interface with the flash memory particles respectively.

The write-back operation reads the data or configuration information of the flash memory particles and writes them to the data storage space of the main control chip. Some instructions do not need to be written back.

In the processor provided in the embodiment of the present application, the instruction storage space interacts with the application layer control, and the data storage space interacts with the data path. The data stored in the data storage space, which does not involve the processor itself, can be written back to the data path. During the execution of the DQ instruction, you can first consider reading data from the data storage space. If the data storage space cannot provide it, then read it from the data path through the data storage space. The data storage space also stores the data information written back by the CA instruction so that the instruction parsing unit can read it if the instruction parsing unit needs the execution result of the previous instruction.

In addition, in the processor provided in the embodiment of the present application, a general instruction architecture can be used, such as the instruction architecture shown in Figure 2. Based on the instruction format shown in Figure 2, the processor can control whether the instructions on the DQ bus and the CA bus can be executed in parallel, that is, whether there is an exclusive relationship between the instructions, and can also control the waveform behavior of each instruction on the IO interface, the data sent/received and the behavior.

In order to better understand the instruction processing method provided in the embodiments of the present application, examples are given. It should be understood that the examples are not limitations.

Figure 7 is an architecture diagram of the processing process of the target instruction provided in the embodiment of the present application. As shown in Figure 7, in the processing process of the target instruction provided in the embodiment of the present application, the processor shown in any one of Figures 1-1 or 1-2 executes the following instructions A~I in sequence according to the instruction sequence and the dual instruction pipeline.

Instructions B and F are data transmission instructions (DQ instructions) and are transmitted on the DQ bus (BUS). B is a read data instruction and needs to write back the DQ BUS data; F is a write data instruction and does not need to write back.

Instructions A, C, D, E, H, and I are command and address related instructions (CA instructions) and are transmitted on the CA BUS. Among them, H is a status read instruction through the CA BUS and needs to write back the CA BUS data; other instructions only need to send CA signals and do not need to write back data.

Since the interface BUS resources required by instruction B and instruction C do not conflict, these two instructions can be executed in parallel;

Since the interface BUS resources required by instruction F and instruction H do not conflict, these two instructions can be executed in parallel;

A, B, and D are the instructions of DIE 1 respectively; these three operations can be executed sequentially but not in parallel. However, B can execute the CA BUS operation of C–DIE2 during the DQ BUS execution.

E, F, and I commands are the instructions of DIE n respectively; these three operations can be executed sequentially but not in parallel. However, F can execute the CA BUS operation of H–DIE m during the DQ BUS execution.

Specifically, in the first clock cycle (the upper and lower dashed lines can be understood as one clock cycle), the instruction fetch unit of the processor obtains the data transmission start command A of DIE 1.

In the second clock cycle, the instruction fetch unit of the processor obtains the DIE 1 data read transfer instruction B, and the instruction parsing unit of the processor obtains the instruction A obtained by the instruction fetch unit in the first clock cycle.

In the third clock cycle, the instruction fetch unit of the processor obtains the DIE 2 command + address C, the instruction parsing unit of the processor obtains the instruction B obtained by the instruction fetch unit in the second clock cycle, and the CA instruction execution unit of the second instruction pipeline executes the A instruction.

In the fourth clock cycle, the instruction fetch unit of the processor obtains the DIE 1 data transmission end instruction D, the instruction parsing unit of the processor obtains the instruction C obtained by the instruction fetch unit in the third clock cycle, the DQ instruction execution unit of the first instruction pipeline executes instruction B, and the CA bus obtains the DIE 1 data transmission start instruction (i.e., SCE).

Thus, the control of the SCA protocol is realized through a heterogeneous pipeline superscalar processor design method. The synchronous control of the CA bus and the DQ bus of the flash memory particle interface is realized, and the transmission on the two buses can be executed in parallel.

In an embodiment of the present application, the application layer control is converted into the SCA protocol waveform of the NAND chip IO interface by means of a processor; to increase flexibility, the standard protocol and custom commands of storage chips (Flash) of various manufacturers can be adapted through the instruction storage space. Through the superscalar design method, two heterogeneous pipelines are provided to handle the control of the CA bus and the DQ bus respectively, so that the signal transmission on the two buses can be executed in parallel. Since the two pipelines share the instruction fetch and instruction parsing units, the hardware area of the processor can be reduced. At the same time, the same processor controls the behavior of the CA bus and the DQ bus, which can more easily control the mutually exclusive relationship between the instruction operations of the two buses. And in an embodiment of the present application, a general instruction architecture is used to control the execution behavior (waveform), data, parallel or exclusive operations of the CA bus and the DQ bus.

The processing target instruction provided by the embodiment of the present application also has the following advantages: 1. The behavior of the DQ bus and the CA bus can be controlled synchronously: whether IO operations can be executed in parallel, and the behavior of the two BUS is exclusive. 2. Using the processor method, the sequence and timing of command/address and data transmission can be flexibly specified, and various flexible flash memory operations can be supported; more flexible adaptation to various operation commands from different manufacturers. 3. Using the superscalar design method, compared with the solution of using two independent processors to control the CA bus and the DQ bus respectively, only one execution unit and one write-back unit are added, and the resource area is relatively small.

An embodiment of the present application also provides a computer-readable storage medium, on which a program or instruction is stored. When the program or instruction is executed by a processor, the various processes of the above-mentioned method embodiment are implemented and the same technical effect can be achieved. To avoid repetition, it will not be repeated here.

The readable storage medium includes a computer-readable storage medium, such as a computer read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

An embodiment of the present application provides a computer program product, which is stored in a storage medium. The program product is executed by at least one processor to implement the various processes of the above-mentioned method embodiment and can achieve the same technical effect. To avoid repetition, it will not be repeated here.

It should be noted that, in this article, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises one..." does not exclude the presence of other identical elements in the process, method, article or device including the element. In addition, it should be noted that the scope of the method and device in the embodiment of the present application is not limited to performing functions in the order shown or discussed, and may also include performing functions in a substantially simultaneous manner or in reverse order according to the functions involved, for example, the described method may be performed in an order different from that described, and various steps may also be added, omitted, or combined. In addition, the features described with reference to certain examples may be combined in other examples.

Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a computer software product, which is stored in a storage medium (such as ROM/RAM, a disk, or an optical disk), and includes a number of instructions for enabling a terminal (which can be a mobile phone, a computer, a server, or a network device, etc.) to execute the methods described in each embodiment of the present application.

The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present application, ordinary technicians in this field can also make many forms without departing from the purpose of the present application and the scope of protection of the claims, all of which are within the protection of the present application.

Claims (15)

1. A processor, comprising:

the instruction fetching unit is used for obtaining a target instruction and sending the target instruction to the instruction analysis unit;

The instruction analysis unit is used for determining the instruction type of the target instruction by analyzing the target instruction, wherein the instruction type comprises a command/address CA operation instruction or a data DQ operation instruction;

the DQ instruction execution unit is used for sending target data to the flash memory particle chip through the DQ bus under the condition that the instruction type is a DQ operation instruction;

the CA instruction execution unit is used for sending CA information or configuration information related to the CA to the flash memory particle chip through a CA bus under the condition that the instruction type is a CA operation instruction;

the instruction fetching unit, the instruction analyzing unit and the first target unit form a first instruction pipeline; the instruction fetching unit, the instruction analyzing unit and the second target unit form a second instruction pipeline;

The first instruction pipeline and the second instruction pipeline execute in parallel if a target condition is satisfied, wherein the first target unit includes the DQ instruction execution unit and the second target unit includes the CA instruction execution unit.

2. The processor of claim 1, wherein the processor further comprises:

The DQ write-back unit is used for acquiring first information from the flash memory particle chip through the DQ bus and writing the first information into a data storage space in the processor under the condition that the DQ operation instruction needs to be written back;

the CA write-back unit is used for acquiring second information from the flash memory particle chip through the CA bus and writing the second information into a data storage space in the processor under the condition that the CA operation instruction needs to be written back;

wherein the first target unit further comprises the DQ write back unit and the second target unit further comprises the CA write back unit.

3. The processor of claim 2, wherein a first designated unit of the first target unit on the first instruction pipeline and a second designated unit of the second target unit on the second instruction pipeline execute in parallel if a target condition is met;

Wherein the first specification unit includes at least one of the DQ instruction execution unit and the DQ write back unit, and the second specification unit includes at least one of the CA instruction execution unit and the CA write back unit.

4. A processor according to any of claims 1-3, characterized in that the processor has an instruction storage space for storing various instructions adapted to a flash granule chip, the instruction storage space being used for storing the target instructions.

5. A processor according to any one of claims 1 to 3, wherein the target instruction is an instruction conforming to a target format; wherein the target format includes: bus type field, data field, write back indication field, length field, waveform indication field, and lock field;

The bus type field is used for indicating whether the bus type used by the target instruction is a CA bus or a DQ bus;

The data field indicates the data content to be transmitted;

The write-back indication field is used for indicating whether the target instruction has write-back operation or not;

the length field is used for indicating the length of the current operation;

the waveform indication field is used for indicating signal time sequence behavior of the target instruction;

The lock field indicates whether the target instruction is executed in synchronization with an instruction of a next different bus.

6. The processor of claim 5, wherein the target condition includes the lock field indicating that a target instruction is executed in synchronization with an instruction of a next different bus.

7. A processor according to any one of claims 1-3, wherein each unit on the first instruction pipeline executes a plurality of first target instructions in parallel, the plurality of first target instructions being different instructions for different flash granule chips; each unit on the second instruction pipeline executes a plurality of second target instructions in parallel, wherein the plurality of second target instructions are different instructions aiming at different flash memory particle chips, and the target instructions comprise a first target instruction and a second target instruction;

Or alternatively, the first and second heat exchangers may be,

Each unit on the first instruction pipeline sequentially executes a plurality of third target instructions, wherein the plurality of third target instructions are different instructions aiming at the same flash memory particle chip; each unit on the second instruction pipeline sequentially executes a plurality of fourth target instructions, wherein the fourth target instructions are different instructions aiming at the same flash memory particle chip, and the target instructions comprise a third target instruction and a fourth target instruction.

8. An apparatus for instruction processing, comprising a flash memory die and a processor according to any of claims 1-7, said processor being coupled to said flash memory die via a CA bus, said processor being coupled to said flash memory die via a DQ bus.

9. The apparatus of claim 8, wherein the number of flash die is N, each of the N flash die is connected to the processor by a CA bus, and each of the N flash die is connected to the processor by a DQ bus, N being a positive integer greater than or equal to 1.

10. The apparatus of claim 9, wherein the target instruction is an instruction conforming to a target format; wherein the target format includes: bus type field, data field, write back indication field, length field, waveform indication field, and lock field;

the waveform indication field in the target instruction comprises a chip selection indication field, the chip selection indication field is used for determining a target flash granule chip from N flash granule chips by the processor, and the chip selection indication field is used for indicating the target flash granule chip to execute the target instruction.

11. The device of any one of claims 8-10, wherein the device is a controller.

12. A storage device, characterized in that it comprises the apparatus according to claim 11.

13. An electronic device, characterized in that it comprises a storage device according to claim 12.

14. A method of instruction processing, performed by a processor, the method comprising:

Acquiring a target instruction;

Analyzing the target instruction, and determining the instruction type of the target instruction, wherein the instruction type comprises a command/address CA operation instruction or a data DQ operation instruction;

Under the condition that the instruction type is DQ operation instruction, sending target data to the flash memory particle chip through a DQ bus;

Under the condition that the instruction type is a CA operation instruction, sending CA information or configuration information related to the CA to the flash memory particle chip through a CA bus;

Under the condition that the DQ operation instruction needs to be written back, acquiring first information from a flash memory particle chip through a DQ bus, and writing the first information into a data storage space in the processor;

And under the condition that the CA operation instruction needs to be written back, acquiring second information from the flash memory particle chip through a CA bus, and writing the second information into a data storage space in the processor.

15. A storage medium storing a program which when executed implements the method of claim 14.