CN118349282B - SIMT processor supporting multiple transmissions, instruction processing method and chip - Google Patents

Abstract

The invention provides a SIMT processor supporting multiple emission, an instruction processing method and a chip, and relates to the technical field of computers, wherein the processor comprises: at least two sets of register files, an instruction dispatch module, an operand collection module, an instruction dispatch module, and an execution module, wherein: the instruction scheduling module is connected with the operand collecting module; the operand collection module is connected with the at least two groups of register files and the instruction distribution module, and is used for collecting operands corresponding to all the first instructions in parallel from the at least two groups of register files and sending all the first instructions to the instruction distribution module; the instruction distribution module is connected with the execution module and is used for determining at most Q second instructions from the cache instructions of the collected operands; the execution module is used for executing at most Q second instructions in parallel. The present invention may enable multiple transmit capabilities of a single SIMT processor.

Description

SIMT processor supporting multiple issues, instruction processing method and chip

Technical Field

The present invention relates to the field of computer technology, and in particular to a SIMT processor supporting multiple transmissions, an instruction processing method and a chip.

Background Art

In recent years, instruction processing chips such as GPU (Graphics Processing Unit) and AI (Artificial Intelligence) processors have played a key role in many fields, especially in fields that require a large amount of parallel computing and high-performance computing, such as artificial intelligence and scientific computing. SIMT (Single Instruction Multiple Threads) processors are the basis of instruction processing chips. The core idea is to run a large number of threads at the same time. These threads execute the same instructions and process different data to achieve efficient parallel computing.

In the prior art, SIMT processors use a single-issue structure, that is, the scheduler selects one instruction to execute in each cycle, and the overall performance is improved by increasing the number of SIMT processors in the instruction processing chip. However, with the increase in computing power requirements, the single-issue structure can no longer meet the increasing execution performance requirements of instruction processing chips.

Summary of the invention

The present invention provides a SIMT processor supporting multiple launches, an instruction processing method and a chip, so as to solve the defect that the single launch structure in the prior art can no longer meet the increasingly improved execution performance requirements of instruction processing chips, and realize the multiple launch capability of a single SIMT processor.

The present invention provides a SIMT processor supporting multiple issues, comprising: at least two groups of register files, an instruction scheduling module, an operand collection module, an instruction distribution module and an execution module, wherein:

The instruction scheduling module is connected to the operand collection module, and is used to group the multiple thread groups and determine the first instructions corresponding to at least two groups; the first instructions corresponding to the at least two groups correspond to the at least two register files in a one-to-one manner;

The operand collection module is connected to the at least two groups of register files and the instruction distribution module, and is used to collect operands corresponding to all first instructions from the at least two groups of register files in parallel, and send all first instructions to the instruction distribution module;

The instruction distribution module is connected to the execution module, and the instruction distribution module is used to determine at most Q second instructions from the cache instructions of the collected operands, where Q is determined based on the number of execution units in the execution module; the cache instructions at least include all the first instructions;

The execution module is used for executing the at most Q second instructions in parallel.

According to the SIMT processor supporting multiple issues provided by the present invention, the instruction scheduling module groups multiple thread groups, and determines the first instructions corresponding to at least two groups, respectively, including:

Grouping the instructions of the multiple thread groups to obtain at least two groups and first instructions to be tested corresponding to the at least two groups; the first instructions to be tested corresponding to the at least two groups correspond to the at least two register files in a one-to-one manner;

Based on the register occupancy table and the operand occupancy table corresponding to the at least two groups respectively, determining the executable instruction groups corresponding to the at least two groups respectively from the first instructions to be tested corresponding to the at least two groups respectively in parallel;

The instruction with the highest priority in each group of the executable instructions is determined as the first instruction corresponding to each of the at least two groups.

According to the SIMT processor supporting multiple transmissions provided by the present invention, the step of determining in parallel the executable instruction groups corresponding to the at least two groups from the first instructions to be tested corresponding to the at least two groups based on the register occupancy table and the operand occupancy table corresponding to the at least two groups, comprises:

Based on the register occupancy tables corresponding to the at least two groups, determining whether the first instruction to be tested corresponding to each group of the groups has a register read/write dependency, and obtaining a first determination result corresponding to the first instruction to be tested corresponding to each group of the groups;

Based on the operand occupancy tables corresponding to the at least two groups, determine whether there are remaining positions in the operand cache unit range corresponding to the first instruction to be tested corresponding to each group of the groups, and obtain a second determination result corresponding to the first instruction to be tested corresponding to each group of the groups;

Based on the first judgment result and the second judgment result corresponding to each group of the groups, the executable instruction groups corresponding to the at least two groups are determined in parallel.

According to the SIMT processor supporting multiple issues provided by the present invention, the operand collection module includes at least two operand collection units and at least two operand caches;

The at least two operand collection units are connected to the read-write controller, and there is a corresponding relationship between the at least two operand collection units, the at least two operand caches and the at least two groups of register stacks. The at least two operand collection units are used to determine the read requests corresponding to all the first instructions in parallel, and send each of the read requests to the read-write controller;

Each of the read requests is used to instruct the read/write controller to determine operands corresponding to all the first instructions in parallel from the at least two groups of register files, and write the operands corresponding to each of the first instructions into the corresponding operand cache.

According to the SIMT processor supporting multiple issues provided by the present invention, the at least two operand caches are further connected to an operand interconnection circuit and at least two read interconnection circuits, the operand interconnection circuit is connected to the execution module, and the at least two read interconnection circuits are correspondingly connected to the at least two groups of register files;

The read/write controller determines operands corresponding to all the first instructions from the at least two groups of register files in parallel, and writes the operands corresponding to all the first instructions into the corresponding operand cache, including:

For each of the read requests, the read-write controller is used to determine the operand address in the read request corresponding to the first instruction; the operand address includes the read address corresponding to the register stack, the selection index corresponding to the read interconnection circuit, and the distribution selection address corresponding to the operand cache; based on the read address corresponding to the register stack, the operand is read from the corresponding register stack; based on the selection index corresponding to the read interconnection circuit and the distribution selection address corresponding to the operand cache, the cache unit corresponding to the operand is determined in the operand cache; and the operand is written into the cache unit.

According to the SIMT processor supporting multiple issues provided by the present invention, the instruction distribution module determines at most Q second instructions from the cache instructions of the collected operands, including:

Writing all the first instructions of the collected operands into their corresponding to-be-executed instruction tables in parallel; the to-be-executed instruction tables correspond one-to-one to all the first instructions;

From all cache instructions corresponding to all instruction tables to be executed, determine at most Q second instructions with no execution conflicts and the best priority combination, the execution conflicts include execution unit conflicts and write conflicts, the execution unit conflicts are used to characterize that the execution units corresponding to any two cache instructions are the same, the write conflicts are used to characterize that the execution results corresponding to any two cache instructions are written to the same register stack at the same time, and the execution units belong to the execution module.

According to the SIMT processor supporting multiple issues provided by the present invention, the execution module includes at least two execution units, the at least two execution units correspond to the at most Q second instructions, and the at least two execution units are both connected to a write interconnection circuit and the operand interconnection circuit, and the write interconnection circuit connects the at least two groups of register files;

For each of the execution units, the execution unit that receives the second instruction is used to determine the corresponding target operand cache based on the second instruction; determine the target operand from the target operand cache based on the operand interconnection circuit; execute the second instruction based on the target operand, determine the execution result, and write the execution result into at least two groups of register stacks corresponding to the second instruction through the write interconnection circuit.

The present invention also provides an instruction processing method, which is applied to a SIMT processor supporting multiple transmissions as described in any one of the above, and the method comprises:

Using an instruction scheduling module to group the plurality of thread groups, and determining first instructions corresponding to at least two groups, wherein the first instructions corresponding to the at least two groups correspond to at least two register stacks in a one-to-one manner;

Using the operand collection module to collect operands corresponding to all first instructions from the at least two groups of register files in parallel, and sending all first instructions to the instruction distribution module;

Determine, by the instruction distribution module, at most Q second instructions from the cache instructions of the collected operands, where Q is determined based on the number of execution units in the execution module; the cache instructions at least include all the first instructions;

The execution module is used to execute the at most Q second instructions in parallel.

The present invention also provides a chip, comprising at least two SIMT processors supporting multiple transmissions as described in any one of the above items.

The present invention also provides a non-transitory computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the instruction processing method described above is implemented.

The SIMT processor, instruction processing method and chip supporting multi-issue provided by the present invention group multiple groups of thread groups through an instruction scheduling module, and determine the first instructions corresponding to at least two groups respectively, the operand collection module collects operands corresponding to all first instructions corresponding to at least two groups of register stacks in parallel from at least two groups of register stacks, and sends all first instructions with collected operands to the instruction distribution module, the instruction distribution module determines at most Q second instructions from the cache instructions including all first instructions, so that the execution module executes at most Q second instructions in parallel. The present invention ensures the realization of multi-issue capability from the aspects of the number of instructions, the storage of operand groups corresponding to each register stack, and the parallel execution consisting of the instruction scheduling module, the operand collection module, the instruction distribution module and the execution module, and improves the efficiency of instruction execution.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

FIG1 is a schematic diagram of the structure of a SIMT processor supporting multiple transmissions provided by an embodiment of the present invention.

FIG. 2 is a schematic diagram of the structure of an instruction scheduling module provided in an embodiment of the present invention.

FIG. 3 is a connection diagram of an operand cache collection module provided by an embodiment of the present invention.

FIG. 4 is a connection diagram of a read interconnect circuit provided by an embodiment of the present invention.

FIG5 is a schematic diagram of the structure of an instruction distribution module provided in an embodiment of the present invention.

FIG. 6 is a connection diagram of an execution module provided in an embodiment of the present invention.

FIG. 7 is a schematic flow chart of an instruction processing method provided in an embodiment of the present invention.

DETAILED DESCRIPTION

In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

In the prior art, the SIMT processors in instruction processing chips such as GPU (Graphics Processing Unit) and AI (Artificial Intelligence) processors adopt a single-issue structure. Taking GPU as an example, the GPU includes multiple interconnected stream processors, and each stream processor includes 4 interconnected SIMT (Single Instruction Multiple Threads) processors. Each SIMT processor adopts a single-issue structure. The scheduler selects an instruction in each cycle, and can support multiple threads to execute the instruction at the same time. It is scheduled in thread groups (warps). Each thread group can include 32 or 64 threads. The utilization of the computing unit is improved by switching multiple thread groups. However, with the increase in demand for computing power, the types of computing units in SIMT processors have increased. For example, tensor computing cores have been added. SIMT processors with a single-issue structure can no longer meet the increasingly improved execution performance requirements of instruction processing chips. At the same time, the utilization of computing units in a single SIMT processor is low.

In view of the above problems in the prior art, an embodiment of the present invention provides a SIMT processor supporting multiple launches. FIG1 is a schematic diagram of the structure of the SIMT processor supporting multiple launches provided by an embodiment of the present invention. As shown in FIG1 , the SIMT processor supporting multiple launches includes: at least two groups of register stacks, an instruction scheduling module, an operand collection module, an instruction distribution module and an execution module.

The instruction scheduling module is connected to the operand collection module, and is used to group multiple thread groups and determine the first instructions corresponding to at least two groups; the first instructions corresponding to the at least two groups correspond to the at least two register stacks one by one.

The operand collection module is connected to the at least two groups of register files and the instruction distribution module, and is used to collect operands corresponding to all first instructions from the at least two groups of register files in parallel, and send all first instructions to the instruction distribution module.

The instruction distribution module is connected to the execution module, and is used to determine at most Q second instructions from the cache instructions of the collected operands, where Q is determined based on the number of execution units in the execution module; the cache instructions at least include all the first instructions.

The execution module is used for executing the at most Q second instructions in parallel.

Specifically, to achieve multi-issue capability, in the embodiment of the present invention, first, the instruction scheduling module obtains instructions of multiple thread groups in each cycle. Then, the instruction scheduling unit groups the multiple thread groups to obtain N groups, where N is an integer greater than 1, and the number of group instructions in each group is T=W. A/N, where T represents the number of grouped instructions in each group, W represents the number of thread groups, and W is an integer greater than 1, and A represents the number of instructions included in a single thread group, and A is an integer greater than or equal to 1. That is, the instruction scheduling module realizes the grouping of instructions of multiple thread groups by grouping multiple thread groups. Afterwards, a first instruction is determined from each group, that is, a first instruction is determined from the T instructions of each group, so as to realize the determination of N first instructions from N groups, and the N first instructions correspond one-to-one to the N register stacks, and the N first instructions correspond to different thread groups. Instead of obtaining only one instruction in each cycle as in the prior art, the multi-launch capability is ensured in terms of the number of instructions. After determining the N first instructions, the instruction scheduling module sends the N first instructions to the operand collection module in parallel.

After receiving N first instructions, the operand collection module needs to collect the operands corresponding to each of the N first instructions before the N first instructions are executed, in order to ensure the subsequent execution efficiency of the N first instructions, that is, to determine the data or data sources involved in the operation in the N first instructions. In order to improve the efficiency of operand collection and ensure multi-transmission capability, in an embodiment of the present invention, all register stacks are divided into multiple groups, and each group of register stacks pre-stores the operands corresponding to each first instruction. At this time, the operand collection module can collect the corresponding operands from the register stacks corresponding to each first instruction respectively, and the collection of the operands of each first instruction is performed in parallel. For each first instruction, after collecting the operands of the first instruction, the first instruction can be sent to the instruction distribution module to indicate to the instruction distribution module that the operands of the first instruction have been collected.

After the instruction distribution module receives each first instruction, the cache instructions in the instruction distribution module include two situations. The first situation is: there are only N first instructions whose operands have been collected in the current cycle in the instruction distribution module. At this time, the instruction distribution module can determine all N first instructions as cache instructions. The instruction distribution module can select M second instructions from the N first instructions, M is an integer less than or equal to N, N is less than or equal to Q, Q is determined based on the parallel capability of the execution module, that is, Q is determined based on the number of execution units included in the execution module, Q is an integer greater than or equal to 2, for example, Q can be 2, 3, 4, etc. The second situation is: the instruction distribution module includes N first instructions whose operands have been collected in the current cycle, and historical instructions whose operands have been collected in the historical cycle. Among them, the historical cycle is the first m cycles of the current cycle, and m is an integer greater than or equal to 1. The historical instructions can be instructions with write conflicts and/or lower priorities in the historical cycle. At this time, all first instructions together with the historical instructions whose operands have been collected in the historical cycle constitute cache instructions. The instruction distribution module selects M second instructions from all cache instructions, where M is an integer less than or equal to Q, and distributes the M second instructions in parallel to the execution module. After the execution module executes the M second instructions in parallel, it determines the execution results corresponding to each second instruction. The instruction scheduling module, the operand collection module, the instruction distribution module, and the execution module constitute at least two parallel instruction processing paths to achieve multi-launch capability. In addition, after determining the execution results corresponding to each second instruction, the execution results can be written into the register stack corresponding to each second instruction for storage.

It should be noted that the number of second instructions determined by the instruction distribution module in each cycle is a dynamic value. For example, taking Q=4 as an example, one second instruction is determined in the first cycle, three second instructions are determined in the second cycle, and two second instructions are determined in the third cycle. The average number of second instructions determined in the three cycles is 2. In the embodiment of the present invention, the SIMT processor realizes multi-issue from the average number of instructions executed in each cycle, rather than multi-issue in each cycle.

Optionally, each register file includes at least four single-port SRAMs (Static Random Access Memory), and the number of single-port SRAMs included in each register file is greater than or equal to 4 and is a power of 2. At least one operand corresponding to a first instruction is stored in the register file corresponding to the first instruction, and at least one operand corresponding to different first instructions is stored in different register files. For example, as shown in Figure 1, the two operands corresponding to the first instruction 0 are stored in register file 0, and are respectively stored in SRAM B0 and SRAM B3 of register file 0. For another example, the three operands corresponding to the first instruction 1 are stored in register file 1, and are respectively stored in SRAMB0, SRAM B1 and SRAM B2 of register file 1.

It should be noted that N can be determined according to the multi-transmission capability supported by the SIMT processor. For example, if the SIMT processor supports dual-transmission capability, N can be 2; if the SIMT processor supports quad-transmission capability, N can be 4, etc. The embodiment of the present invention does not limit this.

It should be noted that operands are used to characterize the source of data to be operated or the data itself. For example, the instruction is: ADD a, b, where a and b are both operands, and a and b are both data to be added. Another example is: ADD ax, bx, where ADD represents the addition operator, ax and bx are both operands, and both are data sources, that is, ax represents the ax register, bx represents the bx register, and the ax register and the bx register respectively store the two values to be involved in the addition operation.

The SIMT processor supporting multiple launches provided by the embodiment of the present invention groups multiple thread groups through an instruction scheduling module, and determines the first instructions corresponding to each of at least two groups. The operand collection module collects operands corresponding to all first instructions corresponding to at least two register stacks in parallel from at least two register stacks, and sends all first instructions with collected operands to the instruction distribution module. The instruction distribution module determines at most Q second instructions from the cache instructions including all first instructions, so that the execution module executes at most Q second instructions in parallel. The present invention ensures the realization of multi-launch capability from the aspects of the number of instructions, the storage of operand groups corresponding to each register stack, and the parallel execution consisting of the instruction scheduling module, the operand collection module, the instruction distribution module and the execution module, and improves the instruction execution efficiency.

Furthermore, the instruction scheduling module groups the multiple thread groups and determines the first instructions corresponding to at least two groups, including the following steps.

The multiple thread groups are grouped to obtain at least two groups and first instructions to be tested corresponding to the at least two groups; the first instructions to be tested corresponding to the at least two groups correspond to the at least two register files in a one-to-one manner.

Based on the register occupancy table and the operand occupancy table respectively corresponding to the at least two groups, the executable instruction groups respectively corresponding to the at least two groups are determined in parallel from the first instructions to be tested respectively corresponding to the at least two groups.

The instruction with the highest priority in each group of the executable instructions is determined as the first instruction corresponding to each of the at least two groups.

Specifically, FIG. 2 is a schematic diagram of the structure of the instruction scheduling module provided by an embodiment of the present invention. As shown in FIG. 2 , the instruction scheduling module is divided into N instruction scheduling units as a whole, and the numbers n of the N instruction scheduling units are 0, 1, 2, ... N-1, respectively. After the instruction scheduling module obtains the instructions of the W thread groups, the N instruction scheduling units divide the W thread groups into N groups, and each instruction scheduling unit processes the first instruction to be tested of a group, and each group includes T first instructions to be tested. After grouping, for each instruction scheduling unit, the instruction scheduling unit can first check whether each first instruction to be tested obtained after grouping can execute subsequent operand collection, that is, obtain the register occupancy table and operand occupancy table of the instruction scheduling unit, the register occupancy table is used to maintain the register being written, and the operand occupancy table is used to maintain the occupancy of the operand cache. After obtaining the register occupancy table and the operand occupancy table, for each first instruction to be tested, based on the instruction information, register occupancy table and operand occupancy table of the first instruction to be tested, determine whether the first instruction to be tested is ready to execute subsequent operand collection. If ready, the first instruction to be tested is determined as an executable instruction. All executable instructions constitute the executable instruction group of the instruction scheduling unit. The number of executable instructions in the executable instruction group is less than or equal to the number of first instructions to be tested obtained after the instruction scheduling unit is grouped. Afterwards, all executable instructions in the executable instruction group are sorted in order from high to low priority, and the executable instruction with the highest priority is determined as the first instruction of the instruction scheduling unit. After N instruction scheduling units perform the above operations, N first instructions can be obtained.

Optionally, the N instruction scheduling units may group the instructions of the W thread groups in an interleaved manner to obtain N groups of first instructions to be tested. The numbers of the first instructions to be tested obtained after grouping in the instruction scheduling unit n are n, n+N, n+2, etc. N, ..., n+(T-1) N. For example, when N=2, after grouping W thread groups, instruction scheduling unit 0 obtains the first instruction to be tested with an even number, and instruction scheduling unit 1 obtains the first instruction to be tested with an odd number.

Furthermore, based on the register occupancy table and the operand occupancy table corresponding to the at least two groups respectively, the method of determining the executable instruction groups corresponding to the at least two groups respectively from the first instructions to be tested corresponding to the at least two groups respectively in parallel includes the following steps.

Based on the register occupancy tables corresponding to the at least two groups, it is determined whether the first instruction to be tested corresponding to each group of the groups has register read/write dependency, and a first determination result of the first instruction to be tested corresponding to each group of the groups is obtained.

Based on the operand occupancy tables corresponding to the at least two groups, it is determined whether there are remaining positions in the operand cache unit range corresponding to the first instruction to be tested corresponding to each group of the groups, and a second judgment result of the first instruction to be tested corresponding to each group of the groups is obtained.

Based on the first judgment result and the second judgment result of the first instruction to be tested corresponding to each group of the groups, the executable instruction groups corresponding to the at least two groups are determined in parallel.

Specifically, after obtaining the register occupancy table and operand occupancy table of each group, for each first instruction to be tested in the group, determine the register to be read and written from the instruction code corresponding to the first instruction to be tested, and determine the read and write status of the register from the register occupancy table. According to the read and write status of the register, determine whether the first instruction to be tested has a register read and write dependency, that is, determine whether the read and write status of the register is an occupied state. The occupied state can be understood as whether the register is occupied by other unfinished instructions. If it is an occupied state, the first judgment result obtained is that there is a register read and write dependency. If it is an idle state, the first judgment result obtained is that there is no register read and write dependency. At the same time, obtain the operand cache unit range corresponding to the first instruction to be tested, and obtain the occupancy of the cache units within the operand cache unit range from the operand occupancy table. If all cache units within the operand cache unit range are occupied and there is no remaining position, the second judgment result obtained is that there is an operand cache conflict. If all cache units within the operand cache unit range are not fully occupied and there are remaining positions, the second judgment result obtained is that there is no operand cache conflict. Afterwards, after determining the first judgment result and the second judgment result, if there is no register read/write dependency in the first judgment result and there is no operand cache conflict in the second judgment result, the first instruction to be tested can be determined as an executable instruction, and all executable instructions constitute the executable instruction group of the instruction scheduling unit. In other cases, the first instruction to be tested is not selected, indicating that the first instruction to be tested is not ready to perform subsequent operand cache collection operations.

It should be noted that the operand cache unit range includes at least one cache unit, and the number of cache units included in the operand cache unit range is less than the number of cache units in any operand cache in the operand collection module. If the operand cache unit range includes only one cache unit, determining whether there is a remaining position in the operand cache unit range can be understood as determining whether the cache unit is occupied. If the operand cache unit range includes at least two cache units, determining whether there is a remaining position in the operand cache unit range can be understood as determining whether there is an unoccupied cache unit in at least two cache units.

Furthermore, the operand collection module includes at least two operand collection units and at least two operand caches.

The at least two operand collection units are connected to a read-write controller, and a corresponding relationship exists between the at least two operand collection units, the at least two operand caches and the at least two groups of register stacks. The at least two operand collection units are used to determine in parallel the read requests corresponding to all the first instructions respectively, and send each of the read requests to the read-write controller.

Each of the read requests is used to instruct the read/write controller to determine operands corresponding to all the first instructions in parallel from the at least two groups of register files, and write the operands corresponding to each of the first instructions into the corresponding operand cache.

Specifically, after the instruction scheduling module determines the N first instructions, the N operand collection units in the operand collection module receive one first instruction respectively. For each operand collection unit, the operand collection unit generates a read request according to the received first instruction, and sends the read request to the read-write controller. The read-write controller can read at least one operand corresponding to the first instruction from the register stack corresponding to the operand collection unit according to the read request, and write the at least one operand into the operand cache corresponding to the operand collection unit, so as to prepare data for the execution of the first instruction.

Furthermore, Figure 3 is a connection diagram of the operand cache collection module provided by an embodiment of the present invention. As shown in Figure 3, the at least two operand caches are also connected to an operand interconnection circuit and at least two read interconnection circuits, the operand interconnection circuit is connected to the execution module, and the at least two read interconnection circuits are correspondingly connected to the at least two groups of register stacks.

The read/write controller determines operands corresponding to all the first instructions from the at least two groups of register files in parallel, and writes the operands corresponding to all the first instructions into the corresponding operand cache, including the following steps.

For each of the read requests, the read-write controller is used to determine the operand address in the read request corresponding to the first instruction; the operand address includes the read address corresponding to the register stack, the selection index corresponding to the read interconnection circuit, and the distribution selection address corresponding to the operand cache; based on the read address corresponding to the register stack, the operand is read from the corresponding register stack; based on the selection index corresponding to the read interconnection circuit and the distribution selection address corresponding to the operand cache, the cache unit corresponding to the operand is determined in the operand cache; and the operand is written into the cache unit.

Specifically, after the read/write controller receives the read request corresponding to each operand collection unit, the operand address corresponding to the first instruction can be generated according to the read request, and the operand address includes the read address corresponding to the register stack, the selection index corresponding to the read interconnection circuit, and the distribution selection address corresponding to the operand cache, wherein the read address corresponding to the register stack can be understood as the storage address of at least one operand corresponding to the first instruction in the corresponding register stack, the selection index corresponding to the read interconnection circuit can be used to determine the number of columns of at least one operand corresponding to the first instruction in the corresponding operand cache, and the distribution selection address corresponding to the operand cache can be used to determine the number of rows of at least one operand corresponding to the first instruction in the corresponding operand cache. Afterwards, the read/write controller can send the read address corresponding to the register stack to the corresponding register stack, and read at least one operand corresponding to the first instruction from the register stack. At the same time, the selection index corresponding to the read interconnection circuit is sent to the read interconnection circuit connected to the register stack, and the number of columns storing the at least one operand in the corresponding operand cache is determined by controlling the output terminal information of the data selector in the read interconnection circuit. In addition, the distribution selection address corresponding to the operand cache is sent to the corresponding operand cache, the row number of at least one operand in the operand cache is determined, and then the at least one operand is stored in a cache unit determined by the row number and the column number.

It should be noted that the read interconnection circuit includes multiple data selectors, and the number of data selectors is the same as the number of columns in the operand cache. Multiple data selectors constitute multiple interconnection paths between the register file and the operand cache. Each data selector can select one from at least four single-port SRAMs included in the connected register file and output it to the operand cache under the control of the selection index. The number of columns in the operand cache limits the maximum number of operands read from the register file and the number of data selectors included in the read interconnection circuit. The number of rows in the operand cache is the same as the number of single-port SRAMs in the register file, and each row in the operand cache can store at least one operand corresponding to a first instruction, and the number of rows in the operand cache limits the number of first instructions corresponding to the operands that can be stored in the operand cache.

For example, FIG4 is a connection diagram of a read interconnect circuit provided by an embodiment of the present invention. As shown in FIG4, the register file includes 4 single-port SRAMs, and the distribution of cache units in the operand cache is 4 3, read the interconnect circuit as 4 3, and the first execution corresponds to two operands. For example, the read interconnection circuit includes three data selectors, which means that at most three operands can be read from the register stack including 4 single-port SRAMs. The operands corresponding to the first instructions can be stored in the operand cache at most, and each row stores an operand corresponding to the first instruction. When reading the first operand X, the read-write controller sends a read address to register stack 0, through which operand X can be read from SRAM B0. At the same time, the read-write controller sends a selection index to the data selector 0 in the read interconnection circuit to determine that operand X is to be written to the first column of operand cache 0. In addition, the read-write controller sends a distribution selection address to operand cache 0 to determine that operand X is to be written to the second row of operand cache 0. Therefore, operand X is finally written to the cache unit corresponding to the second row and first column of operand cache 0. The reading and writing process of the second operand Y is different from that of operand X in that the selection index is sent to the data selector 1 in the read interconnect circuit 0 to send the selection index, and the cache unit in the operand cache 0 to which operand Y is written is different from the cache unit in the operand cache to which operand X is written. The reading and writing process of operand Y in the embodiment of the present invention will not be described in detail.

Further, the instruction distribution module determines at most Q second instructions from the cache instructions of the collected operands, including the following steps.

All the first instructions for which operands have been collected are written in parallel into their corresponding to-be-executed instruction tables; the to-be-executed instruction tables correspond one-to-one to all the first instructions.

From all cache instructions corresponding to all instruction tables to be executed, determine at most Q second instructions with no execution conflicts and the best priority combination, the execution conflicts include execution unit conflicts and write conflicts, the execution unit conflicts are used to characterize that the execution units corresponding to any two cache instructions are the same, the write conflicts are used to characterize that the execution results corresponding to any two cache instructions are written to the same register stack at the same time, and the execution units belong to the execution module.

Specifically, FIG. 5 is a schematic diagram of the structure of the instruction distribution module provided by an embodiment of the present invention. As shown in FIG. 5, after receiving N first instructions of collected operands sent by each operand cache unit, the instruction distribution module writes the N first instructions into N to-be-executed instruction tables, that is, writes a first instruction into each to-be-executed instruction table, and the first instruction becomes a cache instruction after being written into the to-be-executed instruction table. Afterwards, the instruction selection logic unit in the instruction distribution unit selects M second instructions with the best priority combination and no execution conflict from all cache instructions in the N to-be-executed instruction tables. The execution unit conflict can be understood as the execution units corresponding to any two cache instructions in the M second instructions are the same, and the two cache instructions cannot call the same execution unit in the execution module for operation at the same time. The write conflict can be understood as the execution results corresponding to any two cache instructions in the M cache instructions are written into the same register stack at the same time when they are written into the N register stacks. Since at least four single-port SRAMs of the register stack can only allow one single-port SRAM to perform a read operation or a write operation at the same time, any two cache instructions cannot be written into the same register stack at the same time. If any two cache instructions have neither instruction unit conflict nor write conflict, it can be considered that the two cache instructions have no execution conflict. If any two cache instructions have at least one of instruction unit conflict and write conflict, it can be considered that the two cache instructions have execution conflict.

For example, when determining at most Q second instructions with no execution conflict and the best priority combination, the first method is: sort all cache instructions of the N to-be-executed instruction tables in order of priority from high to low, traverse each cache instruction in turn according to the sorting result, first determine whether there is an execution conflict between the second cache instruction and the first cache instruction, if there is an execution conflict, continue to traverse the third cache instruction, and determine whether there is an execution conflict between the first cache instruction and the third cache. If there is no execution conflict, the first cache instruction and the second cache instruction form a cache instruction group, continue to traverse the third cache instruction, and determine whether there is an execution conflict between the two cache instructions in the cache instruction group and any two cache instructions in the third cache instruction. If there is no execution conflict, add the third cache instruction to the cache instruction group. If there is an execution conflict, continue to traverse the fourth cache instruction, and the cache instruction group remains unchanged. Repeat the above operation until the cache instruction group includes M cache instructions, and stop, and all the M cache instructions in the cache instruction group are determined as M second instructions. The second method is: first, according to the numbering order of the N to-be-executed instruction tables, the cache instructions in each to-be-executed instruction table are traversed in turn, and multiple target cache instructions without execution conflicts are determined from the N to-be-executed instruction tables. The process of judging the execution conflicts is the same as the first method, and the embodiment of the present invention will not be repeated here. After determining the multiple target cache instructions, the multiple target cache instructions are sorted in order from high to low priority, and the top M target cache instructions are determined as M second instructions. The embodiment of the present invention does not limit the method for determining the M second instructions.

It should be noted that after the M second instructions are determined from all cached instructions, the M second instructions need to be deleted from the N to-be-executed instruction tables to avoid repeated execution of the M second instructions in subsequent cycles.

In addition, the instruction distribution module is also connected to the instruction scheduling module. After determining M second instructions and sending the M second instructions to Q execution units in the execution module respectively, the instruction distribution module can feed back instruction distribution information to the instruction scheduling module.

Furthermore, the execution module includes at least two execution units, the at least two execution units correspond to all the second instructions, and the at least two execution units are both connected to a write interconnection circuit and the operand interconnection circuit, and the write interconnection circuit connects the at least two groups of register files.

For each of the execution units, the execution unit that receives the second instruction is used to determine the corresponding target operand cache based on the second instruction; determine the target operand from the target operand cache based on the operand interconnection circuit; execute the second instruction based on the target operand, determine the execution result, and write the execution result into the register stack corresponding to the second instruction through the write interconnection circuit.

Specifically, the execution module includes Q execution units, which can be understood as the operation units included in the SIMT processor. After the instruction distribution module determines M second instructions, they are sent to M execution units respectively. When M=Q, it means that each execution unit receives a second instruction. When M is less than Q, it means that there may be an execution unit that has not received the second instruction. Afterwards, each execution unit that receives the second instruction executes its own second instruction in parallel. For each execution unit, the following steps are performed.

FIG6 is a connection diagram of an execution module provided by an embodiment of the present invention. As shown in FIG6 , the execution unit first determines the target operand cache storing the target operand corresponding to the second instruction through the second instruction. Afterwards, the target operand corresponding to the second instruction is read from the target operand cache through the operand interconnection circuit, and the number of the target operands may be at least one. After obtaining the target operand, the second instruction may be executed according to the target operand, the execution result of the second instruction may be determined, and the result may be written into the register stack corresponding to the second instruction through the write interconnection circuit.

Optionally, the execution unit includes but is not limited to: an integer operation unit, a floating point operation unit, a memory access unit and a special operation unit.

An embodiment of the present invention further provides an instruction processing method, which is applied to a SIMT processor supporting multiple transmissions as described in any one of the above items. FIG. 7 is a flow chart of the instruction processing method provided by an embodiment of the present invention. As shown in FIG. 7 , the method includes steps 710 to 740.

Step 710: Group multiple thread groups using an instruction scheduling module to determine first instructions corresponding to at least two groups; the first instructions corresponding to the at least two groups correspond to at least two register stacks in a one-to-one manner.

Step 720: Utilize the operand collection module to collect operands corresponding to all first instructions from the at least two groups of register files in parallel, and send all first instructions to the instruction distribution module.

Step 730: Determine at most Q second instructions from the cache instructions of the collected operands using the instruction distribution module, where Q is determined based on the number of execution units in the execution module; the cache instructions at least include all the first instructions.

Step 740: Utilize the execution module to execute the at most Q second instructions in parallel.

The instruction processing method provided by the embodiment of the present invention groups multiple thread groups through an instruction scheduling module, and determines the first instructions corresponding to each of at least two groups. The operand collection module collects operands corresponding to all first instructions corresponding to at least two register stacks in parallel from at least two register stacks, and sends all first instructions with collected operands to the instruction distribution module. The instruction distribution module determines at most Q second instructions from the cache instructions including all first instructions, so that the execution module executes at most Q second instructions in parallel. The present invention ensures the realization of multi-launch capability from the aspects of the number of instructions, the storage of operand groups corresponding to each register stack, and the parallel execution composed of the instruction scheduling module, the operand collection module, the instruction distribution module and the execution module, thereby improving the instruction execution efficiency.

The embodiment of the present invention further provides a chip, comprising at least two SIMT processors supporting multiple transmissions as described in any one of the above items. The SIMT processors supporting multiple transmissions are interconnected.

Optionally, the chip may include a GPU or an AI processor, which is not limited in the embodiments of the present invention.

On the other hand, the present invention also provides a computer program product, which includes a computer program. The computer program can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by each SIMT processor supporting multiple transmissions, the computer can execute the instruction processing method provided by the above-mentioned methods, and the method includes the following steps.

An instruction scheduling module is used to group multiple thread groups, and first instructions corresponding to at least two groups are determined; the first instructions corresponding to the at least two groups correspond to at least two register stacks in a one-to-one manner.

The operands corresponding to all the first instructions are collected in parallel from the at least two groups of register files by using the operand collection module, and all the first instructions are sent to the instruction distribution module.

The instruction distribution module is used to determine at most Q second instructions from cache instructions of collected operands, where Q is determined based on the number of execution units in the execution module; the cache instructions at least include all the first instructions.

The execution module is used to execute the at most Q second instructions in parallel.

On the other hand, the present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon. When the computer program is executed by each SIMT processor supporting multiple transmissions, the instruction processing method provided by the above methods is implemented, and the method includes the following steps.

An instruction scheduling module is used to group multiple thread groups, and first instructions corresponding to at least two groups are determined; the first instructions corresponding to the at least two groups correspond to at least two register stacks in a one-to-one manner.

The operands corresponding to all the first instructions are collected in parallel from the at least two groups of register files by using the operand collection module, and all the first instructions are sent to the instruction distribution module.

The instruction distribution module is used to determine at most Q second instructions from cache instructions of collected operands, where Q is determined based on the number of execution units in the execution module; the cache instructions at least include all the first instructions.

The execution module is used to execute the at most Q second instructions in parallel.

The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative labor.

Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, can also be implemented by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM/RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims (9)

1. A SIMT processor supporting multiple issues, characterized in that it comprises: at least two groups of register files, an instruction scheduling module, an operand collection module, an instruction distribution module and an execution module, wherein: The instruction scheduling module is connected to the operand collection module, and is used to group the multiple thread groups and determine the first instructions corresponding to at least two groups; the first instructions corresponding to the at least two groups correspond to the at least two register files in a one-to-one manner; The operand collection module is connected to the at least two groups of register files and the instruction distribution module, and is used to collect operands corresponding to all first instructions from the at least two groups of register files in parallel, and send all first instructions to the instruction distribution module; The instruction distribution module is connected to the execution module, and the instruction distribution module is used to determine at most Q second instructions from the cache instructions of the collected operands, where Q is determined based on the number of execution units in the execution module; the cache instructions at least include all the first instructions; The execution module is used to execute the at most Q second instructions in parallel; Each of the register files stores operands corresponding to each of the first instructions; The operand collection module includes at least two operand collection units and at least two operand caches, wherein: The at least two operand collection units are connected to the read-write controller, and there is a corresponding relationship between the at least two operand collection units, the at least two operand caches and the at least two groups of register stacks. The at least two operand collection units are used to determine the read requests corresponding to all the first instructions in parallel, and send each of the read requests to the read-write controller; Each of the read requests is used to instruct the read/write controller to determine operands corresponding to all the first instructions in parallel from the at least two groups of register files, and write the operands corresponding to each of the first instructions into the corresponding operand cache. 2. The SIMT processor supporting multiple issues according to claim 1, wherein the instruction scheduling module groups the multiple thread groups and determines the first instructions corresponding to at least two groups, respectively, including: Grouping the instructions of the multiple thread groups to obtain at least two groups and first instructions to be tested corresponding to the at least two groups; the first instructions to be tested corresponding to the at least two groups correspond to the at least two register files in a one-to-one manner; Based on the register occupancy table and the operand occupancy table corresponding to the at least two groups respectively, determining the executable instruction groups corresponding to the at least two groups respectively from the first instructions to be tested corresponding to the at least two groups respectively in parallel; The instruction with the highest priority in each group of the executable instructions is determined as the first instruction corresponding to each of the at least two groups. 3. The SIMT processor supporting multiple transmissions according to claim 2, characterized in that the step of determining the executable instruction groups corresponding to the at least two groups in parallel from the first instructions to be tested corresponding to the at least two groups based on the register occupancy table and the operand occupancy table corresponding to the at least two groups respectively comprises: Based on the register occupancy tables corresponding to the at least two groups, determining whether the first instruction to be tested corresponding to each group of the groups has a register read/write dependency, and obtaining a first determination result of the first instruction to be tested corresponding to each group of the groups; Based on the operand occupancy tables corresponding to the at least two groups, respectively, determining whether there are remaining positions in the operand cache unit range corresponding to the first instruction to be tested corresponding to each group of the groups, and obtaining a second determination result of the first instruction to be tested corresponding to each group of the groups; Based on the first judgment result and the second judgment result corresponding to each group of the groups, the executable instruction groups corresponding to the at least two groups are determined in parallel. 4. The SIMT processor supporting multiple issues according to any one of claims 1 to 3, characterized in that the at least two operand caches are further connected to an operand interconnection circuit and at least two read interconnection circuits, the operand interconnection circuit is connected to the execution module, and the at least two read interconnection circuits are correspondingly connected to the at least two groups of register files; The read/write controller determines operands corresponding to all the first instructions from the at least two groups of register files in parallel, and writes the operands corresponding to all the first instructions into the corresponding operand cache, including: For each of the read requests, the read-write controller is used to determine the operand address in the read request corresponding to the first instruction; the operand address includes the read address corresponding to the register stack, the selection index corresponding to the read interconnection circuit, and the distribution selection address corresponding to the operand cache; based on the read address corresponding to the register stack, the operand is read from the corresponding register stack; based on the selection index corresponding to the read interconnection circuit and the distribution selection address corresponding to the operand cache, the cache unit corresponding to the operand is determined in the operand cache; and the operand is written into the cache unit. 5. The SIMT processor supporting multiple issues according to any one of claims 1 to 3, characterized in that the instruction dispatch module determines at most Q second instructions from the cache instructions of the collected operands, comprising: Writing all the first instructions of the collected operands into their corresponding to-be-executed instruction tables in parallel; the to-be-executed instruction tables correspond one-to-one to all the first instructions; From all cache instructions corresponding to all instruction tables to be executed, determine at most Q second instructions with no execution conflicts and the best priority combination, the execution conflicts include execution unit conflicts and write conflicts, the execution unit conflicts are used to characterize that the execution units corresponding to any two cache instructions are the same, the write conflicts are used to characterize that the execution results corresponding to any two cache instructions are written to the same register stack at the same time, and the execution units belong to the execution module. 6. The SIMT processor supporting multiple issues according to claim 4, characterized in that the execution module comprises at least two execution units, the at least two execution units correspond to the at most Q second instructions, and the at least two execution units are both connected to a write interconnection circuit and the operand interconnection circuit, and the write interconnection circuit connects the at least two groups of register files; For each of the execution units, the execution unit that receives the second instruction is used to determine the corresponding target operand cache based on the second instruction; determine the target operand from the target operand cache based on the operand interconnection circuit; execute the second instruction based on the target operand, determine the execution result, and write the execution result into the register stack corresponding to the second instruction through the write interconnection circuit. 7. An instruction processing method, characterized in that it is applied to the SIMT processor supporting multiple issues as claimed in any one of claims 1 to 6, and the method comprises: Using an instruction scheduling module to group the plurality of thread groups, and determining first instructions corresponding to at least two groups, wherein the first instructions corresponding to the at least two groups correspond to at least two register stacks in a one-to-one manner; Using the operand collection module to collect operands corresponding to all first instructions from the at least two groups of register files in parallel, and sending all first instructions to the instruction distribution module; Determine, by the instruction distribution module, at most Q second instructions from the cache instructions of the collected operands, where Q is determined based on the number of execution units in the execution module; the cache instructions at least include all the first instructions; Execute the at most Q second instructions in parallel using an execution module; Each of the register files stores operands corresponding to each of the first instructions; The operand collection module includes at least two operand collection units and at least two operand caches, wherein: The at least two operand collection units are connected to the read-write controller, and there is a corresponding relationship between the at least two operand collection units, the at least two operand caches and the at least two groups of register stacks. The at least two operand collection units are used to determine the read requests corresponding to all the first instructions in parallel, and send each of the read requests to the read-write controller; Each of the read requests is used to instruct the read/write controller to determine operands corresponding to all the first instructions in parallel from the at least two groups of register files, and write the operands corresponding to each of the first instructions into the corresponding operand cache. 8. A chip, characterized by comprising at least two SIMT processors supporting multiple transmissions according to any one of claims 1 to 6. 9. A non-transitory computer-readable storage medium having a computer program stored thereon, wherein the computer program implements the instruction processing method according to claim 7 when executed by a SIMT processor supporting multiple issues.