CN118349187B

CN118349187B - System mode control method and storage device

Info

Publication number: CN118349187B
Application number: CN202410764371.0A
Authority: CN
Inventors: 姚冬冬; 曹快; 吴宗霖; 朱启傲
Original assignee: Hefei Kaimeng Technology Co ltd
Current assignee: Hefei Kaimeng Technology Co ltd
Priority date: 2024-06-14
Filing date: 2024-06-14
Publication date: 2024-09-17
Anticipated expiration: 2044-06-14
Also published as: CN118349187A

Abstract

The invention provides a system mode control method and a storage device. The method comprises the following steps: monitoring the state of the storage device in a time range to obtain a plurality of time interval information, wherein each time interval information is reflected in the time range, and the time length between a first time point when the storage device finishes processing a previous instruction and a second time point when the storage device acquires a next instruction; obtaining power consumption evaluation information corresponding to a plurality of candidate time thresholds according to the plurality of time interval information; determining one of a plurality of candidate time thresholds as a first target time threshold according to the power consumption evaluation information; and controlling the storage device to enter a low power consumption mode according to the first target time threshold when the storage device is in the idle mode. Therefore, the power consumption of the storage device during operation can be effectively reduced.

Description

System mode control method and storage device

Technical Field

The present invention relates to a control technology of a storage device, and in particular, to a system mode control method and a storage device.

Background

The storage device including a flash memory is a nonvolatile storage device and is widely applied to electronic devices such as a memory card, a solid state disk, a portable multimedia player (portable multimedia players) and the like. In modern electronic devices, low power design is an important area of research, particularly in firmware design for memory devices, where the firmware typically switches to a low power mode when the system is idle for a long period of time to save energy and extend device life.

Conventional low power mode implementations are configured to automatically enter a low power state by setting a fixed time threshold when the device is not active within the time threshold. However, this method of fixing the threshold lacks flexibility, and cannot be adjusted according to the actual use situation of the device, which may result in wasting energy and reducing the performance of the device in some situations, such as when the idle time of the system is far longer than the set time threshold, and higher power consumption is caused if the time threshold is not adjusted.

Disclosure of Invention

The invention provides a system mode control method and a storage device, which can improve the problems and effectively reduce the power consumption of the storage device during operation under the condition that the performance of the storage device is not affected as much as possible.

An embodiment of the present invention provides a system mode control method for a storage device, including: monitoring the state of the storage device in a time range to obtain a plurality of time interval information, wherein each time interval information in the plurality of time interval information is reflected in the time range, and the time length of the storage device from a first time point when a previous instruction is processed to a second time point when a next instruction is executed; obtaining a plurality of power consumption evaluation information corresponding to a plurality of candidate time thresholds according to the plurality of time interval information; determining a first target time threshold value in the candidate time threshold values according to the power consumption evaluation information; and when the storage device is in the idle mode, controlling the storage device to enter a low power consumption mode according to the first target time threshold.

The embodiment of the invention further provides a storage device, which comprises a connection interface unit, a memory module and a memory controller. The connection interface unit is used for being connected to a host system. The memory controller is connected to the connection interface unit and the memory module. The memory controller is to: monitoring the state of the storage device in a time range to obtain a plurality of time interval information, wherein each time interval information in the plurality of time interval information is reflected in the time range, and the time length between a first time point when a previous instruction is processed and a second time point when a next instruction is acquired by the storage device; obtaining a plurality of power consumption evaluation information corresponding to a plurality of candidate time thresholds according to the plurality of time interval information; determining a first target time threshold value in the candidate time threshold values according to the power consumption evaluation information; and when the storage device is in the idle mode, controlling the storage device to enter a low power consumption mode according to the first target time threshold.

Drawings

FIG. 1 is a schematic diagram of a memory device according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of a managed memory module shown in accordance with an embodiment of the present invention;

FIG. 3 is a schematic diagram illustrating a memory device operating in different system modes at different points in time according to an embodiment of the present invention;

FIG. 4 is a schematic diagram showing monitoring of states of a storage device within a preset time range to obtain a plurality of time interval information according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of power consumption assessment information corresponding to a plurality of candidate time thresholds, shown in accordance with an embodiment of the present invention;

FIG. 6 is a schematic diagram of tabular data shown in accordance with an embodiment of the present invention;

Fig. 7 is a flowchart of a system mode control method according to an embodiment of the present invention.

Detailed Description

Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.

FIG. 1 is a schematic diagram of a memory storage device according to an embodiment of the present invention. Referring to fig. 1, the data storage system includes a storage device 10 and a host system 11. The host system 11 may be any type of computer system, such as a smart phone, a tablet computer, a notebook computer, a desktop computer, an industrial computer, a game machine, a server, or a vehicle computer, and the type of the host system 11 is not limited thereto.

The storage device 10 is connected to the host system 11 and is used to store data from the host system 11. For example, the storage device 10 may include a solid state disk, a USB flash drive, a memory card, or other type of non-volatile storage device. The host system 11 may communicate with the storage device 10 via an embedded multimedia card (embedded Multi-MEDIA CARD, EMMC), universal flash memory (Universal Flash Storage, UFS), peripheral component interconnect Express (PERIPHERAL COMPONENT INTERCONNECT EXPRESS, PCI Express), non-volatile memory Express (Non-Volatile Memory Express, NVM Express), serial advanced technology attachment (SERIAL ADVANCED Technology Attachment, SATA), universal serial bus (Universal Serial Bus, USB), or other types of connection interface standards. Thus, host system 11 may store data to storage device 10 and/or read data from storage device 10.

The memory device 10 includes a connection interface unit 101, a memory module 102, and a memory controller 103. The connection interface unit 101 is used to connect the storage device 10 to the host system 11. For example, the connection interface unit 101 may support connection interface standards such as eMMC, UFS, PCI Express, NVM Express, SATA, PCI Express, or USB. The storage device 10 may communicate (e.g., exchange signals, instructions, and/or data) with the host system 11 via the connection interface unit 101.

The memory module 102 is used to store data. The memory module 102 may include one or more rewritable non-volatile memory modules. Each of the rewritable non-volatile memory modules may include one or more memory cell arrays. Memory cells in a memory cell array store data in the form of voltages (also referred to as threshold voltages). For example, the memory module 102 may include a single level memory cell (SINGLE LEVEL CELL, SLC) NAND type flash memory module, a second level memory cell (Multi LEVEL CELL, MLC) NAND type flash memory module, a third level memory cell (TRIPLE LEVEL CELL, TLC) NAND type flash memory module, a fourth level memory cell (Quad LEVEL CELL, QLC) NAND type flash memory module, and/or other memory modules having the same or similar characteristics.

The memory controller 103 is connected to the connection interface unit 101 and the memory module 102. The memory controller 103 may be regarded as a control core of the memory device 10 and is used to control the memory device 10. For example, the memory controller 103 may be responsible for controlling and/or managing the operation of all or a portion of the memory device 10. For example, the memory controller 103 may include a central processing unit (Central Processing Unit, CPU), or other programmable general purpose or special purpose microprocessor, digital signal Processor (DIGITAL SIGNAL Processor, DSP), programmable controller, application SPECIFIC INTEGRATED Circuits (ASIC), programmable logic device (Programmable Logic Device, PLD), or other similar device or combination of devices. In one embodiment, memory controller 103 comprises a flash memory controller.

In one embodiment, the memory controller 103 may further include a buffer memory, a power management circuit, an encoding circuit, a decoding circuit, and/or other types of various circuit modules, which are not limiting of the present invention. The buffer memory is used for buffering data. The power management circuit is used for managing the power of the memory device 10. The encoding circuit is used for encoding the data to be stored in the memory module 102 to generate an error correction code (and/or an error check code). The decoding circuit is used for decoding the data read from the memory module 102 to correct possible errors in the read data. For example, the encoding circuit and/OR decoding circuit may encode and decode data using various encoding/decoding algorithms such as Low-density parity check (LDPC) codes, BCH codes, reed-solomon (RS) codes, exclusive OR (XOR) codes, and the like.

The memory module 102 may receive a sequence of instructions from the memory controller 103 and access the memory unit according to the sequence of instructions. For example, when data is to be stored, the memory controller 103 may send a write command sequence to the memory module 102 to instruct the memory module 102 to store the data into a specific memory cell. When data is to be read, the memory controller 103 may send a read command sequence to the memory module 102 to instruct the memory module 102 to read the data from a specific memory cell. When data is to be deleted, the memory controller 103 may send an erase command sequence to the memory module 102 to instruct the memory module 102 to erase the data stored in a specific memory cell. In addition, the memory controller 103 may also send other types of instruction sequences to the memory module 102 to instruct the memory module 102 to perform corresponding operations, which is not limited by the present invention.

FIG. 2 is a schematic diagram illustrating managing memory modules according to an embodiment of the invention. Referring to fig. 1 and 2, the memory module 102 includes a plurality of physical units 201 (1) to 201 (B). Each physical unit comprises a plurality of memory cells and is used for nonvolatile memory data.

In one embodiment, a physical unit may include one or more physical programming units. For example, a physical programming unit may include a plurality of physical sectors (sectors). For example, a physical sector may have a data size of 512 Bytes (Bytes, B), and a physical programming unit may include 8 physical sectors. However, the data capacity of one physical fan and/or the total number of physical fans included in one physical programming unit can be adjusted according to the practical requirements, and the present invention is not limited thereto. In one embodiment, a physical programmer may be considered a physical page. For example, the data capacity of one physical programming unit may be 4 kilobytes (4 KB), and the present invention is not limited thereto.

In one embodiment, one physical programmer is the minimum unit of synchronous write data in the memory module 102. For example, when performing a programming operation on a physical programming unit to write data into the physical programming unit, a plurality of memory units in the physical programming unit may be synchronously programmed to store corresponding data. For example, when programming a physical programming unit, a write voltage may be applied to the physical programming unit to change the threshold voltage of at least some of the memory cells in the physical programming unit. The threshold voltage of each memory cell may reflect the bit data stored by the memory cell.

In one embodiment, a physical erase unit may include a plurality of physical program units. Multiple memory cells in a physically erased cell may be erased simultaneously. For example, when performing an erase operation on a physical erased cell, erase voltages may be applied to a plurality of physical programmed cells in the physical erase recipe to change the threshold voltage of at least some of the physical programmed cells and to erase bit data stored in the physical programmed cells.

In one embodiment, the memory controller 103 may logically associate the physical units 201 (1) -201 (A) to the data area 21 and the physical units 201 (A+1) -201 (B) to the spare (spare) area 22. The entity units 201 (1) -201 (a) in the data area 21 are used to store data (also referred to as user data) from the host system 11. For example, each entity unit in the data area 21 may store valid (valid) data and/or invalid (invalid) data. In addition, the physical units 201 (A+1) -201 (B) in the idle area 22 do not store data.

In one embodiment, if a certain physical unit does not store valid data, the physical unit may be associated with the idle area 22. In one embodiment, the free area 22 is also referred to as a free pool (free pool). In addition, the physical cells associated with the inactive region 22 may be erased to erase the data in the physical cells.

In one embodiment, when there is data (i.e., user data) from host system 11 to be stored, memory controller 103 may select one or more physical units from idle region 22 and instruct memory module 102 to store data from host system 11 in the selected physical units. Meanwhile, the selected entity units may be associated to the data area 21.

In one embodiment, the memory controller 103 may configure a plurality of logic units 202 (1) -202 (C) to map the physical units 201 (1) -201 (A) in the data area 21. For example, a logical unit may correspond to a logical block address (Logical Block Address, LBA) or other logical management unit. One logical unit may be mapped to one or more physical units in the data area 21.

In one embodiment, if a physical unit is currently mapped by any logical unit, the memory controller 103 may determine that the data currently stored by the physical unit includes valid data. Conversely, if a physical unit is not currently mapped by any logical unit, the memory controller 103 may determine that the physical unit does not currently store any valid data (and/or that the data in the physical unit is invalid).

In one embodiment, the memory controller 103 may record the mapping relationship between the logical unit and the physical unit in a logical-to-physical mapping table. When an access instruction (e.g., a read instruction, a write instruction, a delete instruction, or other type of instruction) is received from the host system 11, the memory controller 103 may instruct the memory module 102 to perform a corresponding operation according to the information in the logical-to-physical mapping table.

In one embodiment, the memory controller 103 may control the memory device 10 to operate in one of a normal operation mode, an idle mode, and a low power consumption mode. In one embodiment, in the normal operating mode, the memory controller 103 may perform corresponding operational actions according to instructions (also referred to as commands) from the host system 11. For example, in accordance with a read instruction from host system 11, memory controller 103 may send a read instruction sequence to memory module 102 to read data from memory module 102. According to the write instruction from the host system 11, the memory controller 103 may send a write instruction sequence to the memory module 102 to write data to the memory module 102. Alternatively, based on erase instructions from host system 11, memory controller 103 may send erase instruction sequences to memory module 102 to erase data from memory module 102. In addition, memory controller 103 may control memory device 10 to perform other types of operational activities in accordance with other types of instructions from host system 11, as the invention is not limited.

In one embodiment, in the normal operation mode, the storage device 10 may automatically enter the idle mode when a certain instruction is processed (i.e., the operation behavior for the certain instruction is completed). In idle mode, the storage device 10 may be in an idle state. For example, in idle mode, memory controller 103 does not perform operational actions for any instructions from host system 11. In particular, the power consumption of the memory device 10 in the idle mode may be lower than the power consumption of the memory device 10 in the normal operation mode. For example, this power consumption may be positively correlated to the power consumption per unit time of the memory device 10.

In one embodiment, in idle mode, the memory controller 103 may determine whether the cumulative length of time the memory device 10 is operating in idle mode reaches (e.g., is greater than or equal to) a time threshold (also referred to as a handoff time threshold). If the accumulated time length reaches the switching time threshold, the memory controller 103 may control the system of the memory device 10 to enter the low power consumption mode. In particular, the power consumption of the memory device 10 in the low power consumption mode may be lower than the power consumption of the memory device 10 in the idle mode. However, if this accumulated time length does not reach (e.g., is less than) the switching time threshold, the memory controller 103 may not control the memory device 10 to enter the low power consumption mode.

In one embodiment, the memory controller 103 may start a timer when entering idle mode. The timer value of this timer may reflect the cumulative length of time the memory device 10 is operating in idle mode. In one embodiment, the memory controller 103 may compare this timing value to a switch time threshold. If the timing value reaches the switching time threshold, the memory controller 103 can control the memory device 10 to enter the low power mode. However, if this timing value does not reach the switch time threshold, the memory controller 103 may not control the system of the memory device 10 to enter the low power consumption mode.

In one embodiment, in the low power mode, when an instruction from the host system 11 is fetched, the memory controller 103 may control the memory device 10 to exit the low power mode and return to the normal operation mode. After returning to the normal operating mode, the memory controller 103 may perform an operational behavior corresponding to this instruction in the normal operating mode.

FIG. 3 is a schematic diagram illustrating a memory device operating in different system modes at different points in time according to an embodiment of the present invention. Referring to fig. 3, in one embodiment, it is assumed that at time T (1), the memory controller 103 processes the instruction a. After point in time T (1), the storage device 10 may automatically enter an idle mode. After entering the idle mode, assuming at a point in time T (2), the memory controller 103 determines that the accumulated length of time the memory device 10 is operating in the idle mode reaches the switching time threshold. After the time point T (2), the memory controller 103 controls the memory device 10 to enter the low power consumption mode. For example, between the time points T (2) and T (3) (i.e., within the time range Δt (1)), the memory controller 103 controls the storage device 10 to execute a preparation job to enter the low power consumption mode. For example, during the time range ΔT (1), the memory controller 103 may shut down some of the electronic circuitry of the memory device 10 and/or adjust operating parameters of some of the electronic circuitry of the memory device 10. At a time point T (3), the memory controller 103 completes the preparation job to enter the low power consumption mode. After the time point T (3), the memory device 10 starts to operate in the low power consumption mode. For example, between time points T (3) and T (4), the memory device 10 operates in a low power consumption mode.

In one embodiment, assume that at time T (4), memory controller 103 retrieves instruction B. Between time points T (4) and T (5) (i.e., within the time range Δt (2)), the memory controller 103 performs a preparation job to exit the low power consumption mode. For example, during time range ΔT (2), memory controller 103 may activate portions of the electronic circuitry of memory device 10 and/or adjust operating parameters of portions of the electronic circuitry of memory device 10 to restore memory device 10 to a normal operating mode. At a time point T (5), the memory controller 103 completes the preparation job to exit the low power consumption mode. After the point in time T (5), the memory device 10 is re-operated in the normal operation mode to perform the operation behavior corresponding to the instruction B.

It should be noted that, in the embodiment of fig. 3, although the power consumption of the memory device 10 operating in the low power consumption mode may be lower than the power consumption of the memory device 10 operating in the idle mode, additional power consumption may be generated when the memory controller 103 performs the preparation operation to enter and exit the low power consumption mode. Therefore, in practice, the storage device 10 is controlled to enter the low power consumption mode according to the fixed or not properly configured switching time threshold, and the storage device 10 may not always enter the low power consumption mode due to the excessively large switching time threshold, or the storage device 10 may perform the preparation operation for entering and exiting the low power consumption mode excessively frequently due to the excessively small switching time threshold, so that the power consumption of the storage device 10 may not be reduced or increased. Both of the above-described defect states violate the objective of initially setting the low power mode to reduce the power consumption of the memory device 10. Therefore, how to effectively maintain the practicability of the low power mode and avoid the additional power consumption increase of the memory device 10 caused by the excessively frequent entering and exiting of the low power mode in the changeable command transmission environment between the host system 11 and the memory device 10 is one of the problems that those skilled in the art need to improve.

In one embodiment, the memory controller 103 may monitor the status of the memory device 10 over a time range to obtain a plurality of time interval information. For example, each of the plurality of time interval information may be reflected in a time range, and the time length between the time point (also referred to as a first time point) when the previous instruction is processed and the time point (also referred to as a second time point) when the next instruction is acquired by the storage device 10. Taking fig. 3 as an example, the first time point and the second time point may be time points T (1) and T (4), respectively. However, the length of time between the first time point and the second time point reflected by each of the time interval information may be at least partially the same or different, which is not limited by the present invention.

In an embodiment, the memory controller 103 may configure multiple time thresholds (also referred to as candidate time thresholds). The plurality of candidate time thresholds may be different. In an embodiment, the memory controller 103 may set one of the plurality of candidate time thresholds as the switch time threshold.

It may be appreciated that, for the acquisition of the candidate time threshold, the time interval information with the longest time length is equally divided according to the preset divided portions, one divided time length is taken as one candidate time threshold, two divided time lengths are taken as another candidate time threshold, and so on, the present application is not limited in detail herein.

In an embodiment, the memory controller 103 may obtain a plurality of power consumption evaluation information corresponding to the plurality of candidate time thresholds according to the plurality of time interval information. For example, the power consumption evaluation information may at least reflect an estimated total power consumption of the memory device 10 over the time range if a certain candidate time threshold of the plurality of candidate time thresholds is taken as a switching time threshold. For example, this total power consumption may include a sum of estimated power consumption of the memory device 10 operating in the idle mode, power consumption of the memory device 10 operating in the low power mode, and power consumption of the memory device 10 performing a preparation job to and from the low power mode over the time frame. In an embodiment, the memory controller 103 may determine one of the candidate time thresholds as the first target time threshold according to the power consumption evaluation information. In an embodiment, the memory controller 103 may determine a first target time threshold of the plurality of candidate time thresholds based on the plurality of power consumption evaluation information. The first target time threshold is a candidate time threshold corresponding to the power consumption evaluation information which performs optimally among the plurality of power consumption evaluation information. Thereafter, when the memory device 10 is in the idle mode, the memory controller 103 may control the memory device 10 to enter the low power consumption mode (or to remain in the idle mode) according to the first target time threshold. For details of how to control the storage device 10 to enter the low power consumption mode according to the first target time threshold, reference may be made to the embodiment of fig. 3, where the first target time threshold is taken as the switching time threshold, and detailed description is omitted herein.

In an embodiment, each power consumption evaluation information reflects the estimated total power consumption of the storage device in the time range when the corresponding candidate time threshold is taken as the switching time threshold, wherein the switching time threshold is the time length for the storage device to enter the low power consumption mode from the idle mode.

In an embodiment, the memory controller 103 may calculate the first total power consumption corresponding to the plurality of time interval information by using each of the candidate time thresholds as the switching time threshold. The memory controller 103 may then determine each of the first total power consumption as the power consumption evaluation information corresponding to the candidate time threshold.

In an embodiment, the memory controller 103 may divide the idle duration, the mode transition duration, and the low power consumption duration in the plurality of time interval information by using each of the candidate time thresholds as the switching time threshold. The memory controller 103 may correspondingly obtain an idle mode power consumption value, a mode conversion power consumption value, and a low power consumption mode power consumption value according to the idle time period, the mode conversion time period, and the low power consumption time period. The memory controller 103 may then determine the first total power consumption corresponding to each of the candidate time thresholds based on the idle mode power consumption value, the mode transition power consumption value, and the low power mode power consumption value.

In an embodiment, if the plurality of candidate time thresholds includes a first candidate time threshold and a second candidate time threshold, the power consumption evaluation information includes power consumption evaluation information corresponding to the first candidate time threshold (also referred to as first power consumption evaluation information) and power consumption evaluation information corresponding to the second candidate time threshold (also referred to as second power consumption evaluation information). The first power consumption evaluation information may reflect an estimated total power consumption of the memory device 10 in the time range (also referred to as a first candidate total power consumption) if the first candidate time threshold is taken as the switching time threshold. Further, the second power consumption evaluation information may reflect the estimated total power consumption of the storage device 10 in the time range (also referred to as the second candidate total power consumption) if the second candidate time threshold is taken as the switching time threshold.

It will be appreciated that the first candidate time threshold and the second candidate time threshold are defined for ease of illustration of the present application only and are not intended to be limiting.

In an embodiment, the memory controller 103 may obtain an idle mode power consumption value (also referred to as a first idle mode power consumption value), a mode conversion power consumption value (also referred to as a first mode conversion power consumption value), and a low power mode power consumption value (also referred to as a first low power mode power consumption value) according to the plurality of time interval information and the first candidate time threshold. The first idle mode power consumption value, the first mode transition power consumption value, and the first low power mode power consumption value may be sequentially reflected, and if the first candidate time threshold is taken as the switching time threshold, the estimated power consumption of the storage device 10 operating in the idle mode in the time range, the power consumption of the storage device 10 performing the preparation operation to enter and exit the low power mode in the time range, and the power consumption of the storage device 10 operating in the low power mode in the time range are estimated. Then, the memory controller 103 may obtain the first power consumption evaluation information according to the sum of the first idle mode power consumption value, the first mode transition power consumption value, and the first low power consumption mode power consumption value.

In an embodiment, the memory controller 103 may obtain another idle mode power consumption value (also referred to as a second idle mode power consumption value), another mode conversion power consumption value (also referred to as a second mode conversion power consumption value), and another low power mode power consumption value (also referred to as a second low power mode power consumption value) according to the plurality of time interval information and the second candidate time threshold. The second idle mode power consumption value, the second mode transition power consumption value, and the second low power mode power consumption value may be sequentially reflected, and if the second candidate time threshold is taken as the switching time threshold, the estimated power consumption of the storage device 10 operating in the idle mode in the time range, the power consumption of the storage device 10 performing the preparation operation to enter and exit the low power mode in the time range, and the power consumption of the storage device 10 operating in the low power mode in the time range are estimated. Then, the memory controller 103 may obtain the second power consumption evaluation information according to the sum of the second idle mode power consumption value, the second mode conversion power consumption value, and the second low power consumption mode power consumption value.

In an embodiment, the memory controller 103 may compare the first power consumption evaluation information with the second power consumption evaluation information to obtain a comparison result. Based on the comparison result, the memory controller 103 may determine one of the first candidate time threshold and the second candidate time threshold as the first target time threshold.

In one embodiment, the comparison may reflect that the first candidate total power consumption is greater than the second candidate total power consumption or that the first candidate total power consumption is less than the second candidate total power consumption. In one embodiment, if the comparison result reflects that the first candidate total power consumption is greater than the second candidate total power consumption, the memory controller 103 may determine the second candidate time threshold as the first target time threshold. Alternatively, in one embodiment, if the comparison result reflects that the first candidate total power consumption is less than the second candidate total power consumption, the memory controller 103 may determine the first candidate time threshold as the first target time threshold.

In an embodiment, the memory controller 103 may compare a plurality of the power consumption evaluation information to obtain target power consumption evaluation information, wherein the target power consumption evaluation information is power consumption evaluation information, which reflects that the total power consumption of the storage device is the lowest in the time range, among the plurality of the power consumption evaluation information. Then, the memory controller 103 may determine the candidate time threshold corresponding to the target power consumption evaluation information as the first target time threshold.

Fig. 4 is a schematic diagram showing monitoring of states of a storage device within a preset time range to obtain a plurality of time interval information according to an embodiment of the present invention. Referring to fig. 4, it is assumed that, within a predetermined time range, the memory controller 103 processes the previous instruction at the time point TP (1) and then obtains the next instruction at the time point TP (1) ' processes the previous instruction at the time point TP (i) and then obtains the next instruction at the time point TP (i) ' and processes the previous instruction at the time point TP (n) and then obtains the next instruction at the time point TP (n) ' at the time point TP (1). Between time points TP (i) and TP (i)' (i.e., within the time range Δtp (i)), the memory device 10 may operate in an idle mode, possibly also into a low power mode. Wherein i is between 1 and n.

In one embodiment, the memory controller 103 may monitor the status of the memory device 10 within the time range to obtain a plurality of time interval information 41 (1) -41 (n). The time interval information 41 (i) corresponds to a time range Δtp (i). For example, the time interval information 41 (i) may reflect the time length of the time range Δtp (i). It should be noted that the time periods corresponding to the time ranges Δtp (1) to Δtp (n) may be different or at least partially the same, which is not limited by the present invention.

Fig. 5 is a schematic diagram showing power consumption evaluation information corresponding to a plurality of candidate time thresholds according to an embodiment of the present invention. Referring to fig. 5, in the embodiment of fig. 4, the memory controller 103 may set a plurality of time thresholds THR (1) to THR (m). Each of the time thresholds THR (1) -THR (m) is a candidate time threshold.

In one embodiment, the memory controller 103 may obtain the power consumption evaluation information W (1) W (m) according to the time interval information 41 (1) 41 (n) of FIG. 4. The power consumption evaluation information W (j) corresponds to a time threshold THR (j), and j is between 1 and m. In particular, the power consumption evaluation information W (j) may reflect the estimated total power consumption of the memory device 10 in the time range if the time threshold THR (j) is used as the switching time threshold.

In one embodiment, the memory controller 103 may compare the power consumption evaluation information W (1) -W (m) to obtain a comparison result. Based on the comparison result, the memory controller 103 determines one of the time thresholds THR (1) to THR (m) as the first target time threshold. For example, assuming that the comparison result reflects that the total power consumption corresponding to the power consumption evaluation information W (j) is the lowest, the memory controller 103 may determine the time threshold THR (j) as the first target time threshold.

In one embodiment, taking the power consumption evaluation information W (j) as an example, the memory controller 103 may obtain the power consumption evaluation information W (j) according to the time interval information 41 (1) -41 (n) and the time threshold THR (j). For example, the memory controller 103 may obtain the power consumption evaluation information W (j) according to the following equation (1.1).

W(j)=W1(j)+W2(j)+W3(j) (1.1)

In equation (1.1), the parameters W1 (j), W2 (j) and W3 (j) are sequentially expressed, and if the time threshold THR (j) is used as the switching time threshold, the estimated power consumption of the memory device 10 in the idle mode, the power consumption of the memory device 10 to perform the preparation operation to enter and exit the low power mode, and the power consumption of the memory device 10 in the low power mode are within the time range. In one embodiment, the parameters W1 (j), W2 (j), and W3 (j) may be sequentially referred to as an idle mode power consumption value, a mode transition power consumption value, and a low power mode power consumption value. It should be noted that equation (1.1) can also be adjusted according to practical requirements, and the invention is not limited thereto.

In one embodiment, the memory controller 103 classifies each of the time interval information 41 (1) to 41 (n) into a first type of time interval information and a second type of time interval information according to the time threshold THR (j). The first type of time interval information reflects a shorter time length than the time threshold THR (j). The second type of time interval information reflects a length of time longer than or equal to the time threshold THR (j). The memory controller 103 may obtain the power consumption evaluation information W (j) according to the total number of the first type of time interval information and/or the total number of the second type of time interval information.

In one embodiment, the memory controller 103 may obtain the parameters W1 (j), W2 (j) and W3 (j) in the equation (1.1) according to the following equations (2.1) - (2.3).

W1(j)=T1×P1+THR(j)×N×P1 (2.1)

W2(j)=N×WT (2.2)

W3(j)=(T2-THR(j)×N-TE×N)×P2 (2.3)

In equations (2.1) - (2.3), parameter T1 represents the length of time reflected by the first type of time interval information in time interval information 41 (1) - (41 (N), parameter P1 represents the power consumption of memory device 10 operating in idle mode per unit time, parameter N represents the total number of second type of time interval information in time interval information 41 (1) - (41 (N), parameter WT represents the power consumption of memory device 10 performing preparation operations to enter and exit the low power consumption mode, parameter T2 represents the length of time reflected by the second type of time interval information in time interval information 41 (1) - (41 (N), parameter TE represents the time required for memory device 10 to enter the low power consumption mode, and parameter P2 represents the power consumption of memory device 10 operating in the low power consumption mode per unit time. It should be noted that equations (2.1) - (2.3) can also be adjusted according to practical requirements, and the invention is not limited.

It should be noted that, the time length of the second type of time interval information applicable to the above formula (2.3) is equal to or greater than THR (j) +te, that is, the sum of the corresponding candidate time interval and the time required for entering the low power consumption mode; when there is second class interval information with a time length less than THR (j) +te, determining the number M of such second class interval information and the reflected time length T3, then the above formula (2.3) may be rewritten as:

W3(j)=(T2-T3-THR(j)×(N-M)-TE×(N-M))×P2 (2.3)

In an embodiment, the memory controller 103 may obtain count information corresponding to a first candidate time threshold (also referred to as first type count information) and count information corresponding to a second candidate time threshold (also referred to as second type count information) according to the plurality of time interval information. For example, the memory controller 103 may associate each of the plurality of time interval information to one of the plurality of candidate time thresholds and update count information corresponding to the candidate time threshold. For example, the memory controller 103 may associate at least one time interval information (also referred to as a first time interval information) of the plurality of time interval information to a first candidate time threshold and correspondingly update the first type count information. The updated first type of count information may reflect a total number of first time interval information. Further, the memory controller 103 may associate at least one time interval information (also referred to as a second time interval information) of the plurality of time interval information to a second candidate time threshold and correspondingly update the second class count information. The updated second type count information may reflect a total number of second time interval information.

In one embodiment, the memory controller 103 may apply a specific algorithm corresponding to the first candidate time threshold according to the first type of count information, the second type of count information, the first candidate time threshold, and the second candidate time threshold to obtain the first power consumption evaluation information. In addition, the memory controller 103 may apply a specific algorithm corresponding to the second candidate time threshold according to the first type count information, the second type count information, the first candidate time threshold, and the second candidate time threshold to obtain the second power consumption evaluation information.

In an embodiment, the memory controller 103 may obtain count information corresponding to each of the candidate time thresholds according to the plurality of time interval information, wherein each count information reflects the number of time interval information associated to the candidate time threshold in the plurality of time interval information. Then, the memory controller 103 may obtain a plurality of the power consumption evaluation information corresponding to a plurality of candidate time thresholds from the count information and the candidate time thresholds.

Fig. 6 is a schematic diagram of tabular data shown in accordance with an embodiment of the present invention. Referring to fig. 6, in one embodiment, the memory controller 103 may create the table data 61 according to the time interval information 41 (1) to 41 (n) of fig. 4. The table data 61 can be used to record the count information C (1) to C (m) corresponding to the time thresholds THR (1) to THR (m), respectively. For example, the count information C (j) corresponds to the time threshold THR (j). In one embodiment, the table data 61 may also be used to record the power consumption evaluation information W (1) W (m).

In one embodiment, the memory controller 103 may associate the time interval information 41 (1) -41 (n) to one of the time thresholds THR (1) -THR (m) one by one. For example, the memory controller 103 may correlate time interval information relatively close to the time threshold THR (j) among the time interval information 41 (1) to 41 (n) to the time threshold THR (j). Then, the memory controller 103 may update the count information C (j) corresponding to the time threshold THR (j). The updated count information C (j) may reflect that several time interval information among the time interval information 41 (1) to 41 (n) are associated to the time threshold THR (j). In addition, the sum of updated count information C (1) to C (m) may be the same as the sum of time interval information 41 (1) to 41 (n). For example, assume that the total number of the time interval information 41 (1) to 41 (n) is "10" (i.e., n=10), and the total number of the time threshold THR (1) to THR (m) is "3" (i.e., m=3). The count information C (1) may reflect that N (1) pieces of time interval information are respectively associated to the time threshold THR (1), the count information C (2) may reflect that N (2) pieces of time interval information are respectively associated to the time threshold THR (2), the count information C (3) may reflect that N (3) pieces of time interval information are respectively associated to the time threshold THR (3), and the sum of N (1), N (2), and N (3) is "10".

In general, the memory controller 103 may associate each of the plurality of time interval information to the closest candidate time threshold and update the corresponding count information, respectively. In addition, time interval information greater than the previous candidate time threshold and equal to or less than the next candidate time threshold may be associated with the next candidate time threshold and the corresponding count information may be updated.

In one embodiment, the memory controller 103 may obtain the power consumption evaluation information W (j) according to the time threshold THR (1) to THR (m) and the count information C (1) to C (m) by applying an algorithm corresponding to the time threshold THR (j). For example, the memory controller 103 may obtain the power consumption evaluation information W (j) according to the following equations (3.1) - (3.4).

W(j)=W1(j)+W2(j)+W3(j) (3.1)

(3.2)

(3.3)

(3.4)

In equations (3.1) - (3.4), the parameter P1 represents the power consumption of the memory device 10 in the idle mode per unit time, the parameter WT represents the power consumption of the memory device 10 to perform the preparation operation to enter and exit the low power consumption mode, the parameter TE represents the time required for the memory device 10 to enter the low power consumption mode, and the parameter P2 represents the power consumption of the memory device 10 in the low power consumption mode per unit time. It should be noted that equations (3.1) - (3.4) may also be adjusted according to practical requirements, and the present invention is not limited thereto.

In one embodiment, for different time thresholds THR (j), the constant j and the time threshold THR (j) in equations (3.1) - (3.4) can be correspondingly adjusted to obtain corresponding power consumption evaluation information W (j). From this, power consumption evaluation information W (1) to W (m) can be obtained by equations (3.1) to (3.4). It should be noted that equations (3.1) - (3.4) may also be adjusted according to practical requirements, and the present invention is not limited thereto.

In an embodiment, the memory controller 103 may take each of the candidate time thresholds as a switching time threshold, and determine that other candidate time thresholds smaller than the switching time threshold are idle mode time and other candidate time thresholds larger than the switching time threshold are low power consumption mode time. The memory controller 103 may obtain the first power consumption according to each idle mode time, the corresponding count information, the switching time threshold, the corresponding count information, and the count information corresponding to the low power consumption mode time; acquiring second power consumption according to the counting information respectively corresponding to the switching time threshold and the low power consumption mode time; and acquiring third power consumption according to each low power consumption mode time, the corresponding counting information and the corresponding switching time threshold. For example, the parameters W1 (j), W2 (j), and W3 (j) in equation (3.1) may correspond to the first power consumption, the second power consumption, and the third power consumption, respectively. Then, the memory controller 103 may determine power consumption evaluation information corresponding to each of the candidate time thresholds according to the first power consumption, the second power consumption, and the third power consumption. For example, the memory controller 103 may obtain the power consumption evaluation information W (j) corresponding to each of the candidate time thresholds according to equations (2.1) - (2.3) or (3.1) - (3.4).

By the method, the power consumption evaluation information of each candidate time threshold is calculated, so that the requirement on the system computing capacity can be reduced, the occupation of system computing resources is reduced, and the computing speed is improved.

As shown in fig. 6, if the candidate time threshold THR (j) is selected as the switching time threshold, the corresponding count information is C (j), and THR (1) -THR (j-1) are candidate time thresholds named idle mode time, and the corresponding count information is C (1) -C (j-1); THR (j+1) -THR (m) are candidate time thresholds named as low-power-consumption mode time, and corresponding counting information is C (j+1) -C (m).

In an embodiment, the memory controller 103 may obtain the total duration of the storage device in the idle mode based on each of the idle mode time, the switching time threshold, the low power consumption mode time, and the count information corresponding to each. And acquiring the first power consumption according to the idle power and the total duration of the storage device in the idle mode. For specific details, reference may be made to equations (2.1) and (3.2), and the invention is not limited thereto.

In an embodiment, the memory controller 103 may acquire the second power consumption based on the mode switching power consumption and the count information respectively corresponding to the switching time threshold and the low power consumption mode time. For specific details, reference may be made to equations (2.2) and (3.3), and the invention is not limited thereto.

In an embodiment, the memory controller 103 may obtain the total duration of the memory device 10 in the low power mode based on each of the low power mode times and the corresponding count information and the switching time threshold. The memory controller 103 may obtain the third power consumption based on the low power consumption power and the total duration of the memory device 10 in the low power consumption mode. For specific details, reference may be made to equations (2.3) and (3.4), and the invention is not limited thereto.

Specifically, as shown in (3.4), when the total duration of the storage device in the low power mode is calculated, it is necessary to eliminate the time TE for entering the low power mode. Therefore, the time length of the low power mode time in the above formula (3.4) is equal to or greater than THR (j) +te, which is the sum of the corresponding switching time interval and the time required for entering the low power mode; when there is a low power consumption mode time with a time length less than THR (j) +te, determining a first low power consumption mode time THR (H) with a time length greater than or equal to THR (j) +te, then the above formula (3.4) may be rewritten as:

(3.4)

In one embodiment, the memory controller 103 may determine whether the total number of detected or stored time interval information 41 (1) -41 (n) reaches (e.g., is greater than or equal to) a predetermined number. If the total number of the time interval information 41 (1) -41 (n) reaches the preset number, the memory controller 103 may perform the above-mentioned operation of setting or adjusting the first target time threshold. Details of how to set or adjust the first target time threshold are described above, and detailed descriptions thereof are omitted herein. However, if the total number of the time interval information 41 (1) to 41 (n) does not reach the preset number, the memory controller 103 may not perform the above-described operation of setting or adjusting the first target time threshold.

In one embodiment, the memory controller 103 may determine whether the accumulated operating time of the memory device 10 reaches (e.g., is greater than or equal to) a predetermined time. The accumulated operating time of the storage device 10 may refer to the accumulated time length of the storage device 10 from the time point of the previous power-on or power-up to the current time point. If the accumulated operating time of the memory device 10 has reached the preset time, the memory controller 103 may perform the above-mentioned operation of setting or adjusting the first target time threshold. However, if the accumulated operating time of the memory device 10 does not reach the preset time, the memory controller 103 may not perform the above-mentioned operation of setting or adjusting the first target time threshold.

In one embodiment, by adjusting the first target time threshold at an appropriate time, the practicability of the low power mode can be effectively maintained in a variable command transmission environment between the host system 11 and the storage device 10, and the extra power consumption increase of the storage device 10 caused by the excessively frequent entering and exiting of the low power mode can be avoided.

In an embodiment, the memory controller 103 may obtain a second target time threshold that is greater than all time interval information. In an embodiment, when the memory device 10 is in the low power mode, the memory controller 103 may control the memory device 10 to exit the low power mode according to the second target time threshold.

In one embodiment, in the low power mode, the memory controller 103 may determine whether the accumulated time length after the memory device 10 enters the idle mode and the low power mode reaches (e.g., is greater than or equal to) a time threshold (i.e., a second target time threshold). If the accumulated time length reaches the second target time threshold, the memory controller 103 may control the memory device 10 to exit the low power consumption mode and return to the idle mode early. However, if this accumulated time length does not reach (e.g., is less than) the second target time threshold, the memory controller 103 may not control the memory device 10 to exit the low power consumption mode early.

In an embodiment, the memory controller 103 may determine whether count information (also referred to as third type count information) corresponding to a candidate time threshold (also referred to as third candidate time threshold) at an end of the plurality of candidate time thresholds meets a preset condition. If the third type of count information meets the preset condition, the memory controller 103 may update the second target time threshold according to the third candidate time threshold. However, if the third type of count information does not meet the preset condition, the memory controller 103 may not update the second target time threshold.

It is understood that the candidate time threshold for the end is a candidate time threshold greater than a preset length of time.

In an embodiment, the third type of count information may include count information C (m) and/or C (m-1). The memory controller 103 may determine whether the count information C (m) reaches (e.g., is greater than or equal to) a preset value. If the count information C (m) reaches the preset value, the memory controller 103 may determine that the count information C (m) meets the preset condition and update the second target time threshold according to the time threshold THR (m). For example, when the count information C (m) meets a preset condition, the memory controller 103 may update the second target time threshold value TO the time threshold value THR (m) minus the parameter TO. The parameter TO represents the time required for the memory device 10 TO exit the low power consumption mode. Thereafter, when the memory device 10 is in the low power mode, the memory controller 103 may control the memory device 10 to exit the low power mode according to the second target time threshold. However, if the count information C (m) does not reach the preset value, the memory controller 103 may determine that the count information C (m) does not meet the preset condition.

In one embodiment, if the count information C (m) does not reach the preset value, the memory controller 103 can further determine whether the sum of the count information C (m) and the count information C (m-1) reaches the preset value. If the sum of the count information C (m) and the count information C (m-1) reaches the preset value, the memory controller 103 may determine that the count information C (m) and the count information C (m-1) meet the preset condition and update the second target time threshold according to the time threshold THR (m-1). For example, when the count information C (m) and C (m-1) meet the preset condition, the memory controller 103 may update the second target time threshold TO the time threshold THR (m-1) minus the parameter TO.

In one embodiment, the memory device 10 may be caused to early perform a preparation job to exit the low power mode by reducing the second target time threshold at an appropriate time. Thereafter, when a new instruction is fetched, the memory device 10 may return to the normal operation mode more quickly because the memory device 10 has previously executed (or even completed) the preparation operation to exit the low power mode.

Fig. 7 is a flowchart of a system mode control method according to an embodiment of the present invention. Referring to fig. 7, in step S701, the state of the storage device in a time range is monitored to obtain a plurality of time interval information, wherein each time interval information is reflected in the time range, and the time length between a first time point when the storage device finishes processing a previous instruction and a second time point when the storage device acquires a next instruction. In step S702, a plurality of power consumption evaluation information corresponding to a plurality of candidate time thresholds is obtained from the plurality of time interval information. In step S703, a first target time threshold of the plurality of candidate time thresholds is determined according to the power consumption evaluation information. In step S704, when the storage device is in the idle mode, the storage device is controlled to enter a low power consumption mode according to the first target time threshold.

In one embodiment, the step of obtaining a plurality of power consumption evaluation information corresponding to a plurality of candidate time thresholds according to the plurality of time interval information comprises: taking each candidate time threshold value as a switching time threshold value respectively, and calculating first total power consumption corresponding to the plurality of time interval information; determining each of the first total power consumption as the power consumption evaluation information corresponding to the candidate time threshold.

In an embodiment, the step of calculating the first total power consumption corresponding to the plurality of time interval information includes: respectively taking each candidate time threshold as a switching time threshold, and dividing idle time duration, mode conversion time duration and low-power consumption time duration in the time interval information; correspondingly acquiring an idle mode power consumption value, a mode conversion power consumption value and a low power consumption mode power consumption value according to the idle time length, the mode conversion time length and the low power consumption time length; and determining the first total power consumption corresponding to each candidate time threshold according to the idle mode power consumption value, the mode conversion power consumption value and the low power consumption mode power consumption value.

In an embodiment, the step of obtaining a plurality of the power consumption evaluation information corresponding to a plurality of candidate time thresholds according to the plurality of time interval information comprises: obtaining count information corresponding to each candidate time threshold according to the plurality of time interval information, wherein each count information reflects the number of time interval information associated to the candidate time threshold in the plurality of time interval information; and obtaining a plurality of power consumption evaluation information corresponding to a plurality of candidate time thresholds according to the count information and the candidate time thresholds.

In one embodiment, the step of obtaining count information corresponding to each of the candidate time thresholds according to the plurality of time interval information includes: and respectively associating each time interval information in the plurality of time interval information to the closest candidate time threshold value and updating the corresponding count information.

In one embodiment, the step of obtaining a plurality of the power consumption evaluation information corresponding to a plurality of candidate time thresholds according to the count information and the candidate time thresholds includes: each candidate time threshold is respectively used as a switching time threshold, other candidate time thresholds smaller than the switching time threshold are determined to be idle mode time, and other candidate time thresholds larger than the switching time threshold are determined to be low power consumption mode time; acquiring first power consumption according to each idle mode time, the corresponding counting information, a switching time threshold, the corresponding counting information and the counting information corresponding to the low power consumption mode time; acquiring second power consumption according to the counting information respectively corresponding to the switching time threshold and the low power consumption mode time; acquiring third power consumption according to each low power consumption mode time, the corresponding counting information and the corresponding switching time threshold; and determining power consumption evaluation information corresponding to each candidate time threshold according to the first power consumption, the second power consumption and the third power consumption.

In an embodiment, the step of obtaining the first power consumption according to each idle mode time and the corresponding count information, the switching time threshold, the corresponding count information, and the count information corresponding to the low power consumption mode time includes: acquiring the total duration of the storage device in the idle mode based on each idle mode time, the switching time threshold, the low power consumption mode time and the corresponding counting information; acquiring first power consumption according to the idle power and the total duration of the storage device in the idle mode; according to the count information respectively corresponding to the switching time threshold and the low power consumption mode time, the step of obtaining the second power consumption comprises the following steps: acquiring second power consumption based on the mode switching power consumption, the switching time threshold and the counting information corresponding to the low power consumption mode time respectively; the step of obtaining third power consumption according to each low power consumption mode time, the corresponding count information and the corresponding switching time threshold value comprises the following steps: based on each low-power-consumption mode time, the corresponding counting information and the switching time threshold, acquiring the total duration of the storage device in the low-power-consumption mode; and acquiring third power consumption according to the low power consumption power and the total duration of the storage device in the low power consumption mode.

In one embodiment, the step of determining a first target time threshold of the plurality of candidate time thresholds according to the power consumption evaluation information comprises: comparing the plurality of power consumption evaluation information to obtain target power consumption evaluation information, wherein the target power consumption evaluation information is power consumption evaluation information with the lowest total power consumption of the storage device in the time range reflected in the plurality of power consumption evaluation information; and determining the candidate time threshold corresponding to the target power consumption evaluation information as the first target time threshold.

In an embodiment, the system mode control method further includes: acquiring a second target time threshold, wherein the second target time threshold is larger than all time interval information; and controlling the storage device to exit the low power consumption mode according to the second target time threshold when the storage device is in the low power consumption mode.

However, the steps in fig. 7 are described in detail above, and will not be described again here. It should be noted that each step in fig. 7 may be implemented as a plurality of program codes or circuits, and the present invention is not limited thereto. In addition, the method of fig. 7 may be used with the above exemplary embodiment, or may be used alone, and the present invention is not limited thereto.

In summary, the system mode control method and the storage device provided by the invention can adjust the first target time threshold at a proper time. Therefore, the practicability of the low power mode can be effectively maintained under the changeable command transmission environment between the host system 11 and the storage device 10, and the extra power consumption increase of the storage device 10 caused by the excessively frequent entering and exiting of the low power mode is avoided. In addition, the system mode control method and the storage device provided by the invention can also adjust the second target time threshold at proper time. Thus, the efficiency of the subsequent memory device 10 to revert to the normal operating mode can be improved.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.

Claims

1. A system mode control method for a storage device, the system mode control method comprising:

monitoring the state of the storage device in a time range to obtain a plurality of time interval information, wherein each time interval information in the plurality of time interval information is reflected in the time range, and the time length between a first time point when a previous instruction is processed and a second time point when a next instruction is acquired by the storage device;

Obtaining a plurality of power consumption evaluation information corresponding to a plurality of candidate time thresholds according to the plurality of time interval information;

determining a first target time threshold value in the candidate time threshold values according to the power consumption evaluation information; and

When the storage device is in an idle mode, controlling the storage device to enter a low power consumption mode according to the first target time threshold;

wherein determining the first target time threshold of the plurality of candidate time thresholds according to the plurality of power consumption evaluation information comprises:

Comparing the plurality of power consumption evaluation information to obtain target power consumption evaluation information, wherein the target power consumption evaluation information is power consumption evaluation information which reflects the lowest total power consumption of the storage device in the time range in the plurality of power consumption evaluation information;

and determining the candidate time threshold corresponding to the target power consumption evaluation information as the first target time threshold.

2. The system mode control method according to claim 1, wherein each of the power consumption evaluation information reflects the estimated total power consumption of the storage device in the time range if the corresponding candidate time threshold is taken as a switching time threshold, wherein the switching time threshold is a length of time for the storage device to enter a low power consumption mode from an idle mode.

3. The system mode control method according to claim 2, wherein the step of obtaining a plurality of pieces of power consumption evaluation information corresponding to a plurality of candidate time thresholds based on the plurality of pieces of time interval information includes:

Taking each candidate time threshold value as the switching time threshold value, and calculating first total power consumption corresponding to the time interval information; and

Determining each of the first total power consumption as the power consumption evaluation information corresponding to the candidate time threshold.

4. The system mode control method according to claim 3, wherein the step of calculating the first total power consumption corresponding to the plurality of time interval information using each of the candidate time thresholds as the switching time threshold, respectively, includes:

Respectively taking each candidate time threshold as the switching time threshold, and dividing idle time duration, mode conversion time duration and low-power consumption time duration in the time interval information;

Correspondingly acquiring an idle mode power consumption value, a mode conversion power consumption value and a low power consumption mode power consumption value according to the idle time length, the mode conversion time length and the low power consumption time length; and

And determining the first total power consumption corresponding to each candidate time threshold according to the idle mode power consumption value, the mode conversion power consumption value and the low power consumption mode power consumption value.

5. The system mode control method according to claim 2, wherein the step of obtaining the plurality of power consumption evaluation information corresponding to the plurality of candidate time thresholds based on the plurality of time interval information includes:

Obtaining count information corresponding to each candidate time threshold according to the plurality of time interval information, wherein each count information reflects the number of time interval information associated to the candidate time threshold in the plurality of time interval information; and

And obtaining a plurality of power consumption evaluation information corresponding to a plurality of candidate time thresholds according to the counting information and the candidate time thresholds.

6. The system mode control method according to claim 5, wherein the step of obtaining the count information corresponding to each of the candidate time thresholds based on the plurality of time interval information includes:

and respectively associating each time interval information in the plurality of time interval information to the closest candidate time threshold value and updating the corresponding count information.

7. The system mode control method according to claim 6, wherein the step of obtaining the plurality of pieces of power consumption evaluation information corresponding to a plurality of candidate time thresholds based on the count information and the candidate time thresholds includes:

each candidate time threshold is respectively used as the switching time threshold, other candidate time thresholds smaller than the switching time threshold are determined to be idle mode time, and other candidate time thresholds larger than the switching time threshold are determined to be low power consumption mode time;

Acquiring first power consumption according to each idle mode time, the corresponding counting information, a switching time threshold, the corresponding counting information and the counting information corresponding to the low power consumption mode time; acquiring second power consumption according to the counting information respectively corresponding to the switching time threshold and the low power consumption mode time; acquiring third power consumption according to each low power consumption mode time, the corresponding counting information and the corresponding switching time threshold; and

And determining the power consumption evaluation information corresponding to each candidate time threshold according to the first power consumption, the second power consumption and the third power consumption.

8. The system mode control method according to claim 7, wherein,

The step of obtaining the first power consumption according to each idle mode time, the corresponding count information, a switching time threshold, the corresponding count information and the count information corresponding to the low power consumption mode time includes:

Acquiring the total duration of the storage device in the idle mode based on each idle mode time, the switching time threshold, the low power consumption mode time and the corresponding counting information;

Acquiring the first power consumption according to the idle power and the total duration of the storage device in the idle mode;

According to the count information respectively corresponding to the switching time threshold and the low power consumption mode time, the step of obtaining the second power consumption includes:

Acquiring the second power consumption based on the mode switching power consumption, the switching time threshold and the counting information corresponding to the low power consumption mode time respectively;

the step of obtaining the third power consumption according to each low power consumption mode time, the corresponding count information and the corresponding switching time threshold value includes:

Based on each low power consumption mode time, the corresponding counting information and the switching time threshold value, acquiring the total duration of the storage device in the low power consumption mode; and

And acquiring the third power consumption according to the low power consumption power and the total duration of the storage device in the low power consumption mode.

9. The system mode control method according to claim 1, characterized by further comprising:

acquiring a second target time threshold, wherein the second target time threshold is larger than all time interval information; and

And when the storage device is in the low power consumption mode, controlling the storage device to exit the low power consumption mode according to the second target time threshold.

10. A memory device, comprising:

A connection interface unit for connecting to a host system;

A memory module; and

A memory controller connected to the connection interface unit and the memory module,

Wherein the memory controller is to:

11. The storage device of claim 10, wherein each of the power consumption evaluation information reflects an estimated total power consumption of the storage device in the time range if the candidate time threshold is taken as a switching time threshold, wherein the switching time threshold is a length of time for the storage device to enter a low power consumption mode from an idle mode.

12. The storage device of claim 11, wherein the operation of obtaining a plurality of power consumption assessment information corresponding to a plurality of candidate time thresholds based on the plurality of time interval information comprises:

13. The storage device of claim 12, wherein calculating the first total power consumption corresponding to the plurality of time interval information using each of the candidate time thresholds as the switching time threshold, respectively, comprises:

14. The storage device of claim 11, wherein obtaining the plurality of power consumption assessment information corresponding to the plurality of candidate time thresholds from the plurality of time interval information comprises:

15. The storage device of claim 14, wherein the operation of obtaining count information corresponding to each of the candidate time thresholds based on the plurality of time interval information comprises:

16. The storage device of claim 15, wherein obtaining the plurality of power consumption assessment information corresponding to a plurality of candidate time thresholds based on the count information and the candidate time thresholds comprises:

17. The memory device of claim 16, wherein the operation of obtaining the first power consumption based on each of the idle mode times and the corresponding count information comprises:

18. The storage device of claim 10, further comprising: