CN118349098A - A dynamic voltage frequency adjustment device, related method and storage medium - Google Patents

Abstract

The present application discloses a dynamic voltage frequency adjustment device, related methods and storage medium, the device may include: a scene classifier, used to obtain the characteristic information of the instruction stream currently executed by the processing system, and determine the corresponding target scene from N preset scenes based on the characteristic information; a predictor, used to determine the operating parameters of the processing system based on the characteristic information and the target scene, the operating parameters include the operating frequency and the operating voltage; a driver, used to adjust the current frequency and voltage of the processing system to the operating frequency and the operating voltage respectively. The present application can accurately implement DVFS control, stabilize the processor and memory in real time at the balance point of performance and energy consumption, and achieve better energy efficiency control.

Description

A dynamic voltage frequency adjustment device, related method and storage medium

Technical Field

The present application relates to the field of computer technology, and in particular to a dynamic voltage frequency adjustment device, related methods and storage media.

Background technique

With the continuous development of computer technology, the operating frequency and integration of integrated circuits are also constantly improving, and the power consumption of integrated circuits is also increasing rapidly, making it difficult to improve the performance and integration of various hardware systems (such as processors) in computers, and increasing the cost of heat dissipation. In order to save power consumption and control heat, dynamic voltage frequency scaling (Dynamic Voltage Frequency Scaling, DVFS) technology is usually used to adjust the voltage and frequency of various hardware systems of the computer, so that these hardware systems will not always run at the highest frequency, but can be instructed to run at different frequencies according to certain rules based on system load and configuration.

However, in the actual operating environment, the relationship between performance and frequency is very complex, with large nonlinearity and time-varying properties. It is a difficult problem to maintain the accuracy and real-time performance required for DVFS prediction.

Currently, devices and methods related to DVFS technology are still being explored.

Summary of the invention

The embodiments of the present application provide a dynamic voltage frequency adjustment device, related methods and storage medium, which can accurately implement DVFS control, stabilize the processor and memory in real time at the balance point between performance and energy consumption, and achieve better energy efficiency control.

In a first aspect, an embodiment of the present application provides a dynamic voltage and frequency adjustment device, which may include: a scene classifier, used to obtain characteristic information of an instruction stream currently executed by a processing system, and determine a corresponding target scene from N preset scenes based on the characteristic information; wherein the processing system includes one or more of a processor and a memory, and the characteristic information includes one or more of an event type, a number of events, a cache bandwidth, a number of cache misses, and a number of cache access blockages; N is an integer greater than or equal to 2; a predictor, used to determine operating parameters of the processing system based on the characteristic information and the target scene, wherein the operating parameters include an operating frequency and an operating voltage; and a driver, used to adjust the current frequency and voltage of the processing system to the operating frequency and the operating voltage, respectively.

In the embodiment of the present application, the dynamic voltage and frequency adjustment device can obtain the characteristic information (such as event type, event number, cache bandwidth and cache miss number, etc.) of the instruction stream currently executed by the processing system (including the processor and/or memory) through the scene classifier, and determine the target scene from multiple preset scenes based on the characteristic information; then, the dynamic voltage and frequency adjustment device can perform performance prediction based on the characteristic information and the target scene through the predictor to obtain the working parameters of the processing system; finally, the dynamic voltage and frequency adjustment device can adjust the current frequency and voltage of the processing system to the working frequency and working voltage in the working parameters through the driver. Different from some technologies, for example, the DVFS solution based on the result of averaging coarse-grained information over a long period of time, the embodiment of the present application performs scene classification and performance prediction based on real-time, fine-grained information (i.e., characteristic information of the instruction stream currently executed, including one or more of event type, event number, cache bandwidth and cache miss number), which can accurately implement DVFS and stabilize the processor and memory in real time at the balance point of performance and energy consumption, so as to obtain better energy efficiency control.

In one possible implementation, the predictor runs N performance prediction algorithms, and the N performance prediction algorithms correspond one-to-one to the N preset scenarios; the predictor is specifically used to: determine a target performance prediction algorithm corresponding to the target scenario from the N performance prediction algorithms; and determine the operating parameters of the processing system based on the feature information and the target performance prediction algorithm.

In the embodiment of the present application, the predictor can first determine the performance prediction algorithm corresponding to the target scenario from multiple performance prediction algorithms, and then process the feature information through the performance prediction algorithm to obtain the working parameters of the processing system. Since multiple performance prediction algorithms correspond to multiple preset scenarios one by one, the accuracy of the working parameters can be ensured by processing the feature information based on the performance prediction algorithm corresponding to the target scenario.

In a possible implementation, the predictor includes a selector and N sub-predictors, the N sub-predictors correspond one-to-one to N performance prediction algorithms, and the N performance prediction algorithms correspond one-to-one to the N preset scenarios; the predictor is specifically used to: perform performance prediction on the feature information respectively through the N performance prediction algorithms corresponding to the N sub-predictors to obtain N prediction results; determine a target prediction result corresponding to the target scenario from the N prediction results through the selector; the target prediction result includes the working parameters of the processing system.

In an embodiment of the present application, the predictor may include a selector and a plurality of sub-predictors, each of which corresponds to a performance prediction algorithm. The predictor may perform performance prediction on the feature information through the plurality of sub-predictors to obtain a plurality of prediction results; and then the selector determines the prediction result corresponding to the target scene from the plurality of prediction results, and the prediction result includes the working parameters of the processing system. Since the plurality of performance prediction algorithms correspond one-to-one to the plurality of preset scenes, after the feature information is predicted using the performance prediction algorithms of the plurality of sub-predictors, the corresponding prediction results (including the working parameters) are determined based on the target scene, and the accuracy of the working parameters can be ensured.

In one possible implementation, the device also includes a feedback unit, and the feedback unit is used to determine whether to adjust the classification algorithm used to determine the target scene in the scene classifier based on the working performance of the processing system when it is at the working frequency and the working voltage; wherein, when the working performance of the processing system does not meet a preset condition, the classification algorithm is adjusted; and when the working performance of the processing system meets the preset condition, the classification algorithm is not adjusted.

In an embodiment of the present application, the dynamic voltage and frequency adjustment device also includes a feedback unit, and the performance after DVFS can be monitored through the feedback unit. If the performance after DVFS does not meet the preset conditions, the classification algorithm in the scene classifier can be adjusted, thereby further improving the classification accuracy of the scene classifier.

In a possible implementation, the predictor is further used to: perform training based on first sample data to obtain the N performance prediction algorithms; the first sample data includes feature information of sample instruction streams corresponding to the N performance prediction algorithms respectively.

In the embodiment of the present application, the multiple performance prediction algorithms run by the predictor can be obtained by training based on sample data, which can provide a guarantee for the accuracy of the performance prediction algorithm and further ensure the accuracy of DVFS.

In a possible implementation, the scene classifier is further used to: perform training based on second sample data to obtain the N preset scenes; the second sample data includes feature information of sample instruction streams corresponding to the N preset scenes respectively.

In the embodiment of the present application, the multiple preset scenes in the scene classifier can be obtained based on sample data training, which can provide a guarantee for the classification accuracy of the scene classifier and further ensure the accuracy of DVFS.

In a possible implementation, the predictor is specifically used to: obtain performance requirement information, the performance requirement information including a preset range of the operating parameter; and determine the operating parameter of the processing system based on the performance requirement information, the feature information and the target scenario.

In the embodiment of the present application, the predictor can combine the performance requirement information of the application unit to make predictions in the process of determining the operating parameters of the processing system, so as to predict the prediction results that are more in line with the scenario requirements and further ensure the accuracy of the prediction.

In a second aspect, an embodiment of the present application provides a dynamic voltage and frequency adjustment method, which may include: obtaining characteristic information of an instruction stream currently executed by a processing system, and determining a corresponding target scenario from N preset scenarios based on the characteristic information; wherein the processing system includes one or more of a processor and a memory, and the characteristic information includes one or more of an event type, a number of events, a cache bandwidth, a number of cache misses, and a number of cache access blockages; N is an integer greater than or equal to 2; determining operating parameters of the processing system based on the characteristic information and the target scenario, the operating parameters including an operating frequency and an operating voltage; and adjusting the current frequency and voltage of the processing system to the operating frequency and the operating voltage, respectively.

In the embodiment of the present application, the characteristic information (such as event type, number of events, cache bandwidth and number of cache misses, etc.) of the instruction stream currently executed by the processing system (including the processor and/or memory) can be first obtained, and the target scene can be determined from multiple preset scenes based on the characteristic information; then, performance prediction can be performed based on the characteristic information and the target scene to obtain the working parameters of the processing system; finally, the current frequency and voltage of the processing system can be adjusted to the working frequency and working voltage in the working parameters respectively. Different from some technologies that perform DVFS based on the results of long-term averaging of coarse-grained information, or perform DVFS based only on the load condition of the SOC, the embodiment of the present application performs scene classification and performance prediction based on real-time, fine-grained information, and can accurately implement DVFS, stabilize the processor and memory in real time at the balance point between performance and energy consumption, so as to obtain better energy efficiency control.

In one possible implementation, determining the operating parameters of the processing system based on the feature information and the target scenario includes: determining a target performance prediction algorithm corresponding to the target scenario from N performance prediction algorithms; the N performance prediction algorithms correspond one-to-one to the N preset scenarios; and determining the operating parameters of the processing system based on the feature information and the target performance prediction algorithm.

In one possible implementation, determining the operating parameters of the processing system based on the feature information and the target scenario includes: performing performance prediction on the feature information through N performance prediction algorithms to obtain N prediction results; the N performance prediction algorithms correspond one-to-one to the N preset scenarios; determining a target prediction result corresponding to the target scenario from the N prediction results; and the target prediction result includes the operating parameters of the processing system.

In one possible implementation, the method further includes: determining whether to adjust a classification algorithm used to determine the target scene in the scene classifier based on the working performance of the processing system when the processing system is at the working frequency and the working voltage; wherein, when the working performance of the processing system does not meet a preset condition, the classification algorithm is adjusted; and when the working performance of the processing system meets the preset condition, the classification algorithm is not adjusted.

In a possible implementation, the method further includes: performing training based on first sample data to obtain the N performance prediction algorithms; the first sample data includes feature information of sample instruction streams corresponding to the N performance prediction algorithms respectively.

In a possible implementation, the method further includes: performing training based on second sample data to obtain the N preset scenarios; the second sample data includes feature information of sample instruction streams corresponding to the N preset scenarios respectively.

In one possible implementation, determining the operating parameters of the processing system based on the characteristic information and the target scenario includes: obtaining performance requirement information, the performance requirement information including a preset range of the operating parameters; and determining the operating parameters of the processing system based on the performance requirement information, the characteristic information and the target scenario.

In a third aspect, an embodiment of the present application provides a computer-readable storage medium for storing computer software instructions used by a device apparatus for implementing a dynamic voltage and frequency adjustment method provided by one or more of the first aspects above, which includes a program designed for executing the above aspects.

In a fourth aspect, an embodiment of the present application provides a computer program, which includes instructions. When the computer program is executed by a computer, the computer can execute a process executed by an apparatus for implementing a dynamic voltage and frequency adjustment method provided by one or more of the first aspects above.

In a fifth aspect, an embodiment of the present application provides a terminal device, the terminal device includes a processor, and the processor is configured to support the terminal device to implement the corresponding functions in the dynamic voltage and frequency adjustment method provided in the second aspect. The terminal device may also include a memory, the memory is used to couple with the processor, and the memory stores the necessary program instructions and data of the terminal device. The terminal device may also include a communication interface for the terminal device to communicate with other devices or a communication network.

In a sixth aspect, an embodiment of the present application provides a chip system, which includes a processor for supporting a device to implement the functions involved in the first aspect, for example, generating or processing the information involved in the dynamic voltage and frequency adjustment method. In a possible design, the chip system also includes a memory, which is used to store program instructions and data necessary for the device. The chip system can be composed of chips, or it can include chips and other discrete devices.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the technical solutions in the embodiments of the present application or the background technology, the drawings required for use in the embodiments of the present application or the background technology will be described below.

FIG. 1a is a schematic diagram of the structure of a terminal device provided in an embodiment of the present application.

FIG1b is a schematic diagram of the structure of another terminal device provided in an embodiment of the present application.

FIG. 2 is a schematic diagram of the structure of a dynamic voltage frequency adjustment device provided in an embodiment of the present application.

FIG3 is a schematic diagram of the structure of another dynamic voltage frequency adjustment device provided in an embodiment of the present application.

FIG. 4 is a schematic diagram of the structure of another dynamic voltage frequency adjustment device provided in an embodiment of the present application.

FIG5 is a schematic diagram of an algorithm training process provided in an embodiment of the present application.

FIG6 is a schematic diagram of the structure of another dynamic voltage frequency adjustment device provided in an embodiment of the present application.

FIG. 7 is a schematic diagram of the structure of another dynamic voltage frequency adjustment device provided in an embodiment of the present application.

FIG8 is a flow chart of a dynamic voltage frequency adjustment method provided in an embodiment of the present application.

Detailed ways

The embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application.

The terms "first", "second", "third" and "fourth" etc. in the specification and claims of the present application and the drawings are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally includes steps or units that are not listed, or optionally includes other steps or units inherent to these processes, methods, products or devices.

Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in one or more embodiments of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

The terms "component", "module", "system", etc. used in this specification are used to represent computer-related entities, hardware, firmware, a combination of hardware and software, software, or software in execution. For example, a component can be, but is not limited to, a process running on a processor, a processor, an object, an executable file, an execution thread, a program and/or a computer. By way of illustration, both applications and computing devices running on a computing device can be components. One or more components may reside in a process and/or an execution thread, and a component may be located on a computer and/or distributed between two or more computers. In addition, these components may be executed from various computer-readable media having various data structures stored thereon. Components may, for example, communicate through local and/or remote processes according to signals having one or more data packets (e.g., data from two components interacting with another component between a local system, a distributed system and/or a network, such as the Internet interacting with other systems through signals).

First, some terms in this application are explained to facilitate understanding by those skilled in the art.

(1) Dynamic Voltage Frequency Scaling (DVFS), which can generally dynamically adjust the operating frequency and voltage of the chip according to the different computing power requirements of the application program running on the chip (for the same chip, the higher the frequency, the higher the required voltage), so as to achieve the purpose of energy saving. In the embodiment of the present application, during the operation of the computer, by collecting characteristic information of the instruction stream of the processor and/or the storage subsystem, the working scene and working performance (performance corresponding to the working frequency and working voltage) can be predicted, and then the working voltage and working frequency of the processor (Central Processing Unit, CPU) and the storage subsystem and other related hardware can be adjusted, and DVFS control can be accurately implemented to stabilize the processor and the storage subsystem in real time at the balance point of performance and energy consumption, thereby improving the energy efficiency ratio.

(2) DVFS process. When the processor or storage subsystem encounters certain performance bottlenecks, DVFS can reduce the frequency and voltage of non-performance-critical components to reduce the energy consumption of these components. After the performance bottleneck is changed, the voltage and frequency of performance-critical components are increased to maintain performance. When adjusting frequency and voltage, the following principles can generally be used as a reference: when adjusting the frequency from high to low, the frequency can be reduced first, and then the voltage; conversely, when adjusting the frequency from low to high, the voltage can be increased first, and then the frequency.

(3) In this application, "plurality" means two or more. "and/or" describes the association relationship of related objects, indicating that three relationships can exist. For example, A and/or B can mean: A exists alone, A and B exist at the same time, and B exists alone. The character "/" generally indicates that the related objects are in an "or" relationship.

First, the technical problems to be solved by this application are analyzed and proposed. Common DVFS solutions include the following solutions 1 and 2:

Solution 1: Collect information such as preset classification, IO characteristics, processor utilization, scheduling delay, and processor cluster allocation of the program; control this information through independent proportional-integral-derivative controllers (PID Control); synthesize the outputs of each independent proportional-integral-derivative controller loop according to a certain weight to calculate the minimum performance requirement; then look up the pre-configured table according to the minimum performance requirement to determine the frequency, voltage, and core type information; finally output the frequency, voltage, and core scheduling information to perform DVFS control operations.

This solution has the following disadvantages:

Poor real-time performance. The PID controller needs to perform DVFS control based on the long-term average results of the above information. It has poor real-time performance and cannot adapt to the needs of complex environments for high-speed response DVFS control capabilities, affecting the energy efficiency benefits brought by DVFS control.

The algorithm structure is complex. The above information needs to be processed by the corresponding PID controller separately, and the processing results need to be synthesized according to the weights. The algorithm structure is complex, the processing process is slow, and the possibility of hardware implementation is low, which limits the possibility of hardware implementation of the solution and further limits the real-time performance.

The accuracy of DVFS control is low. The granularity of the above information is coarse, that is, the PID controller processes based on coarse-grained information, resulting in low accuracy of DVFS control, which affects the energy efficiency of DVFS. For example, in some application scenarios, after reducing a certain frequency, the performance loss of the program is very small, but the energy efficiency can be greatly improved. However, the solution of DVFS processing based on coarse-grained information in Solution 1 cannot detect and identify such scenarios.

Solution 2: Collect the SOC load through the system-on-chip (SOC) information collection unit; then determine the processor performance requirements through SOC load calculation; then use the DVFS table selection unit to convert the processor performance requirements into the frequency and voltage information controlled by the DVFS; finally, the DVFS operation control unit controls the SOC supply voltage based on the frequency and voltage information.

This solution has the following disadvantages:

The accuracy and real-time performance of DVFS control are poor. Using only the system load (SOC-load) as the basis for DVFS adjustment cannot accurately reflect the performance requirements of the processor, nor can it guarantee the accuracy of DVFS, and thus it is difficult to obtain a better energy efficiency ratio. In addition, the load changes are generally slow, and the response of DVFS based only on the load will also be slow, which cannot meet the needs of those scenarios with high real-time requirements.

In order to solve the problem of low real-time performance and accuracy when performing DVFS, considering the shortcomings of the above solutions, the technical problems actually to be solved by this application include the following:

Scenario classification and performance prediction based on real-time, fine-grained information. In the embodiment of the present application, scenario classification and performance prediction can be performed based on the characteristic information (such as event type, number of events, cache bandwidth, and number of cache misses, etc.) of the instruction stream currently executed by the processing system (including the processor and/or memory), and DVFS can be accurately implemented to stabilize the processor and memory in real time at the balance point between performance and energy consumption, thereby obtaining better energy efficiency control.

In order to better understand the dynamic voltage frequency adjustment device provided in the embodiment of the present application, the system architecture and/or application scenario of the dynamic voltage frequency adjustment device provided in the embodiment of the present application will be described below. It is understandable that the system architecture and application scenario described in the embodiment of the present application are to more clearly illustrate the technical solution of the embodiment of the present application, and do not constitute a limitation on the technical solution provided in the embodiment of the present application.

See FIG. 1a, which is a schematic diagram of the structure of a terminal device provided in an embodiment of the present application. The terminal device 01 provided in the present application may include one or more processors 11, one or more memories 12, one or more power management units (Power Management Unit, PMU) 13 and other hardware 14. The terminal device 01 may be a subscriber unit (Subscriber Unit), a cellular phone (Cellular Phone), a smart phone (Smart Phone), a personal computer (Personal Compute, PC), a personal digital assistant (Personal Digital Assistant, PDA) computer, a tablet computer, a handheld device (Handset), a laptop computer (Laptop Computer), a machine type communication (Machine Type Communication, MTC) terminal, a smart wearable device, etc.

Among them, the processor 11 can be a central processing unit (CPU), a graphics processing unit (GPU), or a chip with other functions (such as SOC, programmable system-on-chip (PSOC)). The CPU can be used to process instructions, execute operations, control time and process data, etc., that is, the CPU mainly interprets computer instructions and processes data in computer software. The operations in the computer can be performed by the CPU to read instructions, decode instructions and execute instructions; GPU is a microprocessor that performs image operations on the computer, mainly performing complex mathematical and geometric calculations to complete graphics rendering. In an embodiment of the present application, the processor 11 may include a dynamic voltage and frequency adjustment device, so that the dynamic voltage and frequency adjustment device can be used to perform scene classification and performance prediction based on the characteristic information of the instruction stream currently executed by the processing system (including the processor and/or memory) (such as event type, event number, cache bandwidth and cache miss times, etc.), and accurately implement DVFS, and stabilize the processor and memory in real time at the balance point of performance and energy consumption, so as to obtain better energy efficiency control.

The memory 12 is used to store the preparation data required by the processor 11 to execute the task, the intermediate data generated during the execution of the task, and the result data after the task is completed. The memory 12 may include one or more local memories, one or more registers, one or more level 1 caches, one or more level 2 caches, and various buffers, etc. It may also include other external memories (not shown in the figure).

The power management unit 13 is connected to the processor 11, the memory 12 and other hardware 14 respectively. The power management unit 13 can be used to supply power to the processor 11, the memory 12 and other hardware 14. The power management unit 13 can also receive control information sent by the dynamic voltage and frequency adjustment device in the processor 11, and adjust the voltage provided to the processor 11 and the memory 12 based on the control information. The control information is determined by the dynamic voltage and frequency adjustment device based on the characteristic information (such as event type, event number, cache bandwidth and cache miss times, etc.) of the instruction stream currently executed by the processing system (including the processor and/or memory) to perform scene classification and performance prediction.

Other hardware 14 may include a clock generator, a display screen, a camera, various IO interfaces, and various sensors. The clock generator may be used to adjust the frequency of the processor 11 and the memory 12 according to the control information sent by the dynamic voltage and frequency adjustment device. The control information is determined by the dynamic voltage and frequency adjustment device based on the characteristic information (such as event type, event number, cache bandwidth, cache miss times, etc.) of the instruction stream currently executed by the processing system (including the processor and/or memory) to perform scene classification and performance prediction.

In a possible implementation, the processor in the terminal device provided by the present application may not include a dynamic voltage and frequency adjustment device, that is, the dynamic voltage and frequency adjustment device may be implemented by a separate chip instead of being integrated on the processor chip. See Figure 1b, which is a schematic diagram of the structure of another terminal device provided by an embodiment of the present application. The terminal device 02 provided by the present application may include one or more processors 21, one or more memories 22, one or more power management units 23, other hardware 24, and one or more dynamic voltage and frequency adjustment devices 25. Among them, the functions and connection relationships of each unit in the terminal device 02 can refer to the relevant description of the above-mentioned terminal device 01, which will not be repeated here.

It should be noted that the embodiments of the present application can be applied to the system architecture of various computer devices. The architecture of the computer device in the above figure is only an exemplary implementation in the embodiments of the present application. The architecture applicable to the embodiments of the present application includes but is not limited to the above architecture. It should be understood that the architecture of the computer device may have more or fewer units/modules than those shown in the figure, may combine two or more units/modules, or may have different unit/module configurations. The various units/modules shown in the figure can be implemented in hardware, software, or a combination of hardware and software including one or more signal processing and/or application-specific integrated circuits.

The following describes the embodiments of the present application in conjunction with the drawings in the embodiments of the present application. First, the structure of the dynamic voltage and frequency adjustment device of the present application is shown in Figure 2. Figure 2 is a schematic diagram of the structure of a dynamic voltage and frequency adjustment device provided in the embodiments of the present application. The dynamic voltage and frequency adjustment device may include a scene classifier 110, a predictor 111, and a driver 112. The dynamic voltage and frequency adjustment device can perform scene classification and performance prediction based on the characteristic information (such as event type, number of events, cache bandwidth, and number of cache misses) of the instruction stream currently executed by the processing system (including the processor and/or memory), and can accurately implement DVFS, stabilize the processor and memory in real time at the balance point between performance and energy consumption, so as to obtain better energy efficiency control. Among them,

The scene classifier 110 is used to obtain feature information of the instruction stream currently executed by the processing system, and determine a corresponding target scene from N preset scenes based on the feature information.

Specifically, the processing system includes one or more of a processor and a memory, and the characteristic information includes one or more of an event type, an event number, a cache bandwidth, a cache miss number, and a cache access blocking number; N is an integer greater than or equal to 2. After acquiring the characteristic information of the instruction stream currently executed by the processing system, the scene classifier 110 can determine the scene (i.e., the target scene) corresponding to the characteristic information from multiple preset scenes (i.e., N preset scenes), wherein the N preset scenes can include a computationally intensive scene, a memory access intensive scene, and a complex control flow scene, etc., wherein the computationally intensive scene can be a scene that requires a large amount of computing resources of the processor for calculation, for example, a scene with a high proportion of floating-point (or fixed-point) operations; the memory access intensive scene can be a scene that requires a large amount of access to memory (e.g., memory, cache, external memory) resources; the complex control flow scene can be a scene that requires the processor to perform complex control. Optionally, the preset scene can also be a game scene, a video scene, a reading scene, or an instant messaging scene, etc., which is not specifically limited here. Furthermore, the characteristic information may specifically include one or more of the number of floating-point instructions, the number of fixed-point instructions, the miss rate of the instruction cache, the error rate of the branch predictor, the number of L2 cache misses, the L2 cache bandwidth, the L2 cache access congestion, the number of L3 cache misses, the L3 cache bandwidth, the L3 cache access congestion, and the memory access congestion, without specific limitation herein.

Understandably, the input of the scene classifier 110 is partly processor events and partly memory events, such as events generated by instruction cache, data cache, L2 cache, L3 cache, and memory controller, etc. Further, the scene classifier 110 can determine the target scene based on the processor events and memory events.

It should be noted that the scene classifier in the dynamic voltage and frequency adjustment device can be implemented by software or hardware, and is not specifically limited in this application.

Optionally, the scene classifier 110 in the dynamic voltage and frequency adjustment device can be a linear classifier, which is used to perform scene classification. The input of the linear classifier can be various events of the processor and the memory, and the output of the linear classifier can be the target scene category in the preset scene. The number of categories of the preset scene can be determined by the accuracy requirement of the classification, the computing power of the system, etc.

Optionally, the scene classifier 110 in the dynamic voltage and frequency adjustment device can also be implemented using a perceptron model, using online feedback to correct the perceptron; the scene classifier 110 in the dynamic voltage and frequency adjustment device can also be implemented using an artificial neural network; the scene classifier 110 in the dynamic voltage and frequency adjustment device can also be implemented using an offline trained model.

The predictor 111 is used to determine the operating parameters of the processing system based on the feature information and the target scene.

Specifically, after acquiring the characteristic information of the instruction stream currently executed by the processing system and the target scene determined by the scene classifier 110, the predictor 111 can determine the operating parameters required by the processing system based on the characteristic information and the target scene, wherein the operating parameters may include the operating frequency and the operating voltage. Optionally, the operating parameters can be determined by the predictor 111 based on the performance prediction results of the processing system when it operates at the operating frequency and the operating voltage. The performance prediction results can be understood as the performance when the frequency and voltage of the current processing system are adjusted to the operating frequency and the operating voltage. The performance prediction results can be a correlation coefficient or an enumeration, such as a strong performance improvement, a slight performance improvement, a substantially unchanged performance, a slight performance decrease, a strong performance decrease, etc.

The driver 112 adjusts the current frequency and voltage of the processing system to the operating frequency and the operating voltage respectively.

Specifically, the driver 112 can adjust the current frequency and voltage of the processing system to the operating frequency and operating voltage in the operating parameters based on the acquired operating parameters, thereby completing the DVFS control. Specifically, the driver 112 can control the clock pulse generator to adjust the current frequency of the processing system to the operating frequency, and control the power management unit to adjust the current voltage of the processing system to the operating voltage through control information, wherein the control information may include the above-mentioned operating parameters, and the control information can be determined by the driver querying a pre-configured frequency point voltage mapping table based on the operating parameters. It should be noted that the power management unit and the clock pulse generator can work together and switch synchronously according to the switching sequence. Modifications to the current frequency and voltage of the processing system will independently affect the processor and memory, so that the processor and memory can operate at a suitable frequency and voltage.

In one possible implementation, the predictor 111 runs N performance prediction algorithms, and the predictor 111 can first determine a target performance prediction algorithm corresponding to the target scenario from the N performance prediction algorithms; and then determine the operating parameters of the processing system based on the feature information and the target performance prediction algorithm. The N performance prediction algorithms correspond one-to-one to N preset scenarios. Specifically, since the predictor 111 runs performance prediction algorithms corresponding to multiple preset scenarios, the performance prediction algorithm corresponding to the target scenario can be selected from multiple performance prediction algorithms based on the target scenario output by the scene classifier 110, and then the performance of adjusting the frequency and voltage of the current processing system to the operating frequency and operating voltage can be predicted based on the performance prediction algorithm and the feature information.

In a possible implementation, the predictor 111 includes a selector and N sub-predictors, see FIG3, FIG3 is a schematic diagram of the structure of another dynamic voltage and frequency adjustment device provided in an embodiment of the present application, wherein the predictor 111 includes a plurality of sub-predictors (i.e., N sub-predictors) and a selector, and each of the plurality of sub-predictors corresponds to a performance prediction algorithm, and each performance prediction algorithm corresponds to a preset scenario one-to-one. Specifically, the predictor 111 can first perform performance prediction on the feature information respectively through the performance prediction algorithm corresponding to each of the sub-predictors to obtain N prediction results, and then determine the target prediction result corresponding to the target scenario from the N prediction results through the selector, and the target prediction result includes the operating parameters of the processing system (including operating frequency and operating voltage). It is understandable that the selector can also be a module or unit independent of the predictor, which is not specifically limited here.

In one possible implementation, the dynamic voltage and frequency adjustment device provided in the embodiment of the present application may further include a feedback unit, see Figure 4, which is a structural schematic diagram of another dynamic voltage and frequency adjustment device provided in the embodiment of the present application, wherein the feedback unit can be used to: determine whether to adjust the classification algorithm used to determine the target scene in the scene classifier 110 based on the working performance of the processing system when it is at the working frequency and the working voltage; when the working performance of the processing system does not meet the preset conditions, adjust the classification algorithm; when the working performance of the processing system meets the preset conditions, do not adjust the classification algorithm. Specifically, the feedback unit can determine whether to adjust the classification algorithm based on whether the actual change direction and amplitude of the processing system performance after adjusting the frequency and voltage are consistent with the predicted direction and amplitude (i.e., the preset condition). For example, when the performance prediction result of the predictor 111 is that the performance is strongly (i.e., amplitude) improved (i.e., direction) after adjusting the frequency and voltage, and when the dynamic voltage and frequency adjustment device adjusts the frequency and voltage of the current processing system to the operating frequency and operating voltage, the performance of the processing system is slightly improved, the performance is basically unchanged, the performance is slightly reduced, or the performance is strongly reduced, etc., then it can be considered that the working performance does not meet the preset conditions, and then the classification algorithm of the scene classifier is adjusted. It can be understood that the preset condition can also be a preset performance threshold. For example, if the performance after adjusting the frequency and voltage reaches 80%, and the preset performance threshold is 90%, then it can be considered that the working performance does not meet the preset conditions, and then the classification algorithm of the scene classifier is adjusted.

Optionally, the feedback unit may also determine whether to adjust the performance prediction algorithm in the predictor 111 based on the working performance of the processing system when it is at the working frequency and the working voltage. The specific judgment process can refer to the above description on whether to adjust the classification algorithm, which will not be repeated here. It should be noted that the feedback unit also determines whether to adjust the performance prediction algorithm in the predictor 111 and the classification algorithm of the scene classifier 110 based on the working performance of the processing system when it is at the working frequency and the working voltage. In other words, the performance prediction algorithm and the classification algorithm can be adjusted together, or they can be adjusted separately, or only one of them can be adjusted, which is not specifically limited here.

Optionally, the feedback unit may include a performance monitor and a performance prediction algorithm weight calculator. Specifically, the feedback unit may obtain feature information of the currently executed instruction stream through the performance monitor, and adjust the classification algorithm of the scene classifier based on the prediction result of the predictor through the performance prediction algorithm weight calculator.

In a possible implementation, the performance prediction algorithm in the predictor 111 may be trained based on sample data (i.e., first sample data), and the sample data includes feature information of sample instruction streams corresponding to N performance prediction algorithms. Specifically, the sample data may be understood as feature information of instruction streams corresponding to a plurality of preset scenarios, and then the sample data may be trained according to the training algorithm, thereby obtaining a plurality of preset scenarios (i.e., N preset scenarios).

In a possible implementation, the classification algorithm in the scene classifier 110 can be obtained by training based on sample data (i.e., second sample data), and the sample data includes feature information of a sample instruction stream corresponding to the classification algorithm. Specifically, the sample data can be understood as feature information of an instruction stream corresponding to the classification algorithm, and then the sample data can be trained according to the training algorithm, so that the classification algorithm of the scene classifier 110 can be obtained.

It should be noted that the performance prediction algorithm in the predictor 111 and the classification algorithm in the scene classifier 110 can be jointly trained and optimized to achieve collaborative optimization so that the accuracy is optimized. Please refer to Figure 5, which is a schematic diagram of an algorithm training process provided in an embodiment of the present application, including the following steps:

Step S501: Initialize the classification algorithm of the scene classifier.

Specifically, other algorithms (eg, K-means algorithm) may be used to initialize the classification algorithm of the scene classifier through feature clustering.

Step S502: using the classification algorithm of the scene classifier to classify the sample data to obtain N preset scenes.

Specifically, the classification algorithm of the scene classifier can be used to classify according to the feature information of the sample data, and then the sample data used for training can be divided into N categories, corresponding to N preset scenes.

Step S503: taking the sample data corresponding to each preset scenario as input, training the predictor, and obtaining a total of N independent performance prediction algorithms.

Specifically, the sample data divided into N categories in step S502 can be independently used for regression training of each performance prediction algorithm, thereby obtaining N performance prediction algorithms, that is, the N performance prediction algorithms correspond one-to-one to the N preset scenarios.

Step S504: determine whether the prediction error of the predictor meets the requirement.

Specifically, each performance prediction algorithm calculates the error for a corresponding group of sample data. When the predicted error meets the requirements, the iterative training process can directly jump to step S508 to output the classification algorithm and the performance prediction algorithm that meets the requirements; if the predicted error does not meet the requirements, the iterative training process can directly jump to step S505 to continue training and tuning.

Step S505: taking all sample data as input, using N performance prediction algorithms to make independent predictions, and calculating the prediction errors.

Specifically, all sample data are taken as input, and N performance prediction algorithms trained in step S503 are used to perform independent predictions on all sample data, and the error of each sample data under different performance prediction algorithms is calculated.

Step S506: regroup all sample data according to the predicted error.

Specifically, according to the error calculated in step S505, each sample data will be divided into a group with the smallest error. Based on this method, all sample data can be re-divided into N groups. It should be noted that in step S505, each sample data is independently predicted N times, and then the sample data will be divided into the group of the performance prediction algorithm corresponding to the prediction with the smallest error. Optionally, when all sample data are divided into the same group, the coefficients of the performance prediction algorithm can be adjusted, and all sample data can be independently predicted again until all sample data are finally divided into N groups, and the number of sample data in each group is relatively balanced, and there is no obvious quantity gap.

Step S507: retraining the classification algorithm of the scene classifier based on the regrouped sample data to obtain a new classification algorithm.

Specifically, the sample data regrouped in step S506 can be used as input to retrain the classification algorithm of the scene classifier, thereby obtaining a new classification algorithm. Optionally, after obtaining the new classification algorithm, the new classification algorithm obtained in step S507 can jump back to step S502, and then repeat the iterative process of step S502-step S503 until the error predicted in step S504 meets the error requirement, and the iteration ends.

Step S508: Output the classification algorithm of the scene classifier and the corresponding performance prediction algorithm.

Specifically, when the prediction error of the predictor meets the requirements, the classification algorithm of the trained scene classifier and the corresponding performance prediction algorithm can be output. Then, the classification algorithm and performance prediction algorithm can be used for DVFS control, and the processor and memory can be stabilized in real time at the balance point of performance and energy consumption while ensuring the accuracy of the classification algorithm and performance prediction algorithm, so as to achieve better energy efficiency control.

In a possible implementation, the above predictor can also be used to first obtain performance requirement information, the performance requirement information includes a preset range of the working parameters; then, based on the performance requirement information, the feature information and the target scenario, determine the working parameters of the processing system. See Figure 6, Figure 6 is a structural schematic diagram of another dynamic voltage and frequency adjustment device provided by an embodiment of the present application, wherein the predictor can also include a policy control unit, the policy control unit includes an interface for docking with the application unit of the terminal device, based on this interface, the policy control unit can obtain the performance requirement information of the application unit of the terminal device corresponding to the hardware, the performance requirement information can include performance constraints or power consumption constraints (for example, performance priority or energy consumption priority), based on the range of performance constraints or power consumption constraints, the range value of the working parameter (i.e., the preset range) can be determined. Understandably, the performance and power consumption requirements of the application unit can be configured to the policy control unit through the operating system interface, which simplifies the interface relationship between the upper software scheduler and the lower hardware and firmware. It should be noted that the policy control unit may not be integrated in the predictor, that is, the policy control unit may be a component independent of the predictor, and signaling interaction can be completed through an internal interface.

In a possible implementation, the dynamic voltage and frequency adjustment device provided in the embodiment of the present application may also include a collector, as shown in FIG7 , which is a schematic diagram of the structure of another dynamic voltage and frequency adjustment device provided in the embodiment of the present application. The dynamic voltage and frequency adjustment device may collect feature information of the instruction stream executed by the processing system (including the processor and/or the memory) through the collector, so that the scene classifier 110 and the sub-predictor 111 may obtain feature information of the instruction stream of the processing system (including processor events and/or memory events). Since the sub-predictor runs a performance prediction algorithm corresponding to each preset scene, the sub-predictor can predict the performance when the frequency and voltage of the current processing system are adjusted to the operating frequency and operating voltage based on its own performance prediction algorithm and feature information (it should be noted that each type of performance prediction algorithm will independently select its own processor event and memory event to predict the performance when the frequency and voltage of the current processing system are adjusted to the operating frequency and operating voltage). Furthermore, the predictor also includes a selector, which can select a target prediction result corresponding to the target scene from multiple prediction results based on the target scene output by the scene classifier 110, so as to more accurately predict the performance when the frequency and voltage of the current processing system are adjusted to the operating frequency and operating voltage. Optionally, the collector may include a processor event sampling unit and a memory event sampling unit, wherein the processor event sampling unit is used to collect information on various events of the processor, and the memory event sampling unit is used to collect information on various events of the memory. The collector can be processed by hardware or firmware, which can further obtain higher real-time performance. It is understandable that the collector can also be integrated into the scene classifier and the predictor, which is not specifically limited here.

To facilitate understanding of the DVFS strategy of the embodiment of the present application, an example is provided here as a reference, which does not constitute a specific limitation. Optionally, the preset scenarios in the scenario classifier can be divided according to the performance benefit interval after frequency reduction, for example, scenario one in which the performance benefit after frequency reduction is less than or equal to 0.72 of the performance before frequency reduction, scenario two in which the performance benefit after frequency reduction is greater than 0.72 of the performance before frequency reduction and less than or equal to 0.84 of the performance before frequency reduction, scenario three in which the performance benefit after frequency reduction is greater than 0.84 of the performance before frequency reduction and less than or equal to 0.96 of the performance before frequency reduction, and scenario four in which the performance benefit after frequency reduction is greater than 0.96 of the performance before frequency reduction; for different performance benefit scenarios, the predictor can give different decision directions, for example, for scenario one, the frequency can be increased, and the intensity of the increase is strong; for scenario two, the frequency can be increased, and the intensity of the increase is weak; for scenario three, the frequency can be reduced, and the intensity of the reduction is weak; for scenario four, the frequency can be reduced, and the intensity of the reduction is strong. Understandably, when evaluating the deviation of the predictor, classification can also be used for quantification, and the deviation situation is divided into 4 categories. For example, Perfect means a perfect match, that is, the direction (increase or decrease) is correct and the strength (strong or weak) is also correct; Good means a direction match, that is, the direction is correct but the strength is wrong; Bad means a direction error, that is, the direction is wrong but the strength is correct; Fatal means a fatal error, that is, the direction is wrong and the strength is also wrong. When the deviation between the result given by the predictor and the actual result is Fatal, the energy efficiency and performance of the computer system device will be lost; when the deviation is Perfect, the energy efficiency and performance of the computer system device will be improved.

In summary, in the embodiments of the present application, scenario classification and performance prediction can be performed based on the characteristic information of the instruction stream currently executed by the processing system (including the processor and/or memory) (such as event type, number of events, cache bandwidth, and number of cache misses, etc.), and DVFS can be accurately implemented, so that the processor and memory can be stabilized in real time at the balance point between performance and energy consumption, thereby obtaining better energy efficiency control.

The above describes the dynamic voltage frequency adjustment device of the embodiment of the present application. The following describes the related methods of the embodiment of the present application.

Please refer to FIG8, which is a flow chart of a dynamic voltage frequency adjustment method provided by an embodiment of the present application. The method can be applied to a terminal device, which can be the terminal device in FIG1a or FIG1b above. That is to say, the terminal device in FIG1a or FIG1b above can be used to support and execute the method flow steps S800 to S802 shown in FIG7, wherein steps S800 to S802 include the following:

Step S800: Acquire characteristic information of the instruction stream currently executed by the processing system, and determine a corresponding target scene from N preset scenes based on the characteristic information.

Step S801: determining operating parameters of the processing system based on the characteristic information and the target scenario, wherein the operating parameters include an operating frequency and an operating voltage.

Step S802: adjusting the current frequency and voltage of the processing system to the operating frequency and the operating voltage respectively.

Specifically, the processing system includes one or more of a processor and a memory, and the characteristic information includes one or more of an event type, a number of events, a cache bandwidth, a number of cache misses, and a number of cache access blockages; N is an integer greater than or equal to 2.

In one possible implementation, determining the operating parameters of the processing system based on the feature information and the target scenario includes: determining a target performance prediction algorithm corresponding to the target scenario from N performance prediction algorithms; the N performance prediction algorithms correspond one-to-one to the N preset scenarios; and determining the operating parameters of the processing system based on the feature information and the target performance prediction algorithm.

In one possible implementation, determining the operating parameters of the processing system based on the feature information and the target scenario includes: performing performance prediction on the feature information through N performance prediction algorithms to obtain N prediction results; the N performance prediction algorithms correspond one-to-one to the N preset scenarios; determining a target prediction result corresponding to the target scenario from the N prediction results; and the target prediction result includes the operating parameters of the processing system.

In one possible implementation, the method further includes: determining whether to adjust a classification algorithm used to determine the target scene in the scene classifier based on the working performance of the processing system when the processing system is at the working frequency and the working voltage; wherein, when the working performance of the processing system does not meet a preset condition, the classification algorithm is adjusted; and when the working performance of the processing system meets the preset condition, the classification algorithm is not adjusted.

In a possible implementation, the method further includes: performing training based on first sample data to obtain the N performance prediction algorithms; the first sample data includes feature information of sample instruction streams corresponding to the N performance prediction algorithms respectively.

In a possible implementation, the method further includes: performing training based on second sample data to obtain the N preset scenarios; the second sample data includes feature information of sample instruction streams corresponding to the N preset scenarios respectively.

In one possible implementation, determining the operating parameters of the processing system based on the characteristic information and the target scenario includes: obtaining performance requirement information, the performance requirement information including a preset range of the operating parameters; and determining the operating parameters of the processing system based on the performance requirement information, the characteristic information and the target scenario.

In an embodiment of the present application, scenario classification and performance prediction can be performed based on characteristic information (such as event type, number of events, cache bandwidth, and number of cache misses, etc.) of the instruction stream currently executed by the processing system (including a processor and/or memory), and DVFS can be accurately implemented, so that the processor and memory can be stabilized in real time at a balance point between performance and energy consumption, thereby obtaining better energy efficiency control.

It should be noted that the relevant description of the dynamic voltage frequency adjustment method process described in the embodiment of the present application can be found in the relevant description in the above-mentioned device embodiment, and will not be repeated here.

An embodiment of the present application further provides a computer-readable storage medium, in which a computer program code is stored. When the above-mentioned processor executes the computer program code, the computer executes the method in any of the above-mentioned embodiments.

The embodiment of the present application also provides a terminal device, which can exist in the form of a chip product, and the terminal device includes a processor, which is configured to support the terminal device to implement the corresponding functions of the method in any of the above embodiments. The terminal device may also include a memory, which is coupled to the processor and stores the necessary program instructions and data of the terminal device. The terminal device may also include a communication interface for the terminal device to communicate with other devices or communication networks.

The embodiment of the present application also provides a computer program product. When the computer program product is run on a computer, the computer executes the method in any of the aforementioned embodiments.

The embodiment of the present application provides a chip system, which includes a processor for supporting a device to implement the functions involved in the first aspect, for example, generating or processing the information involved in the dynamic voltage frequency adjustment method. In a possible design, the chip system also includes a memory, which is used to store program instructions and data necessary for the device. The chip system can be composed of a chip, or it can include a chip and other discrete devices.

In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

It should be noted that, for the above-mentioned method embodiments, for the sake of simplicity, they are all expressed as a series of action combinations, but those skilled in the art should be aware that the present application is not limited by the order of the actions described, because according to the present application, some steps may be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by the present application.

In the several embodiments provided in the present application, it should be understood that the disclosed devices can be implemented in other ways. For example, the device embodiments described above are only schematic, such as the division of the above-mentioned units, which is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, and the indirect coupling or communication connection of devices or units can be electrical or other forms.

The units described above as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the embodiments of the present application.

In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

If the above-mentioned integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions to enable a computer device (which can be a personal computer, a server or a network device, etc., specifically a processor in a computer device) to perform all or part of the steps of the above-mentioned methods of each embodiment of the present application. Among them, the aforementioned storage medium may include: U disk, mobile hard disk, magnetic disk, optical disk, read-only memory (Read-Only Memory, abbreviated: ROM) or random access memory (Random Access Memory, abbreviated: RAM) and other media that can store program codes.

As described above, the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, a person of ordinary skill in the art should understand that the technical solutions described in the aforementioned embodiments can still be modified, or some of the technical features therein can be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims (18)

1. A dynamic voltage frequency adjustment device, the device comprising:

A scene classifier for: acquiring characteristic information of an instruction stream currently executed by a processing system, and determining a corresponding target scene from N preset scenes based on the characteristic information; the processing system comprises one or more of a processor and a memory, wherein the characteristic information comprises one or more of event type, event number, cache bandwidth, cache miss times and cache access blocking numbers; n is an integer greater than or equal to 2;

a predictor for: determining an operating parameter of the processing system based on the characteristic information and the target scene, wherein the operating parameter comprises an operating frequency and an operating voltage;

a driver for: and respectively adjusting the current frequency and the current voltage of the processing system to the working frequency and the working voltage.

2. The apparatus of claim 1, wherein the predictor operates with N performance prediction algorithms, the N performance prediction algorithms corresponding one-to-one to the N preset scenes; the predictor is specifically configured to:

Determining a target performance prediction algorithm corresponding to the target scene from the N performance prediction algorithms;

And determining the working parameters of the processing system based on the characteristic information and the target performance prediction algorithm.

3. The apparatus of claim 2, wherein the predictor comprises a selector and N sub-predictors, the N sub-predictors being in one-to-one correspondence with N performance prediction algorithms, the N performance prediction algorithms being in one-to-one correspondence with the N preset scenes;

The predictor is specifically configured to:

Respectively carrying out performance prediction on the characteristic information through the N performance prediction algorithms corresponding to the N sub-predictors to obtain N prediction results;

Determining a target prediction result corresponding to the target scene from the N prediction results through the selector; the target prediction result includes the operating parameters of the processing system.

4. The apparatus according to any one of claim 1 to 3, further comprising a feedback unit,

The feedback unit is used for: determining whether to adjust a classification algorithm in the scene classifier for determining the target scene based on the operating performance of the processing system at the operating frequency and the operating voltage; when the working performance of the processing system does not meet a preset condition, the classification algorithm is adjusted; and when the working performance of the processing system meets the preset condition, not adjusting the classification algorithm.

5. The apparatus of any one of claims 1-4, wherein the predictor is further to:

training based on the first sample data to obtain the N performance prediction algorithms; the first sample data comprises characteristic information of sample instruction streams respectively corresponding to the N performance prediction algorithms.

6. The apparatus of any of claims 1-5, wherein the scene classifier is further to:

Training based on the second sample data to obtain the N preset scenes; the second sample data comprises characteristic information of sample instruction streams corresponding to the N preset scenes respectively.

7. The apparatus according to any of claims 1-6, wherein the predictor is specifically configured to:

Acquiring performance requirement information, wherein the performance requirement information comprises a preset range of the working parameters;

And determining the working parameters of the processing system based on the performance requirement information, the characteristic information and the target scene.

8. A method of dynamic voltage frequency adjustment, the method comprising:

acquiring characteristic information of an instruction stream currently executed by a processing system, and determining a corresponding target scene from N preset scenes based on the characteristic information; the processing system comprises one or more of a processor and a memory, wherein the characteristic information comprises one or more of event type, event number, cache bandwidth, cache miss times and cache access blocking numbers; n is an integer greater than or equal to 2;

Determining an operating parameter of the processing system based on the characteristic information and the target scene, wherein the operating parameter comprises an operating frequency and an operating voltage;

and respectively adjusting the current frequency and the current voltage of the processing system to the working frequency and the working voltage.

9. The method of claim 8, wherein the determining the operating parameters of the processing system based on the characteristic information and the target scene comprises:

Determining a target performance prediction algorithm corresponding to the target scene from N performance prediction algorithms; the N performance prediction algorithms are in one-to-one correspondence with the N preset scenes;

And determining the working parameters of the processing system based on the characteristic information and the target performance prediction algorithm.

10. The method of claim 8, wherein the determining the operating parameters of the processing system based on the characteristic information and the target scene comprises:

respectively carrying out performance prediction on the characteristic information through N performance prediction algorithms to obtain N prediction results; the N performance prediction algorithms are in one-to-one correspondence with the N preset scenes;

determining a target prediction result corresponding to the target scene from the N prediction results; the target prediction result includes the operating parameters of the processing system.

11. The method of any one of claims 8-10, wherein the method further comprises:

Determining whether to adjust a classification algorithm in the scene classifier for determining the target scene based on the operating performance of the processing system at the operating frequency and the operating voltage; when the working performance of the processing system does not meet a preset condition, the classification algorithm is adjusted; and when the working performance of the processing system meets the preset condition, not adjusting the classification algorithm.

12. The method of any one of claims 8-11, wherein the method further comprises:

training based on the first sample data to obtain the N performance prediction algorithms; the first sample data comprises characteristic information of sample instruction streams respectively corresponding to the N performance prediction algorithms.

13. The method of any one of claims 8-12, wherein the method further comprises:

Training based on the second sample data to obtain the N preset scenes; the second sample data comprises characteristic information of sample instruction streams corresponding to the N preset scenes respectively.

14. The method of any of claims 8-13, wherein the determining an operating parameter of the processing system based on the characteristic information and the target scene comprises:

Acquiring performance requirement information, wherein the performance requirement information comprises a preset range of the working parameters;

And determining the working parameters of the processing system based on the performance requirement information, the characteristic information and the target scene.

15. A computer readable storage medium comprising instructions which, when run on a computer, cause the computer to perform the method of any of claims 8-14.

16. A computer program comprising instructions which, when executed by a computer, cause the computer to perform the method of any of claims 8-14.

17. A terminal device comprising a processor and a memory, wherein the memory is configured to store program code which, when executed by the processor, implements the method of any of claims 8-14.

18. A chip system, comprising at least one processor, a memory and an interface circuit, wherein the memory, the interface circuit and the at least one processor are interconnected by a line, and wherein the at least one memory has instructions stored therein; the method of any of claims 8-14 being implemented when said instructions are executed by said processor.