CN118338647A

CN118338647A - Semiconductor structure and forming method thereof

Info

Publication number: CN118338647A
Application number: CN202310002800.6A
Authority: CN
Inventors: 唐怡
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2023-01-03
Filing date: 2023-01-03
Publication date: 2024-07-12
Also published as: WO2024146131A1

Abstract

A semiconductor structure and a forming method thereof, the forming method includes forming a stacked structure on a semiconductor substrate, the stacked structure including a plurality of first semiconductor layers arranged separately in a vertical direction and including a first active region, a channel region and a second active region in sequence in a first direction, the first semiconductor layers of the first and second active regions including a plurality of linear semiconductor patterns arranged separately in the second direction, the first semiconductor layer of the channel region having a plurality of first openings therein penetrating the first semiconductor layer in the vertical direction and arranged separately in the second direction, the first openings being located between the linear semiconductor patterns of the first active region and corresponding linear semiconductor patterns of the second active region; and forming a channel layer which is arranged along the second direction and a word line structure which extends along the second direction on the surface of the first semiconductor layer of the channel region along the first opening. The method reduces the difficulty in forming the word line structure.

Description

Semiconductor structure and forming method thereof

Technical Field

The present disclosure relates to the field of memory devices, and more particularly, to a semiconductor structure and a method of forming the same.

Background

Dynamic random access memory (Dynamic Random Access Memory, DRAM) is a semiconductor memory device commonly used in computers and consists of many repeated memory cells. Each memory cell typically includes a capacitor and a transistor having a gate connected to a word line, a drain connected to a bit line, and a source connected to the capacitor, a voltage signal on the word line being capable of controlling the transistor to turn on or off, thereby reading data information stored in the capacitor through the bit line, or writing data information to the capacitor through the bit line for storage.

To improve the integration level, the transistor in the existing 3D DRAM manufacturing process generally adopts a multi-layer stacked lateral transistor structure. When forming a multi-layered stacked lateral transistor structure on a semiconductor substrate, a word line structure covering a plurality of channel regions of the lateral transistor of each layer is generally formed, which is parallel to the surface of the semiconductor substrate, but is difficult in forming the lateral word line structure in the prior art.

Disclosure of Invention

Some embodiments of the present disclosure provide a method for forming a semiconductor structure, including:

Providing a semiconductor substrate;

Forming a stacked structure on the semiconductor substrate, wherein the stacked structure comprises a plurality of first semiconductor layers which are arranged in a discrete manner along a vertical direction, the stacked structure sequentially comprises a first active region, a channel region and a second active region along a first direction, the first semiconductor layers of the first active region and the second active region comprise a plurality of linear semiconductor patterns which are arranged in a discrete manner along a second direction, the first semiconductor layers of the channel region are provided with a plurality of first openings which penetrate through the first semiconductor layers along the vertical direction and are arranged in a discrete manner along the second direction, and the first openings are positioned between the linear semiconductor patterns of the first active region and the corresponding linear semiconductor patterns of the second active region; a width of the first opening along the first direction is smaller than a width of the channel region along the first direction, and a width of the first opening along the second direction is smaller than a width of the linear semiconductor pattern along the second direction;

And forming a channel layer which is arranged separately along the second direction and a word line structure which extends along the second direction on the surface of the first semiconductor layer of the channel region along the first opening.

In some embodiments, forming a stacked structure on the semiconductor substrate includes:

Forming a plurality of support protection columns which are arranged in a discrete manner along the second direction, wherein the support protection columns fill the first opening and cover the surface of a part of the first semiconductor layer around the first opening in the channel region; the width of the support protection column along the first direction is greater than or equal to the width of the channel region along the first direction;

And forming a first protection layer, wherein the first protection layer is positioned between a plurality of linear semiconductor patterns which are arranged in the first active region and the second active region in a discrete manner along a second direction and between adjacent support protection columns in the channel region, and the first direction is perpendicular to the second direction and is parallel to the upper surface of the semiconductor substrate.

In some embodiments, the forming, along the first opening, a channel layer arranged separately along the second direction and a word line structure extending along the second direction on a surface of the first semiconductor layer of the channel region includes:

Removing the support protection columns to form a plurality of second openings, wherein the second openings expose part of the surface of the first semiconductor layer around the first openings;

Forming channel layers which are arranged separately along the second direction on the surface of the first semiconductor layer exposed by the second opening by adopting an epitaxial growth process;

removing the first protection layer of the channel region, so that the first semiconductor layer and the channel layer of the channel region are suspended;

and forming a word line structure on the surface of the suspended first semiconductor layer and the surface of the channel layer.

Forming an initial stack structure on the semiconductor substrate, the initial stack structure including initial first semiconductor layers and second semiconductor layers alternately stacked in a vertical direction, the initial stack structure including the first active region, the channel region, and the second active region in sequence in a first direction;

Forming a plurality of first trenches penetrating the initial stacked structure in a vertical direction and extending in a first direction in the initial stacked structure of the first active region and the second active region, the initial first semiconductor layer remaining between adjacent ones of the first trenches in the first active region and the second active region as a linear semiconductor pattern;

And forming a first filling layer filling the first groove.

In some embodiments, forming support guard columns that are discretely arranged along the second direction includes:

Forming a plurality of first openings penetrating through the initial stacked structure in the vertical direction and being arranged in a discrete manner in a second direction in the initial stacked structure of the channel region, wherein the first openings are positioned between the linear semiconductor patterns of the first active region and the corresponding linear semiconductor patterns of the second active region in the first direction;

etching to remove part of the second semiconductor layer of the channel region along the first opening so as to form a second opening; a width of the second opening along the first direction is greater than or equal to a width of the channel region along the first direction, and a width of the second opening along the second direction is greater than or equal to a width of the linear semiconductor pattern along the second direction;

and forming a support protection column filling the second opening.

In some embodiments, forming the first protective layer includes:

removing the first filling layer in the first groove;

Removing the second semiconductor layer along the first trench to form a first void;

And filling the first groove and the first gap with a first protection layer.

In some embodiments, the forming of the word line structure includes:

Removing the first protection layer of the second active region and the first active region;

Forming a second protection layer at a position where the first protection layer is removed from the second active region and the first active region; the material of the second protective layer is different from that of the first protective layer;

After forming a second protective layer, removing the first protective layer of the channel region to form a cavity communicated with the first opening, so that the first semiconductor layer and the channel layer of the channel region are suspended;

Forming word line dielectric layers on the surfaces of the suspended first semiconductor layer and the channel layer;

And forming a metal word line material layer on the surface of the word line dielectric layer, the side wall surface of the cavity and the top surface of the stacked structure.

In some embodiments, the forming of the word line structure further comprises:

after forming the metal word line material layer, forming a word line isolation layer which fills the remaining first opening and cavity and covers the surface of the metal word line material layer of the channel region, wherein the material of the word line isolation layer is different from that of the second protection layer;

removing the metal word line material layer of the second active region and the first active region;

Removing the second protective layer of the second active region and the first active region, exposing the metal word line material layer on the side wall of the first groove, and suspending the linear semiconductor patterns of the second active region and the first active region;

and removing the metal word line material layer on the side wall of the first groove after removing the second protective layer, wherein the remaining metal word line material layer is used as a metal word line.

In some embodiments, the method further comprises:

And forming a first active layer on the surface of the linear semiconductor pattern in the first active region in an epitaxial manner, and forming a second active layer on the surface of the linear semiconductor pattern in the second active region in an epitaxial manner, wherein the first active layer and the second active layer are respectively connected with the channel layer.

In some embodiments, the first active layer and the second active layer are formed using a self-doping selective epitaxial process, and the first active layer and the second active layer are of a first doping type and the channel layer is of a second doping type.

In some embodiments, the method further comprises:

And forming side walls which extend along the second direction and surround part of the first active layer and the second active layer on two opposite sides of the channel layer along the first direction respectively.

In some embodiments, the method further comprises: forming a plurality of discrete bit lines electrically connected to the plurality of first active layers in the vertical direction; and forming capacitors electrically connected with the second active layers in a one-to-one correspondence.

Some embodiments of the present disclosure also provide a semiconductor structure, comprising:

A semiconductor substrate;

a stacked structure on the semiconductor substrate, wherein the stacked structure comprises a plurality of first semiconductor layers which are arranged separately along a vertical direction, the stacked structure sequentially comprises a first active region, a channel region and a second active region along a first direction, the first semiconductor layers of the first active region and the second active region comprise a plurality of linear semiconductor patterns which are arranged separately along a second direction, a word line isolation layer which penetrates through the first semiconductor layers along the vertical direction and extends along the second direction is arranged in the first semiconductor layers of the channel region, and a part of the word line isolation layer which penetrates through the first semiconductor layers is positioned between the linear semiconductor patterns of the first active region and the corresponding linear semiconductor patterns of the second active region;

A channel layer positioned on part of the surface of the first semiconductor substrate of the channel region, wherein adjacent channel layers are separated;

and the word line structure is positioned on the surface of the channel layer and the surface of the first semiconductor substrate of the channel region.

In some embodiments, the material of the channel layer is the same as or different from the material of the first semiconductor layer, and the material of the channel layer is Si or SiGe.

In some embodiments, the word line structure includes a word line dielectric layer on the channel layer surface and a first semiconductor substrate surface of the channel region and a metal word line on the word line dielectric layer.

In some embodiments, further comprising: a first active layer on the surface of the linear semiconductor pattern of the first active region, a second active layer on the surface of the linear semiconductor pattern of the second active region, the first active layer and the second active layer being respectively connected to the channel layer; a plurality of discrete bit lines electrically connecting the plurality of first active layers in a vertical direction; and capacitors electrically connected with the second active layers in a one-to-one correspondence.

In the method for forming a semiconductor according to the foregoing embodiments of the present application, a stacked structure is formed on a semiconductor substrate, a first semiconductor layer of a channel region of the stacked structure has a plurality of first openings penetrating the first semiconductor layer in a vertical direction and being arranged separately in a second direction, the first openings being located between a linear semiconductor pattern of the first active region and a corresponding linear semiconductor pattern of the second active region, a width of the first openings in the first direction being smaller than a width of the channel region in the first direction, and a width of the first openings in the second direction being smaller than a width of the linear semiconductor pattern in the second direction, a position of the first openings defining a position of a channel layer to be formed subsequently, the positions of the first openings are corresponding to each other, so that a channel layer can be formed, the plurality of openings are correspondingly formed to form a plurality of channel layers which can be arranged separately along the second direction, and therefore the first openings can be correspondingly formed to the channel regions of the plurality of transverse transistors, the first semiconductor layers of the channel regions are still connected together along the second direction by the specific width of the first openings, after the channel layers are formed subsequently, word line structures which extend along the second direction can be formed on the surfaces of the plurality of channel layers which are arranged along the second direction and the connected first semiconductor layers of the channel regions, and therefore, the process difficulty in forming the word line structures can be reduced, and defects such as short circuits caused by contact of the word line structures between the upper layer and the lower layer can be prevented.

Drawings

Fig. 1-38 are schematic structural diagrams illustrating a process of forming a semiconductor structure in some embodiments of the present disclosure.

Detailed Description

The following detailed description of specific embodiments of the present disclosure refers to the accompanying drawings. In describing embodiments of the present disclosure in detail, the schematic drawings are not necessarily to scale and are merely illustrative and are not intended to limit the scope of the disclosure. In addition, the spatial dimensions of length, width and depth should be included in actual fabrication.

Some embodiments of the present disclosure first provide a method for forming a semiconductor structure, which is described in detail below with reference to the accompanying drawings.

Referring to fig. 17-18, wherein fig. 18 is a schematic view of a cross-sectional structure along a cutting line AA1 in fig. 17, and fig. 18 is a schematic view of a cross-sectional structure along a cutting line BB1 in fig. 17, a method for forming a semiconductor structure includes: providing a semiconductor substrate 200; forming a stacked structure 201 on a semiconductor substrate 200, the stacked structure 201 including a plurality of first semiconductor layers 202 arranged separately in a vertical direction, the stacked structure 201 including a first active region 22, a channel region 21, and a second active region 23 in this order in a first direction, the first semiconductor layers 202 of the first active region 22 and the second active region 23 including a plurality of linear semiconductor patterns arranged separately in a second direction, the first semiconductor layers 202 of the channel region 21 having a plurality of first openings 206 extending through the first semiconductor layers 202 in the vertical direction and arranged separately in the second direction, the first openings 206 being located between the linear semiconductor patterns of the first active region 22 and the corresponding linear semiconductor patterns of the second active region 23; the width of the first opening 206 in the first direction is smaller than the width of the channel region 21 in the first direction, and the width of the first opening 206 in the second direction is smaller than the width of the linear semiconductor pattern in the second direction, and the first direction is perpendicular to the second direction and is parallel to the upper surface of the semiconductor substrate.

The material of the semiconductor substrate 200 may be single crystal silicon (Si), single crystal germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC); silicon On Insulator (SOI), germanium On Insulator (GOI); or may be other materials, such as III-V compounds based on gallium arsenide, etc. In this embodiment, the material of the semiconductor substrate 200 is single crystal silicon (Si).

The plurality of first semiconductor layers 202 are arranged separately in a vertical direction, and there is no direct contact between the first semiconductor layers 202 of adjacent layers. The vertical direction is a direction perpendicular to the upper surface of the semiconductor substrate 200.

The stacked structure 201 sequentially includes a first active region 22, a channel region 21, and a second active region 23 in a first direction, the first semiconductor layer 202 in the first active region 22 having a plurality of line-shaped semiconductor patterns discretely arranged in a second direction, and adjacent line-shaped semiconductor patterns are separated from each other by a first trench penetrating the stacked structure in the first active region 22 in a vertical direction and extending in the first direction. The first semiconductor layer 202 in the second active region 23 has a plurality of line-shaped semiconductor patterns discretely arranged in the second direction, and adjacent line-shaped semiconductor patterns are separated from each other by a first trench penetrating the stacked structure in the second active region 23 in the vertical direction and extending in the first direction.

The linear semiconductor pattern in the first active region 22 is subsequently used to form one of the source region and the drain region, and the linear semiconductor pattern in the second active region 23 is subsequently used to form the other of the source region or the drain region. In this embodiment, the linear semiconductor pattern in the first active region 22 is subsequently used to form a drain region, and the linear semiconductor pattern in the second active region 23 is subsequently used to form a source region.

The first semiconductor layer 202 of the channel region 21 is used for forming a carrier of the channel layer and the word line structure subsequently, the first semiconductor layer 202 of the channel region 21 is provided with a plurality of first openings 206 which penetrate through the first semiconductor layer 202 along the vertical direction and are arranged along the second direction in a discrete manner, the first openings 206 are positioned between the linear semiconductor patterns of the first active region 22 and the corresponding linear semiconductor patterns of the second active region 23, the width of the first openings 206 along the first direction is smaller than the width of the channel region 21 along the first direction, the width of the first openings 206 along the second direction is smaller than the width of the linear semiconductor patterns along the second direction, the positions of the first openings 206 define the positions of the channel layer formed subsequently, so that one channel layer can be formed corresponding to the position of each first opening 206, and the plurality of openings can be arranged along the second direction in a discrete manner corresponding to the plurality of channel layers formed in pairs, so that the first openings 206 can correspond to the channel regions of the plurality of lateral transistors, the first semiconductor layers 202 of the channel regions 21 are still connected together along the second direction by the specific width of the first openings 206, and after the channel layers are formed subsequently, word line structures extending along the second direction can be formed on the surfaces of the plurality of channel layers arranged along the second direction and on the connected first semiconductor layers 202 of the channel regions 21, thereby reducing the process difficulty in forming the word line structures and preventing the defects such as short circuits caused by the contact of the word line structures between the upper layer and the lower layer.

In some embodiments, the material of the first semiconductor layer 202 is Si, ge or SiGe, so that a channel layer is subsequently formed on the surface of the first semiconductor layer 202 around the first opening 206 by an epitaxial process. In this embodiment, the material of the first semiconductor layer 202 is SiGe, and when a channel layer of Si material is formed on the surface of the first semiconductor layer 202 around the first opening, the first semiconductor layer 202 of SiGe material can generate stress on the channel layer, so as to improve the mobility of carriers in the channel layer. The performance of the lateral transistor is improved.

In some embodiments, the first semiconductor layers 202 of adjacent layers and the first openings 206 of adjacent linear semiconductor layers are filled with the first protective layer 209, the first openings 206 adjacent in the second direction are separated by the first protective layer 209, the first openings 206 in the vertical direction are not filled with the first protective layer, and the width of the first protective layer 209 between the adjacent first openings 206 in the second direction is equal to or smaller than the width of the first trench in the second direction.

The formation of the stacked structure 201 is described in detail below in some embodiments in conjunction with fig. 1-30.

First, referring to fig. 1 to 2, wherein the left view in fig. 2 is a schematic cross-sectional structure along the direction of the cutting line AA1 of fig. 1, the right view in fig. 2 is a schematic cross-sectional structure along the direction of the cutting line BB1 of fig. 1, an initial stacked structure 221 is formed on the semiconductor substrate 200, the initial stacked structure 221 includes initial first semiconductor layers 222 and second semiconductor layers 223 alternately stacked in a vertical direction, and the initial stacked structure 221 includes a first active region 22, a channel region 21, and a second active region 23 in this order along the first direction.

The initial stacked structure 221 is subsequently used to form a stacked structure, and the initial first semiconductor layer 222 is subsequently used to form a first semiconductor layer or a linear semiconductor pattern.

The initial stacked structure 221 includes initial first semiconductor layers 222 and second semiconductor layers 223 alternately stacked in a vertical direction, the initial first semiconductor layers 222 and second semiconductor layers 223 alternately stacked referring to: after forming an initial first semiconductor layer 222 on the semiconductor substrate 200, forming a second semiconductor layer 223 on the surface of the initial first semiconductor layer 222, and then sequentially performing the steps of forming the initial first semiconductor layer 222 and the second semiconductor layer 223 on the initial first semiconductor layer 222 in a cyclic manner. The number of layers of the initial first semiconductor layer 222 and the second semiconductor layer 223 may be determined according to actual needs. In this embodiment, the initial first semiconductor layer 222 is four layers, the second semiconductor layer 223 is also four layers, and the bottom layer of the initial stack structure 221 is one initial first semiconductor layer 222, and the top layer of the initial stack structure 221 is one second semiconductor layer 223. In other embodiments, the number of layers of the initial first semiconductor layer 222 and the second semiconductor layer 223 may be other numbers.

The initial first semiconductor layer 222 and the second semiconductor layer 223 are both made of semiconductor materials, and the material of the initial first semiconductor layer 222 and the material of the second semiconductor layer 223 are different. In some embodiments, the material of the initial first semiconductor layer 222 and the second semiconductor layer 223 may be Si, ge, or SiGe. In this embodiment, the material of the initial first semiconductor layer 222 is SiGe, the thickness of each initial first semiconductor layer 222 is 5nm-50nm, the material of the second semiconductor layer 223 is Si, and the material of each second semiconductor layer 223 is 10nm-100nm. The initial first semiconductor layer 222 and the second semiconductor layer 223 are formed by a deposition process including an epitaxial process.

Referring to fig. 1 to 3, wherein fig. 3 is a diagram of a plurality of first trenches 204 formed in the first active region 22 and the second active region 23 through the initial stack structure 221 in a vertical direction and extending in a first direction after patterning the initial stack structure shown in fig. 1, and the initial first semiconductor layer remaining between adjacent first trenches 204 in the first active region 22 and the initial first semiconductor layer remaining between adjacent first trenches 204 in the second active region 23 are formed as a linear semiconductor pattern.

The plurality of first trenches 204 formed in the first active region 22 are arranged separately in the second direction, the plurality of first trenches 204 formed in the second active region 23 are arranged separately in the second direction, the first trenches 204 penetrate through the initial stacked structure 221 in the vertical direction and extend in the first direction, and the plurality of first trenches 204 are arranged in an array in the first direction and the second direction in the extending direction of the corresponding first trenches 204 of the first active region 22 located in the second active region 23.

After the first trench 204 is formed, the initial first semiconductor layer 222 and the second semiconductor layer 223 of the first active region 22 are disconnected in the second direction, the initial first semiconductor layer 222 and the second semiconductor layer 223 of the second active region 23 are disconnected in the second direction, and the disconnected initial first semiconductor layer 222 of the first active region 22 and the second active region 23 serve as a linear semiconductor pattern so that a plurality of discrete first active regions are formed in correspondence with a plurality of discrete linear semiconductor patterns of the first active region 22, and the initial first semiconductor layer 222 and the second semiconductor layer 223 in the channel region 21 remain as an integral structure in the second direction.

Referring to fig. 3-4, a first fill layer 205 is formed that fills the first trench 204.

The material of the first filling layer 205 is different from the material of the second semiconductor layer 223. In an embodiment, the material of the first filling layer 205 is one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, FSG (fluorine doped silicon dioxide), BSG (boron doped silicon dioxide), PSG (phosphorus doped silicon dioxide) or BPSG (boron doped silicon dioxide), and low dielectric constant (K is less than 2.5). In this embodiment, the material of the first filling layer 205 is silicon oxide.

Referring to fig. 5 to 6, wherein the left view of fig. 6 is a schematic cross-sectional structure along the direction of the cutting line AA1 of fig. 5, the right view of fig. 6 is a schematic cross-sectional structure along the direction of the cutting line BB1 of fig. 5, a plurality of first openings 206 penetrating the initial stacked structure in the vertical direction and being discretely arranged along the second direction are formed in the initial stacked structure 221 of the channel region 21, and in the first direction, the first openings 206 are located between the linear semiconductor patterns of the first active region 22 and the corresponding linear semiconductor patterns of the second active region 23, and the linear semiconductor patterns of the first active region 22 and the corresponding linear semiconductor patterns of the second active region 23 are adjacent along the first direction.

In the initial stacked structure 221 of the channel region 21, a plurality of first openings 206 penetrating the initial stacked structure in a vertical direction and being discretely arranged in a second direction are formed using an anisotropic dry etching process, including an anisotropic plasma etching process.

The width of the formed first openings 206 along the first direction is smaller than the width of the channel regions 21 along the first direction, the width of the first openings 206 along the second direction is smaller than the width of the linear semiconductor patterns along the second direction, the positions of the first openings 206 define the positions of the subsequently formed channel layers, so that one channel layer can be formed corresponding to the positions of each first opening 206, the plurality of openings can be arranged in a separated mode along the second direction correspondingly to form a plurality of channel layers, the channel regions of the plurality of transverse transistors can be corresponding to the plurality of channel layers, the specific width of the first openings 206 enables the initial first semiconductor layers 222 of the channel regions 21 to be still connected together along the second direction, after the channel layers are formed subsequently, word line structures extending along the second direction can be formed on the surfaces of the plurality of channel layers arranged along the second direction and the connected initial first semiconductor layers 222 (or the subsequent first semiconductor layers) of the channel regions 21, therefore the process difficulty in forming word line structures can be reduced, and the defect that the word line structures are in contact with each other can be prevented.

Referring to fig. 5 to 8, wherein the left view of fig. 8 is a schematic cross-sectional structure along the direction of the cutting line AA1 in fig. 7, and the right view of fig. 8 is a schematic cross-sectional structure along the direction of the cutting line BB1 in fig. 7, a portion of the second semiconductor layer 223 of the channel region 21 is etched away along the first opening 206 to form a second opening 207; the width of the second opening 207 in the first direction is greater than or equal to the width of the channel region 21 in the first direction, and the width of the second opening 207 in the second direction is greater than or equal to the width of the linear semiconductor pattern in the second direction.

In some embodiments, before etching to remove the second semiconductor layer 223 of a portion of the channel region 21 along the first opening, a patterned mask layer (not shown) is formed on the surface of the initial stacked structure 221, where the patterned mask layer has a mask opening therein exposing the first opening 206 and a portion of the second semiconductor layer 223 of the channel region 21 around the first opening 206, a width of the mask opening along the first direction is greater than or equal to a width of the channel region 21 along the first direction, and a width of the mask opening along the second direction is greater than or equal to a width of the linear semiconductor pattern along the second direction; etching to remove part of the second semiconductor layer 223 of the channel region 21 along the mask opening and the first opening 206 by using the patterned mask layer as a mask to form a second opening 207, wherein the formed second opening 207 comprises the first opening 206 and a space formed after removing part of the second semiconductor layer 223; and removing the patterned mask layer.

Portions of the second semiconductor layer 223 of the channel region 21 are etched away along the mask opening and the first opening 206 using an isotropic wet etch process that uses an etching solution that etches the second semiconductor layer material at a much greater rate than the initial first semiconductor layer material.

The width of the second opening formed by forming the second opening 207 in the first direction is greater than or equal to the width of the channel region 21 in the first direction, and the width of the second opening 207 in the second direction is greater than or equal to the width of the line-shaped semiconductor pattern in the second direction, the second opening 207 subsequently defining the position of the support protection post and the position of the channel layer.

Referring to fig. 9 to 10, wherein the left side of fig. 10 is a schematic cross-sectional structure along the direction of the cutting line AA1 in fig. 9, and the right side of fig. 10 is a schematic cross-sectional structure along the direction of the cutting line BB1 in fig. 9, the support and protection column 208 filling the second opening is formed.

The support and protection pillars 208 serve to support the initial stacked structure in a subsequent process, on the one hand, and protect the initial first semiconductor layer 222 of the trench region 21 from damage or contamination, on the other hand.

The material of the support guard post 208 is different from that of the first filling layer 205 and the second semiconductor layer 223, and then the etching rate of the support guard post 208 is small when the first filling layer 205 and the second semiconductor layer 223 are removed, so that the support guard post 208 is not etched or etched by a small amount.

In one embodiment, the material of the support guard post 208 is silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, or amorphous carbon. In this embodiment, the material of the support guard post 208 is silicon nitride, and the support guard post 208 is formed by a deposition and planarization process.

The plurality of support and protection pillars 208 are arranged separately along the second direction, the support and protection pillars 208 fill the second openings 207, or the support and protection pillars 208 fill the first openings 206 and cover a portion of the surface of the first semiconductor layer around the first openings 206 in the channel region 21, and the width of the support and protection pillars 208 along the first direction is greater than or equal to the width of the channel region along the first direction, and the width of the support and protection pillars 208 along the second direction is greater than or equal to the width of the linear semiconductor pattern along the second direction.

Referring to fig. 11-12, wherein the left side of fig. 12 is a schematic cross-sectional structure along the direction of the cutting line AA1 in fig. 11, and the right side of fig. 12 is a schematic cross-sectional structure along the direction of the cutting line BB1 in fig. 11, the first filling layer 205 in the first trench is removed (refer to fig. 9).

The removal of the first fill layer 205 employs an isotropic wet etch process. The first filling layer 205 is removed and then the first trench 204 is leaked again.

Referring to fig. 13 to 14, wherein the left view in fig. 14 is a schematic cross-sectional structure along the direction of the cutting line AA1 in fig. 13, and the right view in fig. 14 is a schematic cross-sectional structure along the direction of the cutting line BB1 in fig. 13, the remaining second semiconductor layer 223 is removed along the first trench 204 to form a first void.

And removing the second semiconductor layer by adopting an isotropic wet etching process. After the second semiconductor layer is removed, the linear semiconductor patterns (or the remaining initial first semiconductor layer 222) of the first and second active regions 22 and 23 are suspended, and the remaining initial first semiconductor layer 222 of the channel region 21 is supported by the support guard post 208.

Referring to fig. 15 to 16, the left view in fig. 16 is a schematic cross-sectional structure along the direction of the cutting line AA1 in fig. 15, and the right view in fig. 16 is a schematic cross-sectional structure along the direction of the cutting line BB1 in fig. 15, where the first trench and the first void are filled with the first protection layer 209.

The first protection layer 209 is used to support the initial stacked structure in a subsequent process and to protect the linear semiconductor patterns (or the remaining initial first semiconductor layer 222) of the first and second active regions 22 and 23 in a subsequent process, and redefine the positions of the first and second openings when the support and protection pillars 208 are removed later.

After the first trenches and the first gaps are filled with the first protective layer 209, the first protective layer 209 is formed between the plurality of line-shaped semiconductor patterns which are separately arranged in the second direction in the first active region 22 and the second active region 23 and between adjacent support guard posts 208 in the channel region 21.

The material of the first protective layer 209 is different from the material of the support guard post 208 so that the etching amount of the first protective layer 209 is small or negligible when the support guard post 208 is subsequently removed. In an embodiment, the material of the first filling layer 205 is one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, FSG (fluorine doped silicon dioxide), BSG (boron doped silicon dioxide), PSG (phosphorus doped silicon dioxide) or BPSG (boron doped silicon dioxide), and low dielectric constant (K is less than 2.5). In this embodiment, the material of the first protection layer 209 is silicon oxide, and the process of forming the first protection layer 209 includes deposition and planarization processes.

Referring to fig. 17 to 18, wherein the left view in fig. 18 is a schematic cross-sectional structure along the direction of the cutting line AA1 in fig. 17, and the right view in fig. 18 is a schematic cross-sectional structure along the direction of the cutting line BB1 in fig. 17, the support guard post is removed, and the first opening 206 and the second opening 207 are exposed.

And removing the supporting protection column by adopting an isotropic wet etching process. The spatial regions formed after the support protection columns are removed are all used as the second openings 207, and the accuracy of the positions of the channel layers formed by subsequent epitaxy can be better controlled through the second openings 207.

After the support protection post is removed, taking the remaining initial first semiconductor layer as a first semiconductor layer 202, forming a stacked structure 201, wherein the stacked structure 201 comprises a plurality of layers of first semiconductor layers 202 which are arranged separately along a vertical direction, the stacked structure 201 sequentially comprises a first active region 22, a channel region 21 and a second active region 23 along a first direction, the first semiconductor layers 202 of the first active region 22 and the second active region 23 comprise a plurality of linear semiconductor patterns which are arranged separately along a second direction, the first semiconductor layers 202 of the channel region 21 are provided with a plurality of first openings 206 which penetrate through the first semiconductor layers 202 along the vertical direction and are arranged separately along the second direction, and the first openings 206 are positioned between the linear semiconductor patterns of the first active region 22 and the corresponding linear semiconductor patterns of the second active region 23; the width of the first opening 206 in the first direction is smaller than the width of the channel region 21 in the first direction, and the width of the first opening 206 in the second direction is smaller than the width of the linear semiconductor pattern in the second direction, and the first direction is perpendicular to the second direction and is parallel to the upper surface of the semiconductor substrate; the linear semiconductor patterns of the first active region 22 and the second active region 23 are filled with a first protective layer 209, and the channel region 21 is separated by the first protective layer 209 between adjacent first openings 206 (or second openings 207) in the second direction.

After forming the stack structure, a process of forming a channel layer and a word line structure is performed subsequently.

Referring to fig. 19 to 20, wherein the left view of fig. 20 is a schematic cross-sectional structure along the direction of the cutting line AA1 in fig. 19, and the right view of fig. 20 is a schematic cross-sectional structure along the direction of the cutting line BB1 in fig. 19, a channel layer 210 is formed on the surface of the first semiconductor layer 202 exposed by the second opening 207, the channel layer being discretely arranged along the second direction, using an epitaxial growth process.

The channel layer 210 is formed as a channel region of a lateral transistor. The plurality of channel layers 210 are discrete along the second direction. The channel layer 210 may be doped with a certain impurity ion, which may be an N-type impurity ion or a P-type impurity ion, as needed. In some embodiments, the P-type impurity ions are one or more of boron, gallium and indium, and the N-type impurity ions include one or more of phosphorus, arsenic and antimony.

The channel layer 210 is formed by adopting an epitaxial growth process, and the epitaxial growth process comprises a self-doping selective epitaxial process, so that the channel layer 210 can be formed on the surface of the first semiconductor layer 202 exposed by the second opening 207 in a self-aligned and selective manner, and certain impurity ions are doped in the formed channel layer 210 at the same time, thereby simplifying the process and improving the position accuracy of the formed channel layer 210.

The material of the channel layer 210 may be the same as or different from the material of the first semiconductor layer 202, and in some embodiments, the material of the channel layer 210 may be Si, ge, or SiGe. In this embodiment, the material of the channel layer 210 is different from the material of the first semiconductor layer 202, and the material of the channel layer 210 is Si.

Referring to fig. 21 to 22, wherein the left view of fig. 22 is a schematic cross-sectional structure along the direction of the cutting line AA1 in fig. 21, and the right view of fig. 22 is a schematic cross-sectional structure along the direction of the cutting line BB1 in fig. 21, the second active region 23 and the first protection layer of the first active region 21 are removed, and the first protection layer 209 of the channel region 21 is remained.

The first protection layer removing the second active region 23 and the first active region 21 may employ a wet etching process or a dry etching process.

In some embodiments, a mask layer is formed on the surfaces of the first protection layer 209 and the channel layer 210 of the channel region 21 before removing the first protection layers of the second active region 23 and the first active region 22; taking the mask layer as a mask, removing the first protection layers of the second active region 23 and the first active region 21; the mask layer may be removed after the second protective layer is subsequently formed.

The purpose of the first protective layer 209 that retains the channel region 21 is: the subsequent second active region 23 and the first active region 22 form a second protective layer, so that the plurality of first semiconductor layers 202 in the channel region 21 and the plurality of channel layers 210 located on the first semiconductor layers 202 of the respective layers can be suspended after the remaining first protective layer of the channel region 21 is removed, so that a word line structure extending in the second direction is subsequently formed on the first semiconductor layer 202 of each layer.

Referring to fig. 23 to 24, wherein the left view of fig. 24 is a schematic cross-sectional structure along the direction of the cutting line AA1 in fig. 23, and the right view of fig. 24 is a schematic cross-sectional structure along the direction of the cutting line BB1 in fig. 23, a second protective layer 211 is formed at a position where the first protective layer is removed from the second active region 23 and the first active region 22; the material of the second protection layer 211 is different from that of the first protection layer 209.

The material of the second protection layer 211 is different from that of the first protection layer 209, so that the etching amount of the second protection layer 211 is small or negligible when the first protection layer 209 is removed later. In an embodiment, the material of the second protection layer 211 is one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, FSG (fluorine doped silicon dioxide), BSG (boron doped silicon dioxide), PSG (phosphorus doped silicon dioxide) or BPSG (boron phosphorus doped silicon dioxide), and low dielectric constant (K is less than 2.5). In this embodiment, the material of the second protection layer 211 is silicon nitride, and the process of forming the second protection layer 211 includes deposition and planarization processes.

Referring to fig. 25 to 26, wherein the left view of fig. 26 is a schematic cross-sectional structure along the direction of the cutting line AA1 in fig. 25, and the right view of fig. 26 is a schematic cross-sectional structure along the direction of the cutting line BB1 in fig. 25, after the second passivation layer 211 is formed, the first passivation layer 209 (refer to fig. 19) of the channel region 21 is removed, and a cavity communicating with the first opening (or the second opening) is formed, so that the first semiconductor layer 202 and the channel layer 210 of the channel region 21 are suspended.

The first protective layer 209 removing the channel region 21 may employ an isotropic dry etching process or a wet etching process.

Referring to fig. 27-28, wherein the left side of fig. 28 is a schematic cross-sectional structure along the direction of the cutting line AA1 in fig. 27, and the right side of fig. 28 is a schematic cross-sectional structure along the direction of the cutting line BB1 in fig. 27, a word line structure film 212 is formed on the surface of the suspended first semiconductor layer 202 and the channel layer 210.

The word line structure film 212 includes a word line dielectric layer (not shown) formed on the surface of the suspended first semiconductor layer 202 and the channel layer 210, and a metal word line material layer (not shown) formed on the surface of the word line dielectric layer, the sidewall surfaces of the cavity, and the top surface of the stacked structure. The word line structure film 212 is subsequently used to form a word line structure extending in the second direction, the word line structure including a word line dielectric layer and a metal word line on the word line dielectric layer.

In some embodiments, the word line dielectric layer may be silicon oxide or a high K (K greater than 2.5) dielectric material. The high K (K greater than 2.5) dielectric material may be HfO₂、TiO₂、HfZrO、HfSiNO、Ta₂O₅、ZrO₂、ZrSiO₂、Al₂O₃、SrTiO₃ or BaSrTiO.

In some embodiments, the material of the metal word line may be one or more of Al, cu, ag, au, pt, ni, ti, tiN, taN, ta, taC, taSiN, W, WN, wsi

In some embodiments, the forming of the word line structure may include: forming a word line dielectric layer (not shown) on the surface of the suspended first semiconductor layer 202 and the channel layer 210; forming a metal word line material layer (not shown) on the surface of the word line dielectric layer, the sidewall surface of the cavity, and the top surface of the stacked structure; after the metal word line material layer is formed, a word line isolation layer which fills the remaining first opening and the cavity and covers the surface of the metal word line material layer of the channel region is formed subsequently, and the material of the word line isolation layer is different from that of the second protection layer; removing the metal word line material layer of the second active region and the first active region; removing the second protective layer of the second active region and the first active region, exposing the metal word line material layer on the side wall of the first groove, and suspending the linear semiconductor patterns of the second active region and the first active region; and removing the metal word line material layer on the side wall of the first groove after removing the second protective layer, wherein the remaining metal word line material layer is used as a metal word line. The foregoing part of the word line structure process will be described in detail with reference to the accompanying drawings.

Referring to fig. 29 to 30, wherein the left view of fig. 30 is a schematic cross-sectional structure along the direction of the cutting line AA1 in fig. 29, the right view of fig. 30 is a schematic cross-sectional structure along the direction of the cutting line BB1 in fig. 29, after forming the metal word line material layer (or the word line structure film 212), forming a word line isolation layer 213 filling the remaining first opening 206 and cavity and covering the metal word line material layer surface of the channel region 21, wherein the material of the word line isolation layer 213 is different from the material of the second protection layer 211; the metal word line material layer (or word line structure film 212) of the second active region 23 and the first active region 22 is removed.

In one embodiment, the material of the word line isolation layer 213 is one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, FSG (fluorine doped silicon dioxide), BSG (boron doped silicon dioxide), PSG (phosphorus doped silicon dioxide) or BPSG (boron phosphorus doped silicon dioxide), and low dielectric constant (K is less than 2.5). In this embodiment, the material of the word line isolation layer 213 is silicon oxide, and the process of forming the word line isolation layer 213 includes deposition and planarization processes.

Referring to fig. 31 to 32, wherein the left view of fig. 32 is a schematic cross-sectional structure along the direction of the cutting line AA1 in fig. 31, and the right view of fig. 32 is a schematic cross-sectional structure along the direction of the cutting line BB1 in fig. 31, removing the second protection layer 211 (refer to fig. 30) of the second active region 23 and the first active region 22, exposing the metal word line material layer (or the word line structure film 212) of the sidewall of the first trench 204, and suspending the linear semiconductor pattern (202) of the second active region 23 and the first active region 22; after the second protective layer is removed, the metal word line material layer on the sidewall of the first trench is removed, and the remaining metal word line material layer is used as a metal word line, or the remaining word line structure film 212 is used as a word line structure.

The removal of the second protective layer 211 of the second active region 23 and the first active region 22 and the removal of the metal word line material layer of the first trench sidewall may employ an isotropic dry etching process or an isotropic wet etching process.

The formed word line structures extend in the second direction and the word line structures on the surfaces of the first semiconductor layers 202 of the different layer pairs are separated from each other.

Referring to fig. 33 to 34, wherein the left view of fig. 34 is a schematic cross-sectional structure along the direction of the cutting line AA1 in fig. 33, the right view of fig. 34 is a schematic cross-sectional structure along the direction of the cutting line BB1 in fig. 33, a first active layer 214 is formed on the surface of the suspended linear semiconductor pattern in the first active region 22, a second active layer 215 is formed on the surface of the suspended linear semiconductor pattern in the second active region 23, and the first active layer 214 and the second active layer 215 are respectively connected to the channel layer 210.

The first active region 214 serves as one of the source region and the drain region, and the second active layer 215 serves as the other of the source region and the drain region. In this embodiment, the first active region 214 is used as a drain region, and the second active region 215 is used as a source region.

In some embodiments, the material of the first active region 214 and the second active region 215 may be Si, ge, or SiGe. In this embodiment, the material of the first active region 214 and the second active region 215 is Si.

The first active region 214 and the second active region 215 are doped with the same type of impurity ions, which may be N-type impurity ions or P-type impurity ions. In some embodiments, the P-type impurity ions are one or more of boron, gallium and indium, and the N-type impurity ions include one or more of phosphorus, arsenic and antimony. The first and second active layers 214, 214 are of a first doping type and the channel layer 210 is of a second doping type, and in some embodiments the types of impurity ions doped in the first and second active regions 214, 215 are opposite to the types of impurity ions doped in the channel layer 210, i.e., the first and second doping types are opposite. In some embodiments, the type of impurity ions doped in the first and second active regions 214 and 215 may also be the same as the type of impurity ions doped in the channel layer 210, i.e., the first and second doping types may be the same.

In some embodiments, the first active layer 214 and the second active layer 215 are formed using a self-doping selective epitaxial process.

Referring to fig. 35 to 36, wherein the left view of fig. 36 is a schematic cross-sectional structure along the direction of the cutting line AA1 in fig. 35, and the right view of fig. 36 is a schematic cross-sectional structure along the direction of the cutting line BB1 in fig. 35, side walls 217 extending along the second direction and surrounding portions of the first active layer 214 and the second active layer 215 are formed on opposite sides of the channel layer 210 along the first direction, respectively.

The side wall 217 is used for supporting the linear semiconductor pattern (202).

The material of the side wall 217 may be one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, and silicon carbonitride. In this embodiment, the material of the side wall 2174 is silicon nitride, and the process of forming the side wall 217 includes deposition and etching processes.

Referring to fig. 37-38, wherein the left view of fig. 38 is a schematic cross-sectional structure of fig. 37 along the direction of the cutting line AA1, and the right view of fig. 38 is a schematic cross-sectional structure of fig. 37 along the direction of the cutting line BB1, the method further comprises: forming a plurality of discrete bit lines 218, the bit lines 218 being electrically connected to the plurality of first active layers 214 in a vertical direction; capacitors 219 are formed to be electrically connected to the second active layers 215 in one-to-one correspondence.

The material of the bit line 218 is a metal, which may be one or more of Al, cu, ag, au, pt, ni, ti, tiN, taN, ta, taC, taSiN, W, WN, WSi.

In some embodiments, a metal silicide may be formed on the surface of the first active layer 214 before forming the bit line 218, wherein the metal silicide is one of nickel silicide, tungsten silicide, cobalt silicide, tantalum silicide, titanium silicide, or a combination thereof.

Some embodiments of the present application also provide a semiconductor structure, referring to fig. 37-38, comprising:

A semiconductor substrate 200;

A stacked structure 201 on the semiconductor substrate 200, the stacked structure 201 including a plurality of first semiconductor layers 202 arranged separately in a vertical direction, the stacked structure including a first active region 22, a channel region 21, and a second active region 23 in this order in a first direction 201, the first semiconductor layers 202 of the first active region 21 and the second active region 22 including a plurality of linear semiconductor patterns arranged separately in a second direction, the first semiconductor layers of the channel region 21 having a word line isolation layer 213 extending in the second direction and penetrating the first semiconductor layers in the vertical direction, a portion of the word line isolation layer 213 penetrating the first semiconductor layers 202 being located between the linear semiconductor patterns of the first active region 22 and the corresponding linear semiconductor patterns of the second active region 23;

a channel layer 210 on a portion of the surface of the first semiconductor substrate 202 of the channel region 21, adjacent channel layers 210 being discrete;

A word line structure 212 is located on the surface of the channel layer 210 and on the surface of the first semiconductor substrate 202 of the channel region 21.

In some embodiments, the material of the channel layer 210 is the same as or different from the material of the first semiconductor layer 202, and the material of the channel layer 210 is Si or SiGe.

In some embodiments, the word line structure 212 includes a word line dielectric layer on the surface of the channel layer and the first semiconductor substrate surface of the channel region and a metal word line on the word line dielectric layer.

In some embodiments, further comprising: a first active layer 214 on the linear semiconductor pattern surface of the first active region 22, a second active layer 215 on the linear semiconductor pattern surface of the second active region 23, the first active layer 214 and the second active layer 215 being connected to the channel layer 210, respectively; a plurality of discrete bit lines 218, the bit lines 218 electrically connecting the plurality of first active layers 214 in the vertical direction; the capacitors 219 are electrically connected to the second active layer 215 in one-to-one correspondence.

It should be noted that, in some embodiments of the foregoing semiconductor structure, the same or similar parts as those in some embodiments of the foregoing semiconductor structure forming method are not described herein in detail, and reference is made to the definition or description of the corresponding parts in some embodiments of the foregoing semiconductor structure forming method.

Although the present disclosure has been described in terms of the preferred embodiments, it is not intended to limit the disclosure, and any person skilled in the art may make any possible variations and modifications to the disclosed solution using the methods and techniques disclosed above without departing from the spirit and scope of the disclosure, so any simple modifications, equivalent variations and modifications to the above embodiments according to the technical principles of the present disclosure fall within the scope of the disclosure.

Claims

1. A method of forming a semiconductor structure, comprising:

Providing a semiconductor substrate;

2. The method of forming a semiconductor structure of claim 1, wherein forming a stacked structure on the semiconductor substrate comprises:

3. The method of forming a semiconductor structure according to claim 2, wherein the forming a channel layer arranged separately in the second direction and a word line structure extending in the second direction along the first opening on a surface of the first semiconductor layer of the channel region comprises:

4. The method of claim 2, wherein forming a stacked structure on the semiconductor substrate comprises:

Forming an initial stack structure on the semiconductor substrate, the initial stack structure including initial first semiconductor layers and second semiconductor layers alternately stacked in a vertical direction, the initial stack structure including the first active region, the channel region, and the second active region in sequence in a first direction; forming a plurality of first trenches penetrating the initial stacked structure in a vertical direction and extending in a first direction in the initial stacked structure of the first active region and the second active region, the initial first semiconductor layer remaining between adjacent ones of the first trenches in the first active region and the second active region as a linear semiconductor pattern;

And forming a first filling layer filling the first groove.

5. The method of forming a semiconductor structure of claim 4, wherein forming support guard columns that are discretely arranged along the second direction comprises:

and forming a support protection column filling the second opening.

6. The method of forming a semiconductor structure of claim 4, wherein forming a first protective layer comprises:

removing the first filling layer in the first groove;

And filling the first groove and the first gap with a first protection layer.

7. The method of forming a semiconductor structure of claim 4, wherein the forming of the word line structure comprises:

Forming word line dielectric layers on the surfaces of the suspended first semiconductor layer and the suspended channel layer;

8. The method of forming a semiconductor structure of claim 7, wherein the forming of the word line structure further comprises:

9. The method of forming a semiconductor structure of claim 1, further comprising:

10. The method of claim 9, wherein the first active layer and the second active layer are formed using a self-doping selective epitaxy process, and wherein the first active layer and the second active layer are of a first doping type and the channel layer is of a second doping type.

11. The method of forming a semiconductor structure of claim 10, further comprising:

12. The method of forming a semiconductor structure of claim 9, further comprising: forming a plurality of discrete bit lines electrically connected to the plurality of first active layers in the vertical direction; and forming capacitors electrically connected with the second active layers in a one-to-one correspondence.

13. A semiconductor structure, comprising:

A semiconductor substrate;

14. The semiconductor structure of claim 13, wherein the material of the channel layer is the same as or different from the material of the first semiconductor layer, and wherein the material of the channel layer is Si or SiGe.

15. The semiconductor structure of claim 13, wherein the word line structure comprises a word line dielectric layer on the channel layer surface and a first semiconductor substrate surface of the channel region and a metal word line on the word line dielectric layer.

16. The semiconductor structure of claim 13, further comprising: a first active layer on the surface of the linear semiconductor pattern of the first active region, a second active layer on the surface of the linear semiconductor pattern of the second active region, the first active layer and the second active layer being respectively connected to the channel layer; a plurality of discrete bit lines electrically connecting the plurality of first active layers in a vertical direction; and capacitors electrically connected with the second active layers in a one-to-one correspondence.